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Viewing changes to updates/cw-3.6/linux-next-cherry-picks/0047-ath9k_hw-Add-AR9565-HW-support.patch

  • Committer: Package Import Robot
  • Author(s): Leann Ogasawara
  • Date: 2012-10-10 22:28:55 UTC
  • Revision ID: package-import@ubuntu.com-20121010222855-qepocc61xktv6gs9
Tags: 3.5.0-17.1
https://launchpad.net/bugs/1066123
* Open Quantal LBM
* Add compat-wireless 3.6
  -LP: #1066123

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updates/cw-3.6/linux-next-cherry-picks/0047-ath9k_hw-Add-AR9565-HW-support.patch
 
1
From a4a2954ff49e72ce3fa1f78a156b2492a023c89d Mon Sep 17 00:00:00 2001
 
2
From: Sujith Manoharan <c_manoha@qualcomm.com>
 
3
Date: Mon, 10 Sep 2012 09:20:03 +0530
 
4
Subject: [PATCH] ath9k_hw: Add AR9565 HW support
 
5
 
 
6
Various parts of the code require AR9565 checks,
 
7
this patch adds them.
 
8
 
 
9
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
 
10
Signed-off-by: John W. Linville <linville@tuxdriver.com>
 
11
---
 
12
 drivers/net/wireless/ath/ath9k/ani.c           |  2 +-
 
13
 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | 10 +++++-----
 
14
 drivers/net/wireless/ath/ath9k/ar9003_mac.c    |  2 +-
 
15
 drivers/net/wireless/ath/ath9k/ar9003_phy.c    | 10 +++++-----
 
16
 drivers/net/wireless/ath/ath9k/ar9003_phy.h    | 14 +++++++-------
 
17
 drivers/net/wireless/ath/ath9k/eeprom.h        |  2 +-
 
18
 drivers/net/wireless/ath/ath9k/hw.c            | 20 +++++++++++---------
 
19
 7 files changed, 31 insertions(+), 29 deletions(-)
 
20
 
 
21
--- a/drivers/net/wireless/ath/ath9k/ani.c
 
22
+++ b/drivers/net/wireless/ath/ath9k/ani.c
 
23
@@ -237,7 +237,7 @@ static void ath9k_hw_set_cck_nil(struct
 
24
                                     entry_cck->fir_step_level);
 
25
 
 
26
        /* Skip MRC CCK for pre AR9003 families */
 
27
-       if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah))
 
28
+       if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah))
 
29
                return;
 
30
 
 
31
        if (aniState->mrcCCK != entry_cck->mrc_cck_on)
 
32
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
 
33
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
 
34
@@ -3524,7 +3524,7 @@ static void ar9003_hw_xpa_bias_level_app
 
35
 
 
36
        if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
 
37
                REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
 
38
-       else if (AR_SREV_9462(ah) || AR_SREV_9550(ah))
 
39
+       else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah))
 
40
                REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
 
41
        else {
 
42
                REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
 
43
@@ -3572,7 +3572,7 @@ static void ar9003_hw_ant_ctrl_apply(str
 
44
 
 
45
        u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
 
46
 
 
47
-       if (AR_SREV_9462(ah)) {
 
48
+       if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 
49
                REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
 
50
                                AR_SWITCH_TABLE_COM_AR9462_ALL, value);
 
51
        } else if (AR_SREV_9550(ah)) {
 
52
@@ -3616,7 +3616,7 @@ static void ar9003_hw_ant_ctrl_apply(str
 
53
                }
 
54
        }
 
55
 
 
56
-       if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
 
57
+       if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
 
58
                value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
 
59
                /*
 
60
                 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
 
61
@@ -3847,7 +3847,7 @@ void ar9003_hw_internal_regulator_apply(
 
62
                        REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
 
63
                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
 
64
                                return;
 
65
-               } else if (AR_SREV_9462(ah)) {
 
66
+               } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 
67
                        reg_val = le32_to_cpu(pBase->swreg);
 
68
                        REG_WRITE(ah, AR_PHY_PMU1, reg_val);
 
69
                } else {
 
70
@@ -3878,7 +3878,7 @@ void ar9003_hw_internal_regulator_apply(
 
71
                        while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
 
72
                                                AR_PHY_PMU2_PGM))
 
73
                                udelay(10);
 
74
-               } else if (AR_SREV_9462(ah))
 
75
+               } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
 
76
                        REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
 
77
                else {
 
78
                        reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
 
79
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
 
80
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
 
81
@@ -31,7 +31,7 @@ ar9003_set_txdesc(struct ath_hw *ah, voi
 
82
        u32 val, ctl12, ctl17;
 
83
        u8 desc_len;
 
84
 
 
85
-       desc_len = (AR_SREV_9462(ah) ? 0x18 : 0x17);
 
86
+       desc_len = ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x18 : 0x17);
 
87
 
 
88
        val = (ATHEROS_VENDOR_ID << AR_DescId_S) |
 
89
              (1 << AR_TxRxDesc_S) |
 
90
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
 
91
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
 
92
@@ -88,7 +88,7 @@ static int ar9003_hw_set_channel(struct
 
93
                        channelSel = (freq * 4) / div;
 
94
                        chan_frac = (((freq * 4) % div) * 0x20000) / div;
 
95
                        channelSel = (channelSel << 17) | chan_frac;
 
96
-               } else if (AR_SREV_9485(ah)) {
 
97
+               } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
 
98
                        u32 chan_frac;
 
99
 
 
100
                        /*
 
101
@@ -736,7 +736,7 @@ static int ar9003_hw_process_ini(struct
 
102
        if (chan->channel == 2484)
 
103
                ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);
 
104
 
 
105
-       if (AR_SREV_9462(ah))
 
106
+       if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
 
107
                REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
 
108
                          AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
 
109
 
 
110
@@ -746,9 +746,9 @@ static int ar9003_hw_process_ini(struct
 
111
        ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 
112
        ath9k_hw_apply_txpower(ah, chan, false);
 
113
 
 
114
-       if (AR_SREV_9462(ah)) {
 
115
+       if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 
116
                if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
 
117
-                               AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
 
118
+                                  AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
 
119
                        ah->enabled_cals |= TX_IQ_CAL;
 
120
                else
 
121
                        ah->enabled_cals &= ~TX_IQ_CAL;
 
122
@@ -1111,7 +1111,7 @@ static void ar9003_hw_set_nf_limits(stru
 
123
        if (AR_SREV_9330(ah))
 
124
                ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
 
125
 
 
126
-       if (AR_SREV_9462(ah)) {
 
127
+       if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 
128
                ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
 
129
                ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
 
130
                ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
 
131
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
 
132
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
 
133
@@ -636,8 +636,8 @@
 
134
 #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S       1
 
135
 
 
136
 #define AR_PHY_65NM_CH0_SYNTH4      0x1608c
 
137
-#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT   (AR_SREV_9462(ah) ? 0x00000001 : 0x00000002)
 
138
-#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S (AR_SREV_9462(ah) ? 0 : 1)
 
139
+#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT   ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002)
 
140
+#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)
 
141
 #define AR_PHY_65NM_CH0_SYNTH7      0x16098
 
142
 #define AR_PHY_65NM_CH0_BIAS1       0x160c0
 
143
 #define AR_PHY_65NM_CH0_BIAS2       0x160c4
 
144
@@ -647,7 +647,7 @@
 
145
 #define AR_PHY_65NM_CH2_RXTX4       0x1690c
 
146
 
 
147
 #define AR_CH0_TOP     (AR_SREV_9300(ah) ? 0x16288 : \
 
148
-                               ((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
 
149
+                        (((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x1628c : 0x16280)))
 
150
 #define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)
 
151
 #define AR_CH0_TOP_XPABIASLVL_S (AR_SREV_9550(ah) ? 6 : 8)
 
152
 
 
153
@@ -675,7 +675,7 @@
 
154
 #define AR_SWITCH_TABLE_ALL_S (0)
 
155
 
 
156
 #define AR_PHY_65NM_CH0_THERM       (AR_SREV_9300(ah) ? 0x16290 :\
 
157
-                                       (AR_SREV_9462(ah) ? 0x16294 : 0x1628c))
 
158
+                                    ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16294 : 0x1628c))
 
159
 
 
160
 #define AR_PHY_65NM_CH0_THERM_LOCAL   0x80000000
 
161
 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
 
162
@@ -697,17 +697,17 @@
 
163
 #define AR_CH0_TOP2_XPABIASLVL_S       12
 
164
 
 
165
 #define AR_CH0_XTAL            (AR_SREV_9300(ah) ? 0x16294 : \
 
166
-                                       (AR_SREV_9462(ah) ? 0x16298 : 0x16290))
 
167
+                                ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16298 : 0x16290))
 
168
 #define AR_CH0_XTAL_CAPINDAC   0x7f000000
 
169
 #define AR_CH0_XTAL_CAPINDAC_S 24
 
170
 #define AR_CH0_XTAL_CAPOUTDAC  0x00fe0000
 
171
 #define AR_CH0_XTAL_CAPOUTDAC_S        17
 
172
 
 
173
-#define AR_PHY_PMU1            (AR_SREV_9462(ah) ? 0x16340 : 0x16c40)
 
174
+#define AR_PHY_PMU1            ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16340 : 0x16c40)
 
175
 #define AR_PHY_PMU1_PWD                0x1
 
176
 #define AR_PHY_PMU1_PWD_S      0
 
177
 
 
178
-#define AR_PHY_PMU2            (AR_SREV_9462(ah) ? 0x16344 : 0x16c44)
 
179
+#define AR_PHY_PMU2            ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16344 : 0x16c44)
 
180
 #define AR_PHY_PMU2_PGM                0x00200000
 
181
 #define AR_PHY_PMU2_PGM_S      21
 
182
 
 
183
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
 
184
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
 
185
@@ -108,7 +108,7 @@
 
186
 #define EEP_RFSILENT_ENABLED_S      0
 
187
 #define EEP_RFSILENT_POLARITY       0x0002
 
188
 #define EEP_RFSILENT_POLARITY_S     1
 
189
-#define EEP_RFSILENT_GPIO_SEL       (AR_SREV_9462(ah) ? 0x00fc : 0x001c)
 
190
+#define EEP_RFSILENT_GPIO_SEL       ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00fc : 0x001c)
 
191
 #define EEP_RFSILENT_GPIO_SEL_S     2
 
192
 
 
193
 #define AR5416_OPFLAGS_11A           0x01
 
194
--- a/drivers/net/wireless/ath/ath9k/hw.c
 
195
+++ b/drivers/net/wireless/ath/ath9k/hw.c
 
196
@@ -602,6 +602,11 @@ static int __ath9k_hw_init(struct ath_hw
 
197
        if (AR_SREV_9462(ah))
 
198
                ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
 
199
 
 
200
+       if (AR_SREV_9565(ah)) {
 
201
+               ah->WARegVal |= AR_WA_BIT22;
 
202
+               REG_WRITE(ah, AR_WA, ah->WARegVal);
 
203
+       }
 
204
+
 
205
        ath9k_hw_init_defaults(ah);
 
206
        ath9k_hw_init_config(ah);
 
207
 
 
208
@@ -802,8 +807,7 @@ static void ath9k_hw_init_pll(struct ath
 
209
 {
 
210
        u32 pll;
 
211
 
 
212
-       if (AR_SREV_9485(ah)) {
 
213
-
 
214
+       if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
 
215
                /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
 
216
                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
 
217
                              AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
 
218
@@ -2036,7 +2040,7 @@ static void ath9k_set_power_sleep(struct
 
219
 {
 
220
        REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
 
221
 
 
222
-       if (AR_SREV_9462(ah)) {
 
223
+       if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 
224
                REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
 
225
                REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
 
226
                REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
 
227
@@ -2491,7 +2495,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw
 
228
 
 
229
        if (AR_SREV_9300_20_OR_LATER(ah)) {
 
230
                pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
 
231
-               if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
 
232
+               if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
 
233
                        pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
 
234
 
 
235
                pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
 
236
@@ -2570,14 +2574,12 @@ int ath9k_hw_fill_cap_info(struct ath_hw
 
237
                        ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
 
238
        }
 
239
 
 
240
-       if (AR_SREV_9462(ah)) {
 
241
-
 
242
+       if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 
243
                if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
 
244
                        pCap->hw_caps |= ATH9K_HW_CAP_MCI;
 
245
 
 
246
                if (AR_SREV_9462_20(ah))
 
247
                        pCap->hw_caps |= ATH9K_HW_CAP_RTT;
 
248
-
 
249
        }
 
250
 
 
251
 
 
252
@@ -2743,7 +2745,7 @@ void ath9k_hw_setrxfilter(struct ath_hw
 
253
 
 
254
        ENABLE_REGWRITE_BUFFER(ah);
 
255
 
 
256
-       if (AR_SREV_9462(ah))
 
257
+       if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
 
258
                bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
 
259
 
 
260
        REG_WRITE(ah, AR_RX_FILTER, bits);
 
261
@@ -3040,7 +3042,7 @@ void ath9k_hw_gen_timer_start(struct ath
 
262
        REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
 
263
                    gen_tmr_configuration[timer->index].mode_mask);
 
264
 
 
265
-       if (AR_SREV_9462(ah)) {
 
266
+       if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 
267
                /*
 
268
                 * Starting from AR9462, each generic timer can select which tsf
 
269
                 * to use. But we still follow the old rule, 0 - 7 use tsf and