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#define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */
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#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
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#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */
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#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
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#define REALVIEW_EB11MP_TWD_BASE 0x10100600
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#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
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#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000
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#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
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#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
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#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */
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#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
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#define REALVIEW_EB11MP_TWD_BASE 0x1F000600
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#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
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#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000
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#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
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#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
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#define REALVIEW_EB11MP_PRIV_MEM_SIZE SZ_8K
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#define REALVIEW_EB11MP_PRIV_MEM_OFF(x) (REALVIEW_EB11MP_PRIV_MEM_BASE + (x))
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#define REALVIEW_EB11MP_SCU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0) /* SCU registers */
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#define REALVIEW_EB11MP_GIC_CPU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0100) /* Generic interrupt controller CPU interface */
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#define REALVIEW_EB11MP_TWD_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0600)
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#define REALVIEW_EB11MP_GIC_DIST_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x1000) /* Generic interrupt controller distributor */
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* Core tile identification (REALVIEW_SYS_PROCID)