120
120
struct drxd_state {
121
121
struct dvb_frontend frontend;
122
122
struct dvb_frontend_ops ops;
123
struct dvb_frontend_parameters param;
123
struct dtv_frontend_properties props;
125
125
const struct firmware *fw;
126
126
struct device *dev;
917
state->microcode = kmalloc(fw->size, GFP_KERNEL);
917
state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
918
918
if (state->microcode == NULL) {
919
919
release_firmware(fw);
920
920
printk(KERN_ERR "drxd: firmware load failure: no memory\n");
924
memcpy(state->microcode, fw->data, fw->size);
925
924
state->microcode_length = fw->size;
926
925
release_firmware(fw);
1625
switch (state->param.u.ofdm.bandwidth) {
1626
case BANDWIDTH_8_MHZ:
1624
switch (state->props.bandwidth_hz) {
1627
1626
bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1629
case BANDWIDTH_7_MHZ:
1630
1629
bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1632
case BANDWIDTH_6_MHZ:
1633
1632
bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1804
1803
status = WriteTable(state, state->m_StartDiversityEnd);
1805
1804
if (status < 0)
1807
if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
1806
if (state->props.bandwidth_hz == 8000000) {
1808
1807
status = WriteTable(state, state->m_DiversityDelay8MHZ);
1809
1808
if (status < 0)
1907
1906
static int DRX_Start(struct drxd_state *state, s32 off)
1909
struct dvb_ofdm_parameters *p = &state->param.u.ofdm;
1908
struct dtv_frontend_properties *p = &state->props;
1912
1911
u16 transmissionParams = 0;
1971
1970
if (status < 0)
1974
mirrorFreqSpect = (state->param.inversion == INVERSION_ON);
1973
mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1976
1975
switch (p->transmission_mode) {
1977
1976
default: /* Not set, detect it automatically */
2331
2330
by SC for fix for some 8K,1/8 guard but is restored by
2332
2331
InitEC and ResetEC
2334
switch (p->bandwidth) {
2335
case BANDWIDTH_AUTO:
2336
case BANDWIDTH_8_MHZ:
2333
switch (p->bandwidth_hz) {
2335
p->bandwidth_hz = 8000000;
2337
2338
/* (64/7)*(8/8)*1000000 */
2338
2339
bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2341
2342
status = Write16(state,
2342
2343
FE_AG_REG_IND_DEL__A, 50, 0x0000);
2344
case BANDWIDTH_7_MHZ:
2345
2346
/* (64/7)*(7/8)*1000000 */
2346
2347
bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2347
2348
bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
2348
2349
status = Write16(state,
2349
2350
FE_AG_REG_IND_DEL__A, 59, 0x0000);
2351
case BANDWIDTH_6_MHZ:
2352
2353
/* (64/7)*(6/8)*1000000 */
2353
2354
bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2354
2355
bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
2890
static int drxd_get_frontend(struct dvb_frontend *fe,
2891
struct dvb_frontend_parameters *param)
2896
2891
static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2898
2893
return drxd_config_i2c(fe, enable);
2901
static int drxd_set_frontend(struct dvb_frontend *fe,
2902
struct dvb_frontend_parameters *param)
2896
static int drxd_set_frontend(struct dvb_frontend *fe)
2898
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2904
2899
struct drxd_state *state = fe->demodulator_priv;
2907
state->param = *param;
2908
2903
DRX_Stop(state);
2910
2905
if (fe->ops.tuner_ops.set_params) {
2911
fe->ops.tuner_ops.set_params(fe, param);
2906
fe->ops.tuner_ops.set_params(fe);
2912
2907
if (fe->ops.i2c_gate_ctrl)
2913
2908
fe->ops.i2c_gate_ctrl(fe, 0);
2916
/* FIXME: move PLL drivers */
2917
if (state->config.pll_set &&
2918
state->config.pll_set(state->priv, param,
2919
state->config.pll_address,
2920
state->config.demoda_address, &off) < 0) {
2921
printk(KERN_ERR "Error in pll_set\n");
2927
2913
return DRX_Start(state, off);
2937
2923
static struct dvb_frontend_ops drxd_ops = {
2924
.delsys = { SYS_DVBT},
2940
2926
.name = "Micronas DRXD DVB-T",
2942
2927
.frequency_min = 47125000,
2943
2928
.frequency_max = 855250000,
2944
2929
.frequency_stepsize = 166667,
2958
2943
.i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2960
2945
.set_frontend = drxd_set_frontend,
2961
.get_frontend = drxd_get_frontend,
2962
2946
.get_tune_settings = drxd_get_tune_settings,
2964
2948
.read_status = drxd_read_status,