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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "LiveRangeEdit.h"
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#include "VirtRegMap.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveRangeEdit.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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void LiveRangeEdit::Delegate::anchor() { }
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LiveInterval &LiveRangeEdit::createFrom(unsigned OldReg,
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MachineRegisterInfo &MRI = VRM.getRegInfo();
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LiveInterval &LiveRangeEdit::createFrom(unsigned OldReg) {
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unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
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VRM.setIsSplitFromReg(VReg, VRM.getOriginal(OldReg));
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VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
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LiveInterval &LI = LIS.getOrCreateInterval(VReg);
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newRegs_.push_back(&LI);
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bool LiveRangeEdit::checkRematerializable(VNInfo *VNI,
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const MachineInstr *DefMI,
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const TargetInstrInfo &tii,
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AliasAnalysis *aa) {
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assert(DefMI && "Missing instruction");
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scannedRemattable_ = true;
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if (!tii.isTriviallyReMaterializable(DefMI, aa))
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if (!TII.isTriviallyReMaterializable(DefMI, aa))
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remattable_.insert(VNI);
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void LiveRangeEdit::scanRemattable(LiveIntervals &lis,
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const TargetInstrInfo &tii,
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void LiveRangeEdit::scanRemattable(AliasAnalysis *aa) {
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for (LiveInterval::vni_iterator I = parent_.vni_begin(),
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E = parent_.vni_end(); I != E; ++I) {
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if (VNI->isUnused())
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MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
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MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def);
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checkRematerializable(VNI, DefMI, tii, aa);
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checkRematerializable(VNI, DefMI, aa);
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scannedRemattable_ = true;
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bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis,
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const TargetInstrInfo &tii,
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bool LiveRangeEdit::anyRematerializable(AliasAnalysis *aa) {
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if (!scannedRemattable_)
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scanRemattable(lis, tii, aa);
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return !remattable_.empty();
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/// OrigIdx are also available with the same value at UseIdx.
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bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
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OrigIdx = OrigIdx.getRegSlot(true);
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UseIdx = UseIdx.getRegSlot(true);
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for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
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if (!MO.isReg() || !MO.getReg() || MO.isDef())
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// Reserved registers are OK.
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if (MO.isUndef() || !lis.hasInterval(MO.getReg()))
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if (MO.isUndef() || !LIS.hasInterval(MO.getReg()))
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LiveInterval &li = lis.getInterval(MO.getReg());
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LiveInterval &li = LIS.getInterval(MO.getReg());
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const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
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// No defining instruction provided.
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SlotIndex DefIdx;
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DefIdx = lis.getInstructionIndex(RM.OrigMI);
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DefIdx = LIS.getInstructionIndex(RM.OrigMI);
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DefIdx = RM.ParentVNI->def;
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RM.OrigMI = lis.getInstructionFromIndex(DefIdx);
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RM.OrigMI = LIS.getInstructionFromIndex(DefIdx);
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assert(RM.OrigMI && "No defining instruction for remattable value");
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// Verify that all used registers are available with the same values.
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if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis))
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if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
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MachineBasicBlock::iterator MI,
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unsigned DestReg,
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const TargetInstrInfo &tii,
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const TargetRegisterInfo &tri,
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assert(RM.OrigMI && "Invalid remat");
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tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
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TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
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rematted_.insert(RM.ParentVNI);
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return lis.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
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return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
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void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) {
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void LiveRangeEdit::eraseVirtReg(unsigned Reg) {
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if (delegate_ && delegate_->LRE_CanEraseVirtReg(Reg))
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LIS.removeInterval(Reg);
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bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
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SmallVectorImpl<MachineInstr*> &Dead,
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MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII) {
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SmallVectorImpl<MachineInstr*> &Dead) {
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MachineInstr *DefMI = 0, *UseMI = 0;
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// Check that there is a single def and a single use.
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void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
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LiveIntervals &LIS, VirtRegMap &VRM,
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const TargetInstrInfo &TII,
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ArrayRef<unsigned> RegsBeingSpilled) {
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SetVector<LiveInterval*,
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SmallVector<LiveInterval*, 8>,
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SmallPtrSet<LiveInterval*, 8> > ToShrink;
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MachineRegisterInfo &MRI = VRM.getRegInfo();
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// Erase all dead defs.
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// Shrink just one live interval. Then delete new dead defs.
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LiveInterval *LI = ToShrink.back();
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ToShrink.pop_back();
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if (foldAsLoad(LI, Dead, MRI, LIS, TII))
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if (foldAsLoad(LI, Dead))
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delegate_->LRE_WillShrinkVirtReg(LI->reg);
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if (NumComp <= 1)
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bool IsOriginal = VRM.getOriginal(LI->reg) == LI->reg;
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bool IsOriginal = VRM && VRM->getOriginal(LI->reg) == LI->reg;
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DEBUG(dbgs() << NumComp << " components: " << *LI << '\n');
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SmallVector<LiveInterval*, 8> Dups(1, LI);
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for (unsigned i = 1; i != NumComp; ++i) {
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Dups.push_back(&createFrom(LI->reg, LIS, VRM));
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Dups.push_back(&createFrom(LI->reg));
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// If LI is an original interval that hasn't been split yet, make the new
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// intervals their own originals instead of referring to LI. The original
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// interval must contain all the split products, and LI doesn't.
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VRM.setIsSplitFromReg(Dups.back()->reg, 0);
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VRM->setIsSplitFromReg(Dups.back()->reg, 0);
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delegate_->LRE_DidCloneVirtReg(Dups.back()->reg, LI->reg);
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void LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
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const MachineLoopInfo &Loops) {
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VirtRegAuxInfo VRAI(MF, LIS, Loops);
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MachineRegisterInfo &MRI = MF.getRegInfo();
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for (iterator I = begin(), E = end(); I != E; ++I) {
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LiveInterval &LI = **I;
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if (MRI.recomputeRegClass(LI.reg, MF.getTarget()))