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- Committer: Bazaar Package Importer
- Author(s): Mark Purcell
- Date: 2006-10-24 22:41:01 UTC
- mfrom: (1.1.7 upstream)
- Revision ID: james.westby@ubuntu.com-20061024224101-464p4n2jk16n1jrh
Tags: 1:1.2.10.dfsg-2
* bristuff-0.3.0-PRE-1v
* Remove redundant GPL LICENCE text
* Remove redundant GPL LICENCE text
- files added:
- debian/patches/dbug391840.dpatch
- oct612x
- oct612x/apilib
- oct612x/apilib/bt
- oct612x/apilib/largmath
- oct612x/apilib/llman
- oct612x/include
- oct612x/include/apilib
- oct612x/include/oct6100api
- oct612x/include/octrpc
- oct612x/octdeviceapi
- oct612x/octdeviceapi/oct6100api
- oct612x/octdeviceapi/oct6100api/oct6100_api
- oct612x/octdeviceapi/oct6100api/oct6100_apimi
- wct4xxp
- files removed:
- cwain/LICENSE
- include
- include/apilib
- include/oct6100api
- include/octrpc
- files modified:
- .version
added
removed
oct612x/octdeviceapi/oct6100api/oct6100_api/oct6100_chip_open.c
1
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
2
3
File: oct6100_chip_open.c
4
5
Copyright (c) 2001-2006 Octasic Inc.
6
7
Description:
8
9
This file contains the functions used to power-up the chip according to the
10
user's configuration. Also, the API instance is initialized to reflect the
11
desired configuration.
12
13
This file is part of the Octasic OCT6100 GPL API . The OCT6100 GPL API is
14
free software; you can redistribute it and/or modify it under the terms of
15
the GNU General Public License as published by the Free Software Foundation;
16
either version 2 of the License, or (at your option) any later version.
17
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The OCT6100 GPL API is distributed in the hope that it will be useful, but
19
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
20
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
21
for more details.
22
23
You should have received a copy of the GNU General Public License
24
along with the OCT6100 GPL API; if not, write to the Free Software
25
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
26
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$Octasic_Release: OCT612xAPI-01.00-PR43 $
28
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$Octasic_Revision: 312 $
30
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\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
32
33
34
/***************************** INCLUDE FILES *******************************/
35
36
#include "octdef.h"
37
38
#include "oct6100api/oct6100_defines.h"
39
#include "oct6100api/oct6100_errors.h"
40
41
#include "apilib/octapi_bt0.h"
42
#include "apilib/octapi_llman.h"
43
44
#include "oct6100api/oct6100_apiud.h"
45
#include "oct6100api/oct6100_chip_stats_inst.h"
46
#include "oct6100api/oct6100_tsi_cnct_inst.h"
47
#include "oct6100api/oct6100_events_inst.h"
48
#include "oct6100api/oct6100_conf_bridge_inst.h"
49
#include "oct6100api/oct6100_playout_buf_inst.h"
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51
#include "oct6100api/oct6100_mixer_inst.h"
52
#include "oct6100api/oct6100_channel_inst.h"
53
#include "oct6100api/oct6100_adpcm_chan_inst.h"
54
#include "oct6100api/oct6100_phasing_tsst_inst.h"
55
#include "oct6100api/oct6100_interrupts_inst.h"
56
#include "oct6100api/oct6100_remote_debug_inst.h"
57
#include "oct6100api/oct6100_debug_inst.h"
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#include "oct6100api/oct6100_tlv_inst.h"
59
#include "oct6100api/oct6100_chip_open_inst.h"
60
#include "oct6100api/oct6100_api_inst.h"
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#include "oct6100api/oct6100_chip_stats_pub.h"
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#include "oct6100api/oct6100_interrupts_pub.h"
64
#include "oct6100api/oct6100_tsi_cnct_pub.h"
65
#include "oct6100api/oct6100_events_pub.h"
66
#include "oct6100api/oct6100_conf_bridge_pub.h"
67
#include "oct6100api/oct6100_playout_buf_pub.h"
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#include "oct6100api/oct6100_channel_pub.h"
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#include "oct6100api/oct6100_adpcm_chan_pub.h"
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#include "oct6100api/oct6100_phasing_tsst_pub.h"
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#include "oct6100api/oct6100_remote_debug_pub.h"
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#include "oct6100api/oct6100_chip_open_pub.h"
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#include "oct6100api/oct6100_mixer_pub.h"
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#include "oct6100api/oct6100_channel_pub.h"
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#include "oct6100api/oct6100_debug_pub.h"
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#include "oct6100_chip_open_priv.h"
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#include "oct6100_interrupts_priv.h"
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#include "oct6100_chip_stats_priv.h"
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#include "octrpc/rpc_protocol.h"
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#include "oct6100_remote_debug_priv.h"
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#include "oct6100_miscellaneous_priv.h"
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#include "oct6100_memory_priv.h"
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#include "oct6100_tsst_priv.h"
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#include "oct6100_tsi_cnct_priv.h"
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#include "oct6100_mixer_priv.h"
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#include "oct6100_events_priv.h"
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#include "oct6100_conf_bridge_priv.h"
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#include "oct6100_playout_buf_priv.h"
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#include "oct6100_channel_priv.h"
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#include "oct6100_adpcm_chan_priv.h"
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#include "oct6100_phasing_tsst_priv.h"
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#include "oct6100_tlv_priv.h"
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#include "oct6100_debug_priv.h"
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#include "oct6100_version.h"
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/**************************** PUBLIC FUNCTIONS *****************************/
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/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
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Function: Oct6100GetInstanceSizeDef
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Description: Retrieves the size of the required API instance structure.
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-------------------------------------------------------------------------------
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| Argument | Description
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-------------------------------------------------------------------------------
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f_pApiInstance Pointer to API instance. This memory is used to keep the
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present state of the chip and all its resources.
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f_pGetSize Structure containing API instance size.
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\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
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#if !SKIP_Oct6100GetInstanceSizeDef
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UINT32 Oct6100GetInstanceSizeDef(
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tPOCT6100_GET_INSTANCE_SIZE f_pGetSize )
121
{
122
return cOCT6100_ERR_OK;
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}
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#endif
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#if !SKIP_Oct6100GetInstanceSize
127
UINT32 Oct6100GetInstanceSize(
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tPOCT6100_CHIP_OPEN f_pChipOpen,
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tPOCT6100_GET_INSTANCE_SIZE f_pGetSize )
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{
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tOCT6100_API_INSTANCE_SIZES InstanceSizes;
132
UINT32 ulResult;
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/* Check user configuration for errors and conflicts. */
135
ulResult = Oct6100ApiCheckChipConfiguration( f_pChipOpen );
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if ( ulResult != cOCT6100_ERR_OK )
137
return ulResult;
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/* Calculate the instance size required for user's configuration. */
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ulResult = Oct6100ApiCalculateInstanceSizes( f_pChipOpen, &InstanceSizes );
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if ( ulResult != cOCT6100_ERR_OK )
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return ulResult;
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/* Return required size to user. */
145
f_pGetSize->ulApiInstanceSize = InstanceSizes.ulApiInstTotal;
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return cOCT6100_ERR_OK;
148
}
149
#endif
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151
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/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
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Function: Oct6100ChipOpenDef
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Description: Inserts default chip configuration parameters into the
157
structure pointed to by f_pChipOpen.
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-------------------------------------------------------------------------------
160
| Argument | Description
161
-------------------------------------------------------------------------------
162
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f_pChipOpen Structure containing user chip configuration.
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\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
166
#if !SKIP_Oct6100ChipOpenDef
167
UINT32 Oct6100ChipOpenDef(
168
tPOCT6100_CHIP_OPEN f_pChipOpen )
169
{
170
UINT32 i;
171
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f_pChipOpen->ulUserChipId = 0;
173
f_pChipOpen->fMultiProcessSystem = FALSE;
174
f_pChipOpen->pProcessContext = NULL;
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f_pChipOpen->ulMaxRwAccesses = 8;
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f_pChipOpen->pbyImageFile = NULL;
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f_pChipOpen->ulImageSize = 0;
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f_pChipOpen->ulMemClkFreq = 133000000; /* 133 Mhz */
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f_pChipOpen->ulUpclkFreq = cOCT6100_UPCLK_FREQ_33_33_MHZ; /* 33.33 Mhz */
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f_pChipOpen->fEnableMemClkOut = TRUE;
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f_pChipOpen->ulMemoryType = cOCT6100_MEM_TYPE_DDR;
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f_pChipOpen->ulNumMemoryChips = 1;
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f_pChipOpen->ulMemoryChipSize = cOCT6100_MEMORY_CHIP_SIZE_64MB;
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/* Set the tail displacement to zero. */
190
f_pChipOpen->ulTailDisplacement = 0;
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/* Disable acoustic echo by default. */
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f_pChipOpen->fEnableAcousticEcho = FALSE;
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/* Resource allocation parameters. */
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f_pChipOpen->ulMaxChannels = 672;
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f_pChipOpen->ulMaxTsiCncts = 0;
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f_pChipOpen->ulMaxBiDirChannels = 0;
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f_pChipOpen->ulMaxConfBridges = 0;
200
f_pChipOpen->ulMaxFlexibleConfParticipants = 0;
201
f_pChipOpen->ulMaxPlayoutBuffers = 0;
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f_pChipOpen->ulMaxPhasingTssts = 0;
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f_pChipOpen->ulMaxAdpcmChannels = 0;
205
f_pChipOpen->ulMaxTdmStreams = 32;
206
f_pChipOpen->fUseSynchTimestamp = FALSE;
207
for ( i = 0; i < 4; i++ )
208
{
209
f_pChipOpen->aulTimestampTimeslots[ i ] = cOCT6100_INVALID_TIMESLOT;
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f_pChipOpen->aulTimestampStreams[ i ] = cOCT6100_INVALID_STREAM;
211
}
212
f_pChipOpen->fEnableFastH100Mode = FALSE;
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/* Configure the soft tone event buffer. */
215
f_pChipOpen->ulSoftToneEventsBufSize = 2048;
216
f_pChipOpen->fEnableExtToneDetection = FALSE;
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/* Configure the soft playout event buffer. */
219
f_pChipOpen->ulSoftBufferPlayoutEventsBufSize = cOCT6100_INVALID_VALUE;
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/* Interrupt configuration. */
222
f_pChipOpen->ulInterruptPolarity = cOCT6100_ACTIVE_LOW_POLARITY;
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f_pChipOpen->InterruptConfig.ulErrorMemoryConfig = cOCT6100_INTERRUPT_NO_TIMEOUT;
225
f_pChipOpen->InterruptConfig.ulFatalGeneralConfig = cOCT6100_INTERRUPT_NO_TIMEOUT;
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f_pChipOpen->InterruptConfig.ulFatalMemoryConfig = cOCT6100_INTERRUPT_NO_TIMEOUT;
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f_pChipOpen->InterruptConfig.ulFatalMemoryConfig = cOCT6100_INTERRUPT_NO_TIMEOUT;
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f_pChipOpen->InterruptConfig.ulErrorH100Config = cOCT6100_INTERRUPT_NO_TIMEOUT;
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f_pChipOpen->InterruptConfig.ulErrorOverflowToneEventsConfig = cOCT6100_INTERRUPT_NO_TIMEOUT;
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f_pChipOpen->InterruptConfig.ulErrorMemoryTimeout = 100;
232
f_pChipOpen->InterruptConfig.ulFatalMemoryTimeout = 100;
233
f_pChipOpen->InterruptConfig.ulErrorH100Timeout = 100;
234
f_pChipOpen->InterruptConfig.ulErrorOverflowToneEventsTimeout = 100;
235
f_pChipOpen->ulMaxRemoteDebugSessions = 1;
236
f_pChipOpen->ulTdmSampling = cOCT6100_TDM_SAMPLE_AT_3_QUARTERS;
237
for ( i = 0; i < cOCT6100_TDM_STREAM_MAX_GROUPS; i++ )
238
f_pChipOpen->aulTdmStreamFreqs[ i ] = cOCT6100_TDM_STREAM_FREQ_8MHZ;
239
240
241
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f_pChipOpen->fEnableChannelRecording = FALSE;
243
f_pChipOpen->fEnableProductionBist = FALSE;
244
f_pChipOpen->ulNumProductionBistLoops = 1;
245
246
return cOCT6100_ERR_OK;
247
}
248
#endif
249
250
251
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
252
253
Function: Oct6100ChipOpen
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Description: Configures the chip according to the user specified
256
configuration f_pChipOpen. This function will perform all I/O
257
accesses necessary and initialize the API instance to reflect
258
the configuration.
259
260
-------------------------------------------------------------------------------
261
| Argument | Description
262
-------------------------------------------------------------------------------
263
f_pApiInstance Pointer to API instance. This memory is used to keep the
264
present state of the chip and all its resources.
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266
f_pChipOpen Structure containing user chip configuration.
267
268
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
269
#if !SKIP_Oct6100ChipOpen
270
UINT32 Oct6100ChipOpen(
271
tPOCT6100_INSTANCE_API f_pApiInstance,
272
tPOCT6100_CHIP_OPEN f_pChipOpen )
273
{
274
tOCT6100_API_INSTANCE_SIZES InstanceSizes;
275
UINT32 ulStructSize;
276
UINT32 ulResult;
277
UINT32 ulTempVar;
278
279
/* Check user chip configuration parameters for errors. */
280
ulResult = Oct6100ApiCheckChipConfiguration( f_pChipOpen );
281
if ( ulResult != cOCT6100_ERR_OK )
282
return ulResult;
283
284
/* Check if the host system is multi-process or not and adjust instance accordingly. */
285
if ( f_pChipOpen->fMultiProcessSystem != TRUE )
286
{
287
/* Set pointer to tOCT6100_SHARED_INFO structure within instance. */
288
ulStructSize = sizeof( tOCT6100_INSTANCE_API );
289
mOCT6100_ROUND_MEMORY_SIZE( ulStructSize, ulTempVar )
290
291
f_pApiInstance->pSharedInfo = ( tPOCT6100_SHARED_INFO )(( PUINT8 )f_pApiInstance + ulStructSize);
292
293
/* Save the process context specified by the user. */
294
f_pApiInstance->pProcessContext = f_pChipOpen->pProcessContext;
295
296
297
/* Create serialization object handles. */
298
ulResult = Oct6100ApiCreateSerializeObjects( f_pApiInstance, f_pChipOpen->ulUserChipId );
299
if ( ulResult != cOCT6100_ERR_OK )
300
return ulResult;
301
}
302
303
/* Copy the configuration structure. */
304
ulResult = Oct6100ApiCopyChipConfiguration( f_pApiInstance, f_pChipOpen );
305
if ( ulResult != cOCT6100_ERR_OK )
306
return ulResult;
307
308
/* Perform various calculations based on user chip configuration. */
309
ulResult = Oct6100ApiInitializeMiscellaneousVariables( f_pApiInstance );
310
if ( ulResult != cOCT6100_ERR_OK )
311
return ulResult;
312
313
/* Calculate the amount of memory needed for the API instance structure. */
314
ulResult = Oct6100ApiCalculateInstanceSizes( f_pChipOpen, &InstanceSizes );
315
if ( ulResult != cOCT6100_ERR_OK )
316
return ulResult;
317
318
/* Allocate the memory for the API instance structure internal pointers. */
319
ulResult = Oct6100ApiAllocateInstanceMemory( f_pApiInstance, &InstanceSizes );
320
if ( ulResult != cOCT6100_ERR_OK )
321
return ulResult;
322
323
/* Initialize the allocated instance structure memory. */
324
ulResult = Oct6100ApiInitializeInstanceMemory( f_pApiInstance );
325
if ( ulResult != cOCT6100_ERR_OK )
326
return ulResult;
327
328
/* Initialize the tone information structure. */
329
ulResult = Oct6100ApiInitToneInfo( f_pApiInstance );
330
if ( ulResult != cOCT6100_ERR_OK )
331
return ulResult;
332
333
/* Test the CPU registers. */
334
ulResult = Oct6100ApiCpuRegisterBist( f_pApiInstance );
335
if ( ulResult != cOCT6100_ERR_OK )
336
return ulResult;
337
338
/* Boot the FC2 PLL. */
339
ulResult = Oct6100ApiBootFc2Pll( f_pApiInstance );
340
if ( ulResult != cOCT6100_ERR_OK )
341
return ulResult;
342
343
/* Program the FC1 PLL. */
344
ulResult = Oct6100ApiProgramFc1Pll( f_pApiInstance );
345
if ( ulResult != cOCT6100_ERR_OK )
346
return ulResult;
347
348
/* Decode the key and bist internal memories. */
349
ulResult = Oct6100ApiDecodeKeyAndBist( f_pApiInstance );
350
if ( ulResult != cOCT6100_ERR_OK )
351
return ulResult;
352
353
/* Boot the FC1 PLL. */
354
ulResult = Oct6100ApiBootFc1Pll( f_pApiInstance );
355
if ( ulResult != cOCT6100_ERR_OK )
356
return ulResult;
357
358
/* Boot the SDRAM. */
359
ulResult = Oct6100ApiBootSdram( f_pApiInstance );
360
if ( ulResult != cOCT6100_ERR_OK )
361
return ulResult;
362
363
/* Bist the external memory. */
364
ulResult = Oct6100ApiExternalMemoryBist( f_pApiInstance );
365
if ( ulResult != cOCT6100_ERR_OK )
366
return ulResult;
367
368
/* Initialize the external memory. */
369
ulResult = Oct6100ApiExternalMemoryInit( f_pApiInstance );
370
if ( ulResult != cOCT6100_ERR_OK )
371
return ulResult;
372
373
/* Load the image into the chip. */
374
ulResult = Oct6100ApiLoadImage( f_pApiInstance );
375
if ( ulResult != cOCT6100_ERR_OK )
376
return ulResult;
377
378
/* Write the clock distribution registers. */
379
ulResult = Oct6100ApiEnableClocks( f_pApiInstance );
380
if ( ulResult != cOCT6100_ERR_OK )
381
return ulResult;
382
383
/* Program the NLP processor. */
384
ulResult = Oct6100ApiProgramNLP( f_pApiInstance );
385
if ( ulResult != cOCT6100_ERR_OK )
386
{
387
if ( ulResult == cOCT6100_ERR_OPEN_EGO_TIMEOUT )
388
ulResult = Oct6100ApiProgramNLP( f_pApiInstance );
389
}
390
if ( ulResult != cOCT6100_ERR_OK )
391
return ulResult;
392
393
if ( f_pChipOpen->fEnableProductionBist == FALSE )
394
{
395
/* Read all TLV fields present in external memory. */
396
ulResult = Oct6100ApiProcessTlvRegion( f_pApiInstance );
397
if ( ulResult != cOCT6100_ERR_OK )
398
return ulResult;
399
400
/* Configure the H.100 interface. */
401
ulResult = Oct6100ApiSetH100Register( f_pApiInstance );
402
if ( ulResult != cOCT6100_ERR_OK )
403
return ulResult;
404
}
405
406
/* Write miscellaneous registers. */
407
ulResult = Oct6100ApiWriteMiscellaneousRegisters( f_pApiInstance );
408
if ( ulResult != cOCT6100_ERR_OK )
409
return ulResult;
410
411
/* Proceed with the rest only if the production BIST has not been requested. */
412
if ( f_pChipOpen->fEnableProductionBist == FALSE )
413
{
414
/* Configure the interrupt registers. */
415
ulResult = Oct6100ApiIsrHwInit( f_pApiInstance, &f_pChipOpen->InterruptConfig );
416
if ( ulResult != cOCT6100_ERR_OK )
417
return ulResult;
418
419
/* Initialize the errors counters. */
420
ulResult = Oct6100ApiChipStatsSwInit( f_pApiInstance );
421
if ( ulResult != cOCT6100_ERR_OK )
422
return ulResult;
423
424
/* Configure all interrupts of the chip. */
425
ulResult = Oct6100InterruptConfigureSer( f_pApiInstance, &f_pChipOpen->InterruptConfig, FALSE );
426
if ( ulResult != cOCT6100_ERR_OK )
427
return ulResult;
428
429
/* Get revision number of chip. */
430
ulResult = Oct6100ApiGetChipRevisionNum( f_pApiInstance );
431
if ( ulResult != cOCT6100_ERR_OK )
432
return ulResult;
433
434
435
436
437
438
/* Initialize the channels. */
439
ulResult = Oct6100ApiInitChannels( f_pApiInstance );
440
if ( ulResult != cOCT6100_ERR_OK )
441
return ulResult;
442
443
/* Initialize the mixer memory. */
444
ulResult = Oct6100ApiInitMixer( f_pApiInstance );
445
if ( ulResult != cOCT6100_ERR_OK )
446
return ulResult;
447
448
/* Initialize the mixer memory. */
449
ulResult = Oct6100ApiInitRecordResources( f_pApiInstance );
450
if ( ulResult != cOCT6100_ERR_OK )
451
return ulResult;
452
453
/* Initialize free external memory for buffer playout. */
454
ulResult = Oct6100ApiBufferPlayoutMemorySwInit( f_pApiInstance );
455
if ( ulResult != cOCT6100_ERR_OK )
456
return ulResult;
457
458
459
460
}
461
462
return cOCT6100_ERR_OK;
463
}
464
#endif
465
466
467
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
468
469
Function: Oct6100ChipCloseDef
470
471
Description: Puts the chip into soft reset.
472
473
-------------------------------------------------------------------------------
474
| Argument | Description
475
-------------------------------------------------------------------------------
476
f_pApiInstance Pointer to API instance. This memory is used to keep the
477
present state of the chip and all its resources.
478
479
f_pChipClose Pointer to a tOCT6100_CHIP_CLOSE structure.
480
481
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
482
#if !SKIP_Oct6100ChipCloseDef
483
UINT32 Oct6100ChipCloseDef(
484
tPOCT6100_CHIP_CLOSE f_pChipClose )
485
{
486
f_pChipClose->ulDummyVariable = 0;
487
488
return cOCT6100_ERR_OK;
489
}
490
#endif
491
492
#if !SKIP_Oct6100ChipClose
493
UINT32 Oct6100ChipClose(
494
tPOCT6100_INSTANCE_API f_pApiInstance,
495
tPOCT6100_CHIP_CLOSE f_pChipClose )
496
{
497
tOCT6100_WRITE_PARAMS WriteParams;
498
UINT32 ulResult;
499
500
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
501
502
WriteParams.ulUserChipId = f_pApiInstance->pSharedInfo->ChipConfig.ulUserChipId;
503
WriteParams.ulWriteAddress = 0x100;
504
WriteParams.usWriteData = 0x0000;
505
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
506
if ( ulResult != cOCT6100_ERR_OK )
507
return ulResult;
508
509
/* Destroy the allocated ressources used for serialization. */
510
ulResult = Oct6100ApiDestroySerializeObjects( f_pApiInstance );
511
if ( ulResult != cOCT6100_ERR_OK )
512
return ulResult;
513
514
return cOCT6100_ERR_OK;
515
}
516
#endif
517
518
519
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
520
521
Function: Oct6100CreateLocalInstance
522
523
Description: Creates a local instance for a process in a multi-process
524
host system.
525
526
-------------------------------------------------------------------------------
527
| Argument | Description
528
-------------------------------------------------------------------------------
529
f_pCreateLocal Structure used to create process' local instance.
530
531
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
532
#if !SKIP_Oct6100CreateLocalInstanceDef
533
UINT32 Oct6100CreateLocalInstanceDef(
534
tPOCT6100_CREATE_LOCAL_INSTANCE f_pCreateLocal )
535
{
536
f_pCreateLocal->pApiInstShared = NULL;
537
f_pCreateLocal->pApiInstLocal = NULL;
538
f_pCreateLocal->pProcessContext = NULL;
539
f_pCreateLocal->ulUserChipId = 0;
540
541
return cOCT6100_ERR_OK;
542
}
543
#endif
544
545
546
#if !SKIP_Oct6100CreateLocalInstance
547
UINT32 Oct6100CreateLocalInstance(
548
tPOCT6100_CREATE_LOCAL_INSTANCE f_pCreateLocal )
549
{
550
tPOCT6100_INSTANCE_API pApiInstLocal;
551
UINT32 ulApiInstSize;
552
UINT32 ulTempVar;
553
UINT32 ulResult;
554
555
/* Check user's structure for errors. */
556
if ( f_pCreateLocal->pApiInstShared == NULL )
557
return cOCT6100_ERR_MULTIPROC_API_INST_SHARED;
558
559
if ( f_pCreateLocal->pApiInstLocal == NULL )
560
return cOCT6100_ERR_MULTIPROC_API_INST_LOCAL;
561
562
/* Get local pointer to local instance. */
563
pApiInstLocal = f_pCreateLocal->pApiInstLocal;
564
565
/* Assign pointers to local structure. */
566
ulApiInstSize = sizeof( tOCT6100_INSTANCE_API );
567
mOCT6100_ROUND_MEMORY_SIZE( ulApiInstSize, ulTempVar )
568
569
pApiInstLocal->pSharedInfo = ( tPOCT6100_SHARED_INFO )(( PUINT8 )f_pCreateLocal->pApiInstShared + ulApiInstSize);
570
pApiInstLocal->pProcessContext = f_pCreateLocal->pProcessContext;
571
572
/* Create serialization object handles needed. */
573
ulResult = Oct6100ApiCreateSerializeObjects( pApiInstLocal, f_pCreateLocal->ulUserChipId );
574
if ( ulResult != cOCT6100_ERR_OK )
575
return ulResult;
576
577
return cOCT6100_ERR_OK;
578
}
579
#endif
580
581
582
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
583
584
Function: Oct6100DestroyLocalInstance
585
586
Description: Release local instance for a process in a multi-process
587
host system.
588
589
-------------------------------------------------------------------------------
590
| Argument | Description
591
-------------------------------------------------------------------------------
592
f_pApiInstance Pointer to API instance. This memory is used to keep
593
the present state of the chip and all its resources.
594
595
f_pDestroyLocal Structure used to destroy the process' local instance.
596
597
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
598
#if !SKIP_Oct6100DestroyLocalInstanceDef
599
UINT32 Oct6100DestroyLocalInstanceDef(
600
tPOCT6100_DESTROY_LOCAL_INSTANCE f_pDestroyLocal )
601
{
602
f_pDestroyLocal->ulDummy = 0;
603
604
return cOCT6100_ERR_OK;
605
}
606
#endif
607
608
#if !SKIP_Oct6100DestroyLocalInstance
609
UINT32 Oct6100DestroyLocalInstance(
610
tPOCT6100_INSTANCE_API f_pApiInstance,
611
tPOCT6100_DESTROY_LOCAL_INSTANCE f_pDestroyLocal )
612
{
613
UINT32 ulResult;
614
615
/* Destroy the allocated ressources used for serialization. */
616
ulResult = Oct6100ApiDestroySerializeObjects( f_pApiInstance );
617
if ( ulResult != cOCT6100_ERR_OK )
618
return ulResult;
619
620
return cOCT6100_ERR_OK;
621
}
622
#endif
623
624
625
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
626
627
Function: Oct6100GetHwRevision
628
629
Description: Gets the hardware revision number of the chip.
630
631
-------------------------------------------------------------------------------
632
| Argument | Description
633
-------------------------------------------------------------------------------
634
f_pGetHwRev Pointer to user structure in which to return revision
635
number.
636
637
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
638
#if !SKIP_Oct6100GetHwRevisionDef
639
UINT32 Oct6100GetHwRevisionDef(
640
tPOCT6100_GET_HW_REVISION f_pGetHwRev )
641
{
642
f_pGetHwRev->ulUserChipId = cOCT6100_INVALID_CHIP_ID;
643
f_pGetHwRev->pProcessContext = NULL;
644
f_pGetHwRev->ulRevisionNum = cOCT6100_INVALID_VALUE;
645
646
return cOCT6100_ERR_OK;
647
}
648
#endif
649
650
651
#if !SKIP_Oct6100GetHwRevision
652
UINT32 Oct6100GetHwRevision(
653
tPOCT6100_GET_HW_REVISION f_pGetHwRev )
654
{
655
tOCT6100_READ_PARAMS ReadParams;
656
UINT32 ulResult;
657
UINT16 usReadData;
658
659
/* Read the hardware revision register. */
660
ReadParams.pProcessContext = f_pGetHwRev->pProcessContext;
661
662
ReadParams.ulUserChipId = f_pGetHwRev->ulUserChipId;
663
ReadParams.pusReadData = &usReadData;
664
ReadParams.ulReadAddress = 0x17E;
665
mOCT6100_DRIVER_READ_API( ReadParams, ulResult )
666
if ( ulResult != cOCT6100_ERR_OK )
667
return ulResult;
668
669
f_pGetHwRev->ulRevisionNum = ( usReadData >> 8 ) & 0xFF;
670
671
return cOCT6100_ERR_OK;
672
}
673
#endif
674
675
676
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
677
678
Function: Oct6100FreeResources
679
680
Description: This function closes all opened channels and frees all
681
specified global resources used by the chip.
682
683
-------------------------------------------------------------------------------
684
| Argument | Description
685
-------------------------------------------------------------------------------
686
f_pApiInstance Pointer to API instance. This memory is used to keep
687
the present state of the chip and all its resources.
688
689
f_pFreeResources Pointer to user structure in which to choose what
690
to free.
691
692
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
693
#if !SKIP_Oct6100FreeResourcesDef
694
UINT32 Oct6100FreeResourcesDef(
695
tPOCT6100_FREE_RESOURCES f_pFreeResources )
696
{
697
f_pFreeResources->fFreeTsiConnections = FALSE;
698
f_pFreeResources->fFreeConferenceBridges = FALSE;
699
f_pFreeResources->fFreePlayoutBuffers = FALSE;
700
f_pFreeResources->fFreePhasingTssts = FALSE;
701
f_pFreeResources->fFreeAdpcmChannels = FALSE;
702
703
return cOCT6100_ERR_OK;
704
}
705
#endif
706
707
708
#if !SKIP_Oct6100FreeResources
709
UINT32 Oct6100FreeResources(
710
tPOCT6100_INSTANCE_API f_pApiInstance,
711
tPOCT6100_FREE_RESOURCES f_pFreeResources )
712
{
713
tOCT6100_SEIZE_SERIALIZE_OBJECT SeizeSerObj;
714
tOCT6100_RELEASE_SERIALIZE_OBJECT ReleaseSerObj;
715
UINT32 ulSerRes = cOCT6100_ERR_OK;
716
UINT32 ulFncRes = cOCT6100_ERR_OK;
717
718
/* Set the process context of the serialize structure. */
719
SeizeSerObj.pProcessContext = f_pApiInstance->pProcessContext;
720
ReleaseSerObj.pProcessContext = f_pApiInstance->pProcessContext;
721
722
/* Seize all list semaphores needed by this function. */
723
SeizeSerObj.ulSerialObjHndl = f_pApiInstance->ulApiSerObj;
724
SeizeSerObj.ulTryTimeMs = cOCT6100_WAIT_INFINITELY;
725
ulSerRes = Oct6100UserSeizeSerializeObject( &SeizeSerObj );
726
if ( ulSerRes == cOCT6100_ERR_OK )
727
{
728
/* Call the serialized function. */
729
ulFncRes = Oct6100FreeResourcesSer( f_pApiInstance, f_pFreeResources );
730
}
731
else
732
{
733
return ulSerRes;
734
}
735
736
/* Release the seized semaphores. */
737
ReleaseSerObj.ulSerialObjHndl = f_pApiInstance->ulApiSerObj;
738
ulSerRes = Oct6100UserReleaseSerializeObject( &ReleaseSerObj );
739
740
/* If an error occured then return the error code. */
741
if ( ulSerRes != cOCT6100_ERR_OK )
742
return ulSerRes;
743
if ( ulFncRes != cOCT6100_ERR_OK )
744
return ulFncRes;
745
746
return cOCT6100_ERR_OK;
747
}
748
#endif
749
750
751
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
752
753
Function: Oct6100ProductionBist
754
755
Description: This function retrieves the current BIST status of the
756
firmware.
757
758
-------------------------------------------------------------------------------
759
| Argument | Description
760
-------------------------------------------------------------------------------
761
f_pApiInstance Pointer to API instance. This memory is used to keep
762
the present state of the chip and all its resources.
763
764
f_pProductionBist Pointer to user structure where the bist information
765
will be returned.
766
767
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
768
#if !SKIP_Oct6100ProductionBistDef
769
UINT32 Oct6100ProductionBistDef(
770
tPOCT6100_PRODUCTION_BIST f_pProductionBist )
771
{
772
f_pProductionBist->ulCurrentAddress = cOCT6100_INVALID_VALUE;
773
f_pProductionBist->ulCurrentLoop = cOCT6100_INVALID_VALUE;
774
f_pProductionBist->ulFailedAddress = cOCT6100_INVALID_VALUE;
775
f_pProductionBist->ulReadValue = cOCT6100_INVALID_VALUE;
776
f_pProductionBist->ulExpectedValue = cOCT6100_INVALID_VALUE;
777
f_pProductionBist->ulBistStatus = cOCT6100_BIST_IN_PROGRESS;
778
f_pProductionBist->ulCurrentTest = cOCT6100_INVALID_VALUE;
779
780
return cOCT6100_ERR_OK;
781
}
782
#endif
783
784
785
#if !SKIP_Oct6100ProductionBist
786
UINT32 Oct6100ProductionBist(
787
tPOCT6100_INSTANCE_API f_pApiInstance,
788
tPOCT6100_PRODUCTION_BIST f_pProductionBist )
789
{
790
tOCT6100_SEIZE_SERIALIZE_OBJECT SeizeSerObj;
791
tOCT6100_RELEASE_SERIALIZE_OBJECT ReleaseSerObj;
792
UINT32 ulSerRes = cOCT6100_ERR_OK;
793
UINT32 ulFncRes = cOCT6100_ERR_OK;
794
795
/* Set the process context of the serialize structure. */
796
SeizeSerObj.pProcessContext = f_pApiInstance->pProcessContext;
797
ReleaseSerObj.pProcessContext = f_pApiInstance->pProcessContext;
798
799
/* Seize all list semaphores needed by this function. */
800
SeizeSerObj.ulSerialObjHndl = f_pApiInstance->ulApiSerObj;
801
SeizeSerObj.ulTryTimeMs = cOCT6100_WAIT_INFINITELY;
802
ulSerRes = Oct6100UserSeizeSerializeObject( &SeizeSerObj );
803
if ( ulSerRes == cOCT6100_ERR_OK )
804
{
805
/* Call the serialized function. */
806
ulFncRes = Oct6100ProductionBistSer( f_pApiInstance, f_pProductionBist );
807
}
808
else
809
{
810
return ulSerRes;
811
}
812
813
/* Release the seized semaphores. */
814
ReleaseSerObj.ulSerialObjHndl = f_pApiInstance->ulApiSerObj;
815
ulSerRes = Oct6100UserReleaseSerializeObject( &ReleaseSerObj );
816
817
/* If an error occured then return the error code. */
818
if ( ulSerRes != cOCT6100_ERR_OK )
819
return ulSerRes;
820
if ( ulFncRes != cOCT6100_ERR_OK )
821
return ulFncRes;
822
823
return cOCT6100_ERR_OK;
824
}
825
#endif
826
827
828
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
829
830
Function: Oct6100ApiGetVersion
831
832
Description: Retrieves the API version.
833
834
-------------------------------------------------------------------------------
835
| Argument | Description
836
-------------------------------------------------------------------------------
837
838
f_pApiGetVersion Pointer to structure that will receive version information.
839
840
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
841
#if !SKIP_Oct6100ApiGetVersionDef
842
UINT32 Oct6100ApiGetVersionDef(
843
tPOCT6100_API_GET_VERSION f_pApiGetVersion )
844
{
845
UINT32 i;
846
847
/* Initialize the string. */
848
for ( i = 0; i < cOCT6100_API_VERSION_STRING_LENGTH; i++ )
849
f_pApiGetVersion->achApiVersion[ i ] = 0;
850
851
return cOCT6100_ERR_OK;
852
}
853
#endif
854
855
#if !SKIP_Oct6100ApiGetVersion
856
UINT32 Oct6100ApiGetVersion(
857
tPOCT6100_API_GET_VERSION f_pApiGetVersion )
858
{
859
/* Copy API version information to user. */
860
Oct6100UserMemCopy( f_pApiGetVersion->achApiVersion, cOCT6100_API_VERSION, sizeof(cOCT6100_API_VERSION) );
861
862
return cOCT6100_ERR_OK;
863
}
864
#endif
865
866
867
/*************************** PRIVATE FUNCTIONS *****************************/
868
869
870
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
871
872
Function: Oct6100ApiCheckChipConfiguration
873
874
Description: Checks the user chip configuration structure for errors.
875
876
-------------------------------------------------------------------------------
877
| Argument | Description
878
-------------------------------------------------------------------------------
879
880
f_pChipOpen Pointer to chip configuration structure.
881
882
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
883
#if !SKIP_Oct6100ApiCheckChipConfiguration
884
UINT32 Oct6100ApiCheckChipConfiguration(
885
IN tPOCT6100_CHIP_OPEN f_pChipOpen )
886
{
887
UINT32 ulTempVar;
888
UINT32 i;
889
890
/*-----------------------------------------------------------------------------*/
891
/* Check general parameters. */
892
if ( f_pChipOpen->fMultiProcessSystem != TRUE &&
893
f_pChipOpen->fMultiProcessSystem != FALSE )
894
return cOCT6100_ERR_OPEN_MULTI_PROCESS_SYSTEM;
895
896
if ( f_pChipOpen->ulMaxRwAccesses < 1 ||
897
f_pChipOpen->ulMaxRwAccesses > 1024)
898
return cOCT6100_ERR_OPEN_MAX_RW_ACCESSES;
899
900
/* Check the clocks. */
901
if ( f_pChipOpen->ulUpclkFreq != cOCT6100_UPCLK_FREQ_33_33_MHZ )
902
return cOCT6100_ERR_OPEN_UP_CLK_FREQ;
903
904
if ( f_pChipOpen->ulMemClkFreq != cOCT6100_MCLK_FREQ_133_MHZ &&
905
f_pChipOpen->ulMemClkFreq != cOCT6100_MCLK_FREQ_125_MHZ &&
906
f_pChipOpen->ulMemClkFreq != cOCT6100_MCLK_FREQ_117_MHZ &&
907
f_pChipOpen->ulMemClkFreq != cOCT6100_MCLK_FREQ_108_MHZ &&
908
f_pChipOpen->ulMemClkFreq != cOCT6100_MCLK_FREQ_100_MHZ &&
909
f_pChipOpen->ulMemClkFreq != cOCT6100_MCLK_FREQ_92_MHZ &&
910
f_pChipOpen->ulMemClkFreq != cOCT6100_MCLK_FREQ_83_MHZ &&
911
f_pChipOpen->ulMemClkFreq != cOCT6100_MCLK_FREQ_75_MHZ )
912
return cOCT6100_ERR_OPEN_MEM_CLK_FREQ;
913
914
if ( f_pChipOpen->fEnableMemClkOut != TRUE &&
915
f_pChipOpen->fEnableMemClkOut != FALSE )
916
return cOCT6100_ERR_OPEN_ENABLE_MEM_CLK_OUT;
917
918
/* Check the image file. */
919
if ( f_pChipOpen->ulImageSize < cOCT6100_MIN_IMAGE_SIZE ||
920
f_pChipOpen->ulImageSize > cOCT6100_MAX_IMAGE_SIZE )
921
return cOCT6100_ERR_OPEN_IMAGE_SIZE;
922
923
if ( f_pChipOpen->pbyImageFile == NULL )
924
return cOCT6100_ERR_OPEN_IMAGE_FILE;
925
926
/* Check the acoustic echo activation flag. */
927
if ( f_pChipOpen->fEnableAcousticEcho != TRUE &&
928
f_pChipOpen->fEnableAcousticEcho != FALSE )
929
return cOCT6100_ERR_OPEN_ENABLE_ACOUSTIC_ECHO;
930
931
/* Check the tail displacement parameter. */
932
if ( f_pChipOpen->ulTailDisplacement > cOCT6100_MAX_TAIL_DISPLACEMENT )
933
return cOCT6100_ERR_OPEN_TAIL_DISPLACEMENT;
934
935
/*-----------------------------------------------------------------------------*/
936
/* Check TDM bus configuration parameters. */
937
for ( i = 0; i < 8; i++ )
938
{
939
if ( f_pChipOpen->aulTdmStreamFreqs[ i ] != cOCT6100_TDM_STREAM_FREQ_2MHZ &&
940
f_pChipOpen->aulTdmStreamFreqs[ i ] != cOCT6100_TDM_STREAM_FREQ_4MHZ &&
941
f_pChipOpen->aulTdmStreamFreqs[ i ] != cOCT6100_TDM_STREAM_FREQ_8MHZ)
942
return cOCT6100_ERR_OPEN_TDM_STREAM_FREQS;
943
}
944
945
if ( f_pChipOpen->ulTdmSampling != cOCT6100_TDM_SAMPLE_AT_3_QUARTERS &&
946
f_pChipOpen->ulTdmSampling != cOCT6100_TDM_SAMPLE_AT_RISING_EDGE &&
947
f_pChipOpen->ulTdmSampling != cOCT6100_TDM_SAMPLE_AT_FALLING_EDGE )
948
return cOCT6100_ERR_OPEN_TDM_SAMPLING;
949
950
if ( f_pChipOpen->fEnableFastH100Mode != TRUE &&
951
f_pChipOpen->fEnableFastH100Mode != FALSE )
952
return cOCT6100_ERR_OPEN_FAST_H100_MODE;
953
954
/*-----------------------------------------------------------------------------*/
955
/* Check external memory configuration parameters. */
956
if ( f_pChipOpen->ulMemoryType != cOCT6100_MEM_TYPE_SDR &&
957
f_pChipOpen->ulMemoryType != cOCT6100_MEM_TYPE_DDR &&
958
f_pChipOpen->ulMemoryType != cOCT6100_MEM_TYPE_SDR_PLL_BYPASS )
959
return cOCT6100_ERR_OPEN_MEMORY_TYPE;
960
961
if ( f_pChipOpen->ulMemoryChipSize != cOCT6100_MEMORY_CHIP_SIZE_8MB &&
962
f_pChipOpen->ulMemoryChipSize != cOCT6100_MEMORY_CHIP_SIZE_16MB &&
963
f_pChipOpen->ulMemoryChipSize != cOCT6100_MEMORY_CHIP_SIZE_32MB &&
964
f_pChipOpen->ulMemoryChipSize != cOCT6100_MEMORY_CHIP_SIZE_64MB &&
965
f_pChipOpen->ulMemoryChipSize != cOCT6100_MEMORY_CHIP_SIZE_128MB )
966
return cOCT6100_ERR_OPEN_MEMORY_CHIP_SIZE;
967
968
if ( f_pChipOpen->ulMemoryChipSize == cOCT6100_MEMORY_CHIP_SIZE_8MB &&
969
f_pChipOpen->ulMemoryType == cOCT6100_MEM_TYPE_DDR )
970
return cOCT6100_ERR_OPEN_MEMORY_CHIP_SIZE;
971
972
if ( f_pChipOpen->ulNumMemoryChips < 1 ||
973
f_pChipOpen->ulNumMemoryChips > cOCT6100_MAX_NUM_MEMORY_CHIP )
974
return cOCT6100_ERR_OPEN_MEMORY_CHIPS_NUMBER;
975
976
/* Check the total memory size. */
977
ulTempVar = f_pChipOpen->ulMemoryChipSize * f_pChipOpen->ulNumMemoryChips;
978
if ( ulTempVar < cOCT6100_MEMORY_CHIP_SIZE_16MB ||
979
ulTempVar > cOCT6100_MEMORY_CHIP_SIZE_128MB )
980
return cOCT6100_ERR_OPEN_TOTAL_MEMORY_SIZE;
981
982
if ( f_pChipOpen->ulMaxTdmStreams != 4 &&
983
f_pChipOpen->ulMaxTdmStreams != 8 &&
984
f_pChipOpen->ulMaxTdmStreams != 16 &&
985
f_pChipOpen->ulMaxTdmStreams != 32 )
986
return cOCT6100_ERR_OPEN_MAX_TDM_STREAM;
987
988
if ( f_pChipOpen->ulMaxTdmStreams > 8 &&
989
f_pChipOpen->ulMemClkFreq == cOCT6100_MCLK_FREQ_75_MHZ )
990
return cOCT6100_ERR_OPEN_MAX_TDM_STREAM;
991
992
if ( f_pChipOpen->fUseSynchTimestamp != TRUE &&
993
f_pChipOpen->fUseSynchTimestamp != FALSE )
994
return cOCT6100_ERR_OPEN_USE_SYNCH_TIMESTAMP;
995
996
if ( f_pChipOpen->fUseSynchTimestamp == TRUE )
997
{
998
return cOCT6100_ERR_NOT_SUPPORTED_OPEN_USE_SYNCH_TIMESTAMP;
999
}
1000
1001
/*-----------------------------------------------------------------------------*/
1002
/* Check soft buffer for tone events size. */
1003
if ( f_pChipOpen->ulSoftToneEventsBufSize < cOCT6100_NUM_PGSP_EVENT_OUT ||
1004
f_pChipOpen->ulSoftToneEventsBufSize > cOCT6100_ABSOLUTE_MAX_NUM_PGSP_EVENT_OUT )
1005
return cOCT6100_ERR_OPEN_SOFT_TONE_EVENT_SIZE;
1006
1007
if ( f_pChipOpen->fEnableExtToneDetection != TRUE &&
1008
f_pChipOpen->fEnableExtToneDetection != FALSE )
1009
return cOCT6100_ERR_OPEN_ENABLE_EXT_TONE_DETECTION;
1010
1011
/* Check soft buffer for playout events size. */
1012
if ( ( f_pChipOpen->ulSoftBufferPlayoutEventsBufSize != cOCT6100_INVALID_VALUE )
1013
&& ( f_pChipOpen->ulSoftBufferPlayoutEventsBufSize < cOCT6100_MIN_BUFFER_PLAYOUT_EVENT ||
1014
f_pChipOpen->ulSoftBufferPlayoutEventsBufSize > cOCT6100_MAX_BUFFER_PLAYOUT_EVENT ) )
1015
return cOCT6100_ERR_OPEN_SOFT_PLAYOUT_STOP_EVENT_SIZE;
1016
1017
/*-----------------------------------------------------------------------------*/
1018
/* Check interrupt configuration parameters. */
1019
if ( f_pChipOpen->ulInterruptPolarity != cOCT6100_ACTIVE_LOW_POLARITY &&
1020
f_pChipOpen->ulInterruptPolarity != cOCT6100_ACTIVE_HIGH_POLARITY )
1021
return cOCT6100_ERR_OPEN_INTERRUPT_POLARITY;
1022
1023
if ( f_pChipOpen->InterruptConfig.ulFatalGeneralConfig != cOCT6100_INTERRUPT_NO_TIMEOUT &&
1024
f_pChipOpen->InterruptConfig.ulFatalGeneralConfig != cOCT6100_INTERRUPT_DISABLE )
1025
return cOCT6100_ERR_OPEN_FATAL_GENERAL_CONFIG;
1026
1027
if ( f_pChipOpen->InterruptConfig.ulFatalMemoryConfig != cOCT6100_INTERRUPT_NO_TIMEOUT &&
1028
f_pChipOpen->InterruptConfig.ulFatalMemoryConfig != cOCT6100_INTERRUPT_TIMEOUT &&
1029
f_pChipOpen->InterruptConfig.ulFatalMemoryConfig != cOCT6100_INTERRUPT_DISABLE )
1030
return cOCT6100_ERR_OPEN_FATAL_MEMORY_CONFIG;
1031
1032
if ( f_pChipOpen->InterruptConfig.ulErrorMemoryConfig != cOCT6100_INTERRUPT_NO_TIMEOUT &&
1033
f_pChipOpen->InterruptConfig.ulErrorMemoryConfig != cOCT6100_INTERRUPT_TIMEOUT &&
1034
f_pChipOpen->InterruptConfig.ulErrorMemoryConfig != cOCT6100_INTERRUPT_DISABLE )
1035
return cOCT6100_ERR_OPEN_ERROR_MEMORY_CONFIG;
1036
1037
if ( f_pChipOpen->InterruptConfig.ulErrorOverflowToneEventsConfig != cOCT6100_INTERRUPT_NO_TIMEOUT &&
1038
f_pChipOpen->InterruptConfig.ulErrorOverflowToneEventsConfig != cOCT6100_INTERRUPT_TIMEOUT &&
1039
f_pChipOpen->InterruptConfig.ulErrorOverflowToneEventsConfig != cOCT6100_INTERRUPT_DISABLE )
1040
return cOCT6100_ERR_OPEN_ERROR_OVERFLOW_TONE_EVENTS_CONFIG;
1041
1042
if ( f_pChipOpen->InterruptConfig.ulErrorH100Config != cOCT6100_INTERRUPT_NO_TIMEOUT &&
1043
f_pChipOpen->InterruptConfig.ulErrorH100Config != cOCT6100_INTERRUPT_TIMEOUT &&
1044
f_pChipOpen->InterruptConfig.ulErrorH100Config != cOCT6100_INTERRUPT_DISABLE )
1045
return cOCT6100_ERR_OPEN_ERROR_H100_CONFIG;
1046
1047
/* Check the timeout value. */
1048
if ( f_pChipOpen->InterruptConfig.ulFatalMemoryTimeout < 10 ||
1049
f_pChipOpen->InterruptConfig.ulFatalMemoryTimeout > 10000 )
1050
return cOCT6100_ERR_OPEN_FATAL_MEMORY_TIMEOUT;
1051
1052
if ( f_pChipOpen->InterruptConfig.ulErrorMemoryTimeout < 10 ||
1053
f_pChipOpen->InterruptConfig.ulErrorMemoryTimeout > 10000 )
1054
return cOCT6100_ERR_OPEN_ERROR_MEMORY_TIMEOUT;
1055
1056
if ( f_pChipOpen->InterruptConfig.ulErrorOverflowToneEventsTimeout < 10 ||
1057
f_pChipOpen->InterruptConfig.ulErrorOverflowToneEventsTimeout > 10000 )
1058
return cOCT6100_ERR_OPEN_ERROR_OVERFLOW_TONE_EVENTS_TIMEOUT;
1059
1060
if ( f_pChipOpen->InterruptConfig.ulErrorH100Timeout < 10 ||
1061
f_pChipOpen->InterruptConfig.ulErrorH100Timeout > 10000 )
1062
return cOCT6100_ERR_OPEN_ERROR_H100_TIMEOUT;
1063
1064
/*-----------------------------------------------------------------------------*/
1065
/* Check maximum resources. */
1066
1067
switch ( f_pChipOpen->ulMemClkFreq )
1068
{
1069
case 133000000:
1070
ulTempVar = 672;
1071
break;
1072
case 125000000:
1073
ulTempVar = 624;
1074
break;
1075
case 117000000:
1076
ulTempVar = 576;
1077
break;
1078
case 108000000:
1079
ulTempVar = 528;
1080
break;
1081
case 100000000:
1082
ulTempVar = 480;
1083
break;
1084
case 92000000:
1085
ulTempVar = 432;
1086
break;
1087
case 83000000:
1088
ulTempVar = 384;
1089
break;
1090
case 75000000:
1091
ulTempVar = 336;
1092
break;
1093
default:
1094
return cOCT6100_ERR_FATAL_DA;
1095
}
1096
1097
if ( f_pChipOpen->ulMaxChannels > ulTempVar )
1098
return cOCT6100_ERR_OPEN_MAX_ECHO_CHANNELS;
1099
1100
if ( f_pChipOpen->ulMaxTsiCncts > cOCT6100_MAX_TSI_CNCTS )
1101
return cOCT6100_ERR_OPEN_MAX_TSI_CNCTS;
1102
1103
1104
if ( f_pChipOpen->ulMaxBiDirChannels > 255 )
1105
return cOCT6100_ERR_OPEN_MAX_BIDIR_CHANNELS;
1106
1107
if ( f_pChipOpen->ulMaxBiDirChannels > (f_pChipOpen->ulMaxChannels / 2) )
1108
return cOCT6100_ERR_OPEN_MAX_BIDIR_CHANNELS;
1109
1110
if ( f_pChipOpen->ulMaxConfBridges > cOCT6100_MAX_CONF_BRIDGE )
1111
return cOCT6100_ERR_OPEN_MAX_CONF_BRIDGES;
1112
1113
if ( f_pChipOpen->ulMaxFlexibleConfParticipants > cOCT6100_MAX_FLEX_CONF_PARTICIPANTS )
1114
return cOCT6100_ERR_OPEN_MAX_FLEXIBLE_CONF_PARTICIPANTS;
1115
1116
if ( f_pChipOpen->ulMaxPlayoutBuffers > cOCT6100_MAX_PLAYOUT_BUFFERS )
1117
return cOCT6100_ERR_OPEN_MAX_PLAYOUT_BUFFERS;
1118
1119
1120
1121
if ( f_pChipOpen->ulMaxPhasingTssts > cOCT6100_MAX_PHASING_TSST )
1122
return cOCT6100_ERR_OPEN_MAX_PHASING_TSSTS;
1123
1124
if ( f_pChipOpen->ulMaxAdpcmChannels > cOCT6100_MAX_ADPCM_CHANNELS )
1125
return cOCT6100_ERR_OPEN_MAX_ADPCM_CHANNELS;
1126
1127
if ( f_pChipOpen->ulMaxRemoteDebugSessions > 256 )
1128
return cOCT6100_ERR_OPEN_MAX_REMOTE_DEBUG_SESSIONS;
1129
1130
1131
1132
1133
1134
/* Check the channel recording flag. */
1135
if ( f_pChipOpen->fEnableChannelRecording != TRUE &&
1136
f_pChipOpen->fEnableChannelRecording != FALSE )
1137
return cOCT6100_ERR_OPEN_DEBUG_CHANNEL_RECORDING;
1138
1139
/* Check the enable production BIST flag. */
1140
if ( ( f_pChipOpen->fEnableProductionBist != TRUE )
1141
&& ( f_pChipOpen->fEnableProductionBist != FALSE ) )
1142
return cOCT6100_ERR_OPEN_ENABLE_PRODUCTION_BIST;
1143
1144
/* Check number of loops for the production BIST. */
1145
if ( f_pChipOpen->fEnableProductionBist == TRUE )
1146
{
1147
if ( f_pChipOpen->ulNumProductionBistLoops == 0 )
1148
return cOCT6100_ERR_OPEN_NUM_PRODUCTION_BIST_LOOPS;
1149
}
1150
1151
/* If the production BIST has been requested, make sure all */
1152
/* other resources are disabled. */
1153
if ( f_pChipOpen->fEnableProductionBist == TRUE )
1154
{
1155
/* All must be disabled. */
1156
f_pChipOpen->ulMaxChannels = 0;
1157
f_pChipOpen->ulMaxTsiCncts = 0;
1158
f_pChipOpen->fEnableChannelRecording = FALSE;
1159
f_pChipOpen->ulMaxBiDirChannels = 0;
1160
f_pChipOpen->ulMaxConfBridges = 0;
1161
f_pChipOpen->ulMaxPlayoutBuffers = 0;
1162
f_pChipOpen->ulSoftBufferPlayoutEventsBufSize = cOCT6100_INVALID_VALUE;
1163
f_pChipOpen->ulMaxPhasingTssts = 0;
1164
f_pChipOpen->ulMaxAdpcmChannels = 0;
1165
1166
1167
}
1168
1169
return cOCT6100_ERR_OK;
1170
}
1171
#endif
1172
1173
1174
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
1175
1176
Function: Oct6100ApiCopyChipConfiguration
1177
1178
Description: Copies the chip configuration from the user supplied config
1179
structure to the instance structure.
1180
1181
-------------------------------------------------------------------------------
1182
| Argument | Description
1183
-------------------------------------------------------------------------------
1184
f_pApiInstance Pointer to API instance. This memory is used to keep the
1185
present state of the chip and all its resources.
1186
1187
f_pChipOpen Pointer to chip configuration structure.
1188
1189
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
1190
#if !SKIP_Oct6100ApiCopyChipConfiguration
1191
UINT32 Oct6100ApiCopyChipConfiguration(
1192
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance,
1193
IN tPOCT6100_CHIP_OPEN f_pChipOpen )
1194
{
1195
tPOCT6100_SHARED_INFO pSharedInfo;
1196
UINT32 i;
1197
1198
/* Get local pointer to shared portion of instance. */
1199
pSharedInfo = f_pApiInstance->pSharedInfo;
1200
1201
pSharedInfo->ChipConfig.ulUserChipId = f_pChipOpen->ulUserChipId;
1202
pSharedInfo->ChipConfig.fMultiProcessSystem = (UINT8)( f_pChipOpen->fMultiProcessSystem & 0xFF );
1203
1204
pSharedInfo->ChipConfig.usMaxRwAccesses = (UINT16)( f_pChipOpen->ulMaxRwAccesses & 0xFFFF );
1205
1206
pSharedInfo->ChipConfig.pbyImageFile = f_pChipOpen->pbyImageFile;
1207
pSharedInfo->ChipConfig.ulImageSize = f_pChipOpen->ulImageSize;
1208
1209
pSharedInfo->ChipConfig.ulMemClkFreq = f_pChipOpen->ulMemClkFreq;
1210
pSharedInfo->ChipConfig.ulUpclkFreq = f_pChipOpen->ulUpclkFreq;
1211
1212
pSharedInfo->ChipConfig.byMemoryType = (UINT8)( f_pChipOpen->ulMemoryType & 0xFF );
1213
pSharedInfo->ChipConfig.byNumMemoryChips = (UINT8)( f_pChipOpen->ulNumMemoryChips & 0xFF );
1214
pSharedInfo->ChipConfig.ulMemoryChipSize = f_pChipOpen->ulMemoryChipSize;
1215
1216
pSharedInfo->ChipConfig.usTailDisplacement = (UINT16)( f_pChipOpen->ulTailDisplacement & 0xFFFF );
1217
pSharedInfo->ChipConfig.fEnableAcousticEcho = (UINT8)( f_pChipOpen->fEnableAcousticEcho & 0xFF );
1218
/* Resource allocation parameters. */
1219
if ( f_pChipOpen->fEnableChannelRecording == TRUE && f_pChipOpen->ulMaxChannels == 672 )
1220
pSharedInfo->ChipConfig.usMaxChannels = (UINT16)( ( f_pChipOpen->ulMaxChannels - 1 ) & 0xFFFF );
1221
else
1222
pSharedInfo->ChipConfig.usMaxChannels = (UINT16)( f_pChipOpen->ulMaxChannels & 0xFFFF );
1223
pSharedInfo->ChipConfig.usMaxTsiCncts = (UINT16)( f_pChipOpen->ulMaxTsiCncts & 0xFFFF );
1224
pSharedInfo->ChipConfig.usMaxBiDirChannels = (UINT16)( f_pChipOpen->ulMaxBiDirChannels & 0xFFFF );
1225
pSharedInfo->ChipConfig.usMaxConfBridges = (UINT16)( f_pChipOpen->ulMaxConfBridges & 0xFFFF );
1226
pSharedInfo->ChipConfig.usMaxFlexibleConfParticipants = (UINT16)( f_pChipOpen->ulMaxFlexibleConfParticipants & 0xFFFF );
1227
pSharedInfo->ChipConfig.usMaxPlayoutBuffers = (UINT16)( f_pChipOpen->ulMaxPlayoutBuffers & 0xFFFF );
1228
1229
pSharedInfo->ChipConfig.usMaxPhasingTssts = (UINT16)( f_pChipOpen->ulMaxPhasingTssts & 0xFFFF );
1230
pSharedInfo->ChipConfig.usMaxAdpcmChannels = (UINT16)( f_pChipOpen->ulMaxAdpcmChannels & 0xFFFF );
1231
pSharedInfo->ChipConfig.byMaxTdmStreams = (UINT8)( f_pChipOpen->ulMaxTdmStreams & 0xFF );
1232
pSharedInfo->ChipConfig.fUseSynchTimestamp = (UINT8)( f_pChipOpen->fUseSynchTimestamp & 0xFF );
1233
for ( i = 0; i < 4; i++ )
1234
{
1235
pSharedInfo->ChipConfig.ausTimestampTimeslots[ i ] = (UINT16)( f_pChipOpen->aulTimestampTimeslots[ i ] & 0xFFFF );
1236
pSharedInfo->ChipConfig.ausTimestampStreams[ i ] = (UINT16)( f_pChipOpen->aulTimestampStreams[ i ] & 0xFFFF );
1237
}
1238
pSharedInfo->ChipConfig.byInterruptPolarity = (UINT8)( f_pChipOpen->ulInterruptPolarity & 0xFF );
1239
1240
pSharedInfo->ChipConfig.byTdmSampling = (UINT8)( f_pChipOpen->ulTdmSampling & 0xFF );
1241
pSharedInfo->ChipConfig.fEnableFastH100Mode = (UINT8)( f_pChipOpen->fEnableFastH100Mode & 0xFF );
1242
1243
for ( i = 0; i < cOCT6100_TDM_STREAM_MAX_GROUPS; i++ )
1244
{
1245
if ( pSharedInfo->ChipConfig.fEnableFastH100Mode == TRUE )
1246
pSharedInfo->ChipConfig.aulTdmStreamFreqs[ i ] = cOCT6100_TDM_STREAM_FREQ_16MHZ;
1247
else
1248
pSharedInfo->ChipConfig.aulTdmStreamFreqs[ i ] = f_pChipOpen->aulTdmStreamFreqs[ i ];
1249
}
1250
1251
pSharedInfo->ChipConfig.fEnableFastH100Mode = (UINT8)( f_pChipOpen->fEnableFastH100Mode & 0xFF );
1252
pSharedInfo->ChipConfig.fEnableMemClkOut = (UINT8)( f_pChipOpen->fEnableMemClkOut & 0xFF );
1253
1254
/* Add 1 to the circular buffer such that all user requested events can fit in the circular queue. */
1255
pSharedInfo->ChipConfig.ulSoftToneEventsBufSize = f_pChipOpen->ulSoftToneEventsBufSize + 1;
1256
pSharedInfo->ChipConfig.fEnableExtToneDetection = (UINT8)( f_pChipOpen->fEnableExtToneDetection & 0xFF );
1257
1258
if ( f_pChipOpen->ulSoftBufferPlayoutEventsBufSize != cOCT6100_INVALID_VALUE )
1259
pSharedInfo->ChipConfig.ulSoftBufPlayoutEventsBufSize = f_pChipOpen->ulSoftBufferPlayoutEventsBufSize + 1;
1260
else
1261
pSharedInfo->ChipConfig.ulSoftBufPlayoutEventsBufSize = 0;
1262
pSharedInfo->ChipConfig.usMaxRemoteDebugSessions = (UINT16)( f_pChipOpen->ulMaxRemoteDebugSessions & 0xFFFF );
1263
1264
pSharedInfo->ChipConfig.fEnableChannelRecording = (UINT8)( f_pChipOpen->fEnableChannelRecording & 0xFF );
1265
1266
1267
1268
pSharedInfo->ChipConfig.fEnableProductionBist = (UINT8)( f_pChipOpen->fEnableProductionBist & 0xFF );
1269
pSharedInfo->ChipConfig.ulNumProductionBistLoops = f_pChipOpen->ulNumProductionBistLoops;
1270
1271
return cOCT6100_ERR_OK;
1272
}
1273
#endif
1274
1275
1276
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
1277
1278
Function: Oct6100ApiInitializeMiscellaneousVariables
1279
1280
Description: Function where all the various parameters from the API instance
1281
are set to their defaults value.
1282
1283
-------------------------------------------------------------------------------
1284
| Argument | Description
1285
-------------------------------------------------------------------------------
1286
f_pApiInstance Pointer to API instance. This memory is used to keep the
1287
present state of the chip and all its resources.
1288
1289
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
1290
#if !SKIP_Oct6100ApiInitializeMiscellaneousVariables
1291
UINT32 Oct6100ApiInitializeMiscellaneousVariables(
1292
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
1293
{
1294
tPOCT6100_SHARED_INFO pSharedInfo;
1295
UINT32 i;
1296
1297
/* Obtain pointer to shared portion of instance. */
1298
pSharedInfo = f_pApiInstance->pSharedInfo;
1299
1300
/* Calculate the total memory available. */
1301
pSharedInfo->MiscVars.ulTotalMemSize = pSharedInfo->ChipConfig.ulMemoryChipSize * pSharedInfo->ChipConfig.byNumMemoryChips;
1302
1303
/* Software buffers initialization. */
1304
1305
/* Tones */
1306
pSharedInfo->SoftBufs.ulToneEventBufferWritePtr = 0;
1307
pSharedInfo->SoftBufs.ulToneEventBufferReadPtr = 0;
1308
pSharedInfo->SoftBufs.ulToneEventBufferSize = pSharedInfo->ChipConfig.ulSoftToneEventsBufSize;
1309
pSharedInfo->SoftBufs.ulToneEventBufferOverflowCnt = 0;
1310
1311
/* Playout */
1312
pSharedInfo->SoftBufs.ulBufPlayoutEventBufferWritePtr = 0;
1313
pSharedInfo->SoftBufs.ulBufPlayoutEventBufferReadPtr = 0;
1314
pSharedInfo->SoftBufs.ulBufPlayoutEventBufferSize = pSharedInfo->ChipConfig.ulSoftBufPlayoutEventsBufSize;
1315
pSharedInfo->SoftBufs.ulBufPlayoutEventBufferOverflowCnt = 0;
1316
1317
/* Set the number of conference bridges opened to zero. */
1318
pSharedInfo->MiscVars.usNumBridgesOpened = 0;
1319
pSharedInfo->MiscVars.usFirstBridge = cOCT6100_INVALID_INDEX;
1320
1321
/* Set the H.100 slave mode. */
1322
pSharedInfo->MiscVars.ulH100SlaveMode = cOCT6100_H100_TRACKA;
1323
1324
/* Save the Mclk value.*/
1325
pSharedInfo->MiscVars.ulMclkFreq = pSharedInfo->ChipConfig.ulMemClkFreq;
1326
1327
/* Init the NLP params. */
1328
pSharedInfo->MiscVars.usCodepoint = 0;
1329
pSharedInfo->MiscVars.usCpuLsuWritePtr = 0;
1330
1331
/* Pouch counter not present until TLVs are read. */
1332
pSharedInfo->DebugInfo.fPouchCounter = FALSE;
1333
pSharedInfo->DebugInfo.fIsIsrCalledField = FALSE;
1334
1335
/* Initialize the image info parameters */
1336
pSharedInfo->ImageInfo.fAdaptiveNoiseReduction = FALSE;
1337
pSharedInfo->ImageInfo.fSoutNoiseBleaching = FALSE;
1338
pSharedInfo->ImageInfo.fComfortNoise = FALSE;
1339
pSharedInfo->ImageInfo.fBufferPlayout = TRUE;
1340
pSharedInfo->ImageInfo.fSoutBufferPlayoutHardSkip = FALSE;
1341
pSharedInfo->ImageInfo.fRinBufferPlayoutHardSkip = FALSE;
1342
pSharedInfo->ImageInfo.fNlpControl = FALSE;
1343
pSharedInfo->ImageInfo.fRinAutoLevelControl = FALSE;
1344
pSharedInfo->ImageInfo.fSoutAutoLevelControl = FALSE;
1345
pSharedInfo->ImageInfo.fAlcNoiseBleedOutTime = FALSE;
1346
pSharedInfo->ImageInfo.fRinHighLevelCompensation = FALSE;
1347
pSharedInfo->ImageInfo.fSoutHighLevelCompensation = FALSE;
1348
pSharedInfo->ImageInfo.fAlcHlcStatus = FALSE;
1349
pSharedInfo->ImageInfo.fRinDcOffsetRemoval = FALSE;
1350
pSharedInfo->ImageInfo.fSilenceSuppression = FALSE;
1351
pSharedInfo->ImageInfo.fSinDcOffsetRemoval = FALSE;
1352
pSharedInfo->ImageInfo.fToneDisabler = FALSE;
1353
pSharedInfo->ImageInfo.fAdpcm = FALSE;
1354
pSharedInfo->ImageInfo.fTailDisplacement = FALSE;
1355
pSharedInfo->ImageInfo.fConferencing = FALSE;
1356
pSharedInfo->ImageInfo.fConferencingNoiseReduction = FALSE;
1357
pSharedInfo->ImageInfo.fDominantSpeakerEnabled = FALSE;
1358
pSharedInfo->ImageInfo.fAecEnabled = FALSE;
1359
pSharedInfo->ImageInfo.fAcousticEcho = FALSE;
1360
pSharedInfo->ImageInfo.fToneRemoval = FALSE;
1361
1362
pSharedInfo->ImageInfo.fDefaultErl = FALSE;
1363
pSharedInfo->ImageInfo.fMaxEchoPoint = FALSE;
1364
pSharedInfo->ImageInfo.fNonLinearityBehaviorA = FALSE;
1365
pSharedInfo->ImageInfo.fNonLinearityBehaviorB = FALSE;
1366
pSharedInfo->ImageInfo.fPerChannelTailDisplacement = FALSE;
1367
pSharedInfo->ImageInfo.fPerChannelTailLength = FALSE;
1368
pSharedInfo->ImageInfo.fAfTailDisplacement = FALSE;
1369
pSharedInfo->ImageInfo.fMusicProtection = FALSE;
1370
pSharedInfo->ImageInfo.fAftControl = FALSE;
1371
pSharedInfo->ImageInfo.fSinVoiceDetectedStat = FALSE;
1372
pSharedInfo->ImageInfo.fRinAppliedGainStat = FALSE;
1373
pSharedInfo->ImageInfo.fSoutAppliedGainStat = FALSE;
1374
pSharedInfo->ImageInfo.fListenerEnhancement = FALSE;
1375
pSharedInfo->ImageInfo.fRoutNoiseReduction = FALSE;
1376
pSharedInfo->ImageInfo.fAnrSnrEnhancement = FALSE;
1377
pSharedInfo->ImageInfo.fAnrVoiceNoiseSegregation = FALSE;
1378
pSharedInfo->ImageInfo.fRinMute = FALSE;
1379
pSharedInfo->ImageInfo.fSinMute = FALSE;
1380
pSharedInfo->ImageInfo.fToneDisablerVqeActivationDelay = FALSE;
1381
pSharedInfo->ImageInfo.fAecTailLength = FALSE;
1382
pSharedInfo->ImageInfo.fMusicProtectionConfiguration= FALSE;
1383
pSharedInfo->ImageInfo.fBufferPlayoutSkipInEvents = FALSE;
1384
pSharedInfo->ImageInfo.fRinEnergyStat = FALSE;
1385
pSharedInfo->ImageInfo.fSoutEnergyStat = FALSE;
1386
pSharedInfo->ImageInfo.fDoubleTalkBehavior = FALSE;
1387
pSharedInfo->ImageInfo.fDoubleTalkBehaviorFieldOfst = FALSE;
1388
pSharedInfo->ImageInfo.fIdleCodeDetection = TRUE;
1389
pSharedInfo->ImageInfo.fIdleCodeDetectionConfiguration = FALSE;
1390
pSharedInfo->ImageInfo.fSinLevel = TRUE;
1391
pSharedInfo->ImageInfo.fResetRinAlcOnTones = FALSE;
1392
pSharedInfo->ImageInfo.fResetSoutAlcOnTones = FALSE;
1393
1394
pSharedInfo->ImageInfo.usMaxNumberOfChannels = 0;
1395
pSharedInfo->ImageInfo.ulToneProfileNumber = cOCT6100_INVALID_VALUE;
1396
pSharedInfo->ImageInfo.ulBuildId = cOCT6100_INVALID_VALUE;
1397
pSharedInfo->ImageInfo.byImageType = cOCT6100_IMAGE_TYPE_WIRELINE;
1398
pSharedInfo->ImageInfo.usMaxTailDisplacement = 0;
1399
pSharedInfo->ImageInfo.usMaxTailLength = cOCT6100_TAIL_LENGTH_128MS;
1400
pSharedInfo->DebugInfo.ulDebugEventSize = 0x100;
1401
pSharedInfo->ImageInfo.byMaxNumberPlayoutEvents = 32;
1402
pSharedInfo->DebugInfo.ulMatrixBaseAddress = cOCT6100_MATRIX_DWORD_BASE;
1403
pSharedInfo->DebugInfo.ulDebugChanStatsByteSize = cOCT6100_DEBUG_CHAN_STATS_EVENT_BYTE_SIZE;
1404
pSharedInfo->DebugInfo.ulDebugChanLiteStatsByteSize = cOCT6100_DEBUG_CHAN_STATS_LITE_EVENT_BYTE_SIZE;
1405
pSharedInfo->DebugInfo.ulHotChannelSelectBaseAddress= cOCT6100_MATRIX_CHAN_SELECT_DWORD_ADD;
1406
pSharedInfo->DebugInfo.ulMatrixTimestampBaseAddress = cOCT6100_MATRIX_TIMESTAMP_DWORD_ADD;
1407
pSharedInfo->DebugInfo.ulMatrixWpBaseAddress = cOCT6100_MATRIX_WRITE_PTR_DWORD_ADD;
1408
pSharedInfo->DebugInfo.ulAfWritePtrByteOffset = 206;
1409
pSharedInfo->DebugInfo.ulRecordedPcmEventByteSize = 4096;
1410
pSharedInfo->DebugInfo.ulAfEventCbByteSize = 0x100000;
1411
1412
/* Set all tones to invalid. */
1413
pSharedInfo->ImageInfo.byNumToneDetectors = 0;
1414
for ( i = 0; i < cOCT6100_MAX_TONE_EVENT; i++ )
1415
{
1416
pSharedInfo->ImageInfo.aToneInfo[ i ].ulToneID = cOCT6100_INVALID_VALUE;
1417
pSharedInfo->ImageInfo.aToneInfo[ i ].ulDetectionPort = cOCT6100_INVALID_PORT;
1418
Oct6100UserMemSet( pSharedInfo->ImageInfo.aToneInfo[ i ].aszToneName, 0x00, cOCT6100_TLV_MAX_TONE_NAME_SIZE );
1419
}
1420
/* Initialize the channel recording info. */
1421
pSharedInfo->DebugInfo.usRecordChanIndex = pSharedInfo->ChipConfig.usMaxChannels;
1422
pSharedInfo->DebugInfo.usRecordMemIndex = cOCT6100_INVALID_INDEX;
1423
1424
pSharedInfo->DebugInfo.usCurrentDebugChanIndex = cOCT6100_INVALID_INDEX;
1425
/* Initialize the mixer information. */
1426
pSharedInfo->MixerInfo.usFirstBridgeEventPtr = cOCT6100_INVALID_INDEX;
1427
pSharedInfo->MixerInfo.usFirstSinCopyEventPtr = cOCT6100_INVALID_INDEX;
1428
pSharedInfo->MixerInfo.usFirstSoutCopyEventPtr = cOCT6100_INVALID_INDEX;
1429
pSharedInfo->MixerInfo.usLastBridgeEventPtr = cOCT6100_INVALID_INDEX;
1430
pSharedInfo->MixerInfo.usLastSinCopyEventPtr = cOCT6100_INVALID_INDEX;
1431
pSharedInfo->MixerInfo.usLastSoutCopyEventPtr = cOCT6100_INVALID_INDEX;
1432
1433
pSharedInfo->MixerInfo.usRecordCopyEventIndex = cOCT6100_INVALID_INDEX;
1434
pSharedInfo->MixerInfo.usRecordSinEventIndex = cOCT6100_INVALID_INDEX;
1435
1436
return cOCT6100_ERR_OK;
1437
}
1438
#endif
1439
1440
1441
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
1442
1443
Function: Oct6100ApiCalculateInstanceSizes
1444
1445
Description: Calculates the amount of memory needed for the instance
1446
structure memory block based on the user's configuration.
1447
1448
-------------------------------------------------------------------------------
1449
| Argument | Description
1450
-------------------------------------------------------------------------------
1451
f_pChipOpen Pointer to user chip configuration structure.
1452
1453
f_pInstSizes Pointer to structure containing the size of memory needed
1454
by all pointers internal to the API instance. The memory
1455
is needed to keep track of the present state of all the
1456
chip's resources.
1457
1458
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
1459
#if !SKIP_Oct6100ApiCalculateInstanceSizes
1460
UINT32 Oct6100ApiCalculateInstanceSizes(
1461
IN OUT tPOCT6100_CHIP_OPEN f_pChipOpen,
1462
OUT tPOCT6100_API_INSTANCE_SIZES f_pInstSizes )
1463
{
1464
UINT32 ulApiInstProcessSpecific;
1465
UINT32 ulTempVar;
1466
UINT32 ulResult;
1467
1468
/* Start with all instance sizes set to 0. */
1469
Oct6100UserMemSet( f_pInstSizes, 0x00, sizeof( tOCT6100_API_INSTANCE_SIZES ) );
1470
1471
/* All memory sizes are rounded up to the next multiple of 64 bytes. */
1472
1473
/*-----------------------------------------------------------------------------*/
1474
/* Obtain size of static members of API instance. */
1475
f_pInstSizes->ulApiInstStatic = sizeof( tOCT6100_SHARED_INFO );
1476
mOCT6100_ROUND_MEMORY_SIZE( f_pInstSizes->ulApiInstStatic, ulTempVar )
1477
1478
/* Calculate memory needed by pointers internal to the API instance. */
1479
1480
/*-----------------------------------------------------------------------------*/
1481
/* Calculate memory needed for the EC channels. */
1482
ulResult = Oct6100ApiGetChannelsEchoSwSizes( f_pChipOpen, f_pInstSizes );
1483
if ( ulResult != cOCT6100_ERR_OK )
1484
return ulResult;
1485
1486
/*-----------------------------------------------------------------------------*/
1487
/* Memory needed by the TSI structures. */
1488
ulResult = Oct6100ApiGetTsiCnctSwSizes( f_pChipOpen, f_pInstSizes );
1489
if ( ulResult != cOCT6100_ERR_OK )
1490
return ulResult;
1491
1492
/*-----------------------------------------------------------------------------*/
1493
/* Calculate memory needed for the conference bridges. */
1494
ulResult = Oct6100ApiGetConfBridgeSwSizes( f_pChipOpen, f_pInstSizes );
1495
if ( ulResult != cOCT6100_ERR_OK )
1496
return ulResult;
1497
1498
/*-----------------------------------------------------------------------------*/
1499
/* Memory needed by the buffer playout structures. */
1500
ulResult = Oct6100ApiGetPlayoutBufferSwSizes( f_pChipOpen, f_pInstSizes );
1501
if ( ulResult != cOCT6100_ERR_OK )
1502
return ulResult;
1503
1504
1505
1506
/*-----------------------------------------------------------------------------*/
1507
/* Memory needed by soft Rx Event buffers. */
1508
ulResult = Oct6100ApiGetEventsSwSizes( f_pChipOpen, f_pInstSizes );
1509
if ( ulResult != cOCT6100_ERR_OK )
1510
return ulResult;
1511
1512
/*-----------------------------------------------------------------------------*/
1513
/* Calculate memory needed for phasing tssts. */
1514
ulResult = Oct6100ApiGetPhasingTsstSwSizes( f_pChipOpen, f_pInstSizes );
1515
if ( ulResult != cOCT6100_ERR_OK )
1516
return ulResult;
1517
1518
/*-----------------------------------------------------------------------------*/
1519
/* Calculate memory needed for the ADPCM channels. */
1520
ulResult = Oct6100ApiGetAdpcmChanSwSizes( f_pChipOpen, f_pInstSizes );
1521
if ( ulResult != cOCT6100_ERR_OK )
1522
return ulResult;
1523
1524
/*-----------------------------------------------------------------------------*/
1525
/* Calculate memory needed for the management of TSSTs. */
1526
ulResult = Oct6100ApiGetTsstSwSizes( f_pInstSizes );
1527
if ( ulResult != cOCT6100_ERR_OK )
1528
return ulResult;
1529
1530
/*-----------------------------------------------------------------------------*/
1531
/* Calculate memory needed for the management of the mixer. */
1532
ulResult = Oct6100ApiGetMixerSwSizes( f_pChipOpen, f_pInstSizes );
1533
if ( ulResult != cOCT6100_ERR_OK )
1534
return ulResult;
1535
1536
/*-----------------------------------------------------------------------------*/
1537
/* Determine amount of memory needed for memory allocation softwares. These
1538
pieces of software will be responsible for the allocation of the chip's
1539
external memory and API memory. */
1540
ulResult = Oct6100ApiGetMemorySwSizes( f_pChipOpen, f_pInstSizes );
1541
if ( ulResult != cOCT6100_ERR_OK )
1542
return ulResult;
1543
1544
/*-----------------------------------------------------------------------------*/
1545
/* Memory needed for remote debugging sessions. */
1546
ulResult = Oct6100ApiGetRemoteDebugSwSizes( f_pChipOpen, f_pInstSizes );
1547
if ( ulResult != cOCT6100_ERR_OK )
1548
return ulResult;
1549
1550
/*-----------------------------------------------------------------------------*/
1551
/* Calculate total memory needed by pointers internal to API instance. The
1552
total contains both the process specific portion of the instance
1553
(tOCT6100_INSTANCE_API) and the shared portion (tOCT6100_SHARED_INFO). The
1554
process specific portion will be used only in the case where the host system
1555
is a single-process one. */
1556
1557
ulApiInstProcessSpecific = sizeof( tOCT6100_INSTANCE_API );
1558
mOCT6100_ROUND_MEMORY_SIZE( ulApiInstProcessSpecific, ulTempVar )
1559
1560
f_pInstSizes->ulApiInstTotal =
1561
f_pInstSizes->ulChannelList +
1562
f_pInstSizes->ulChannelAlloc +
1563
f_pInstSizes->ulTsiCnctList +
1564
f_pInstSizes->ulTsiCnctAlloc +
1565
f_pInstSizes->ulSoftToneEventsBuffer +
1566
f_pInstSizes->ulSoftBufPlayoutEventsBuffer +
1567
f_pInstSizes->ulBiDirChannelList +
1568
f_pInstSizes->ulBiDirChannelAlloc +
1569
f_pInstSizes->ulConfBridgeList +
1570
f_pInstSizes->ulConfBridgeAlloc +
1571
f_pInstSizes->ulFlexConfParticipantsList +
1572
f_pInstSizes->ulFlexConfParticipantsAlloc +
1573
f_pInstSizes->ulPlayoutBufList +
1574
f_pInstSizes->ulPlayoutBufAlloc +
1575
f_pInstSizes->ulPlayoutBufMemoryNodeList +
1576
1577
f_pInstSizes->ulCopyEventList +
1578
f_pInstSizes->ulCopyEventAlloc +
1579
f_pInstSizes->ulMixerEventList +
1580
f_pInstSizes->ulMixerEventAlloc +
1581
f_pInstSizes->ulPhasingTsstList +
1582
f_pInstSizes->ulPhasingTsstAlloc +
1583
f_pInstSizes->ulAdpcmChannelList +
1584
f_pInstSizes->ulAdpcmChannelAlloc +
1585
f_pInstSizes->ulConversionMemoryAlloc +
1586
f_pInstSizes->ulTsiMemoryAlloc +
1587
f_pInstSizes->ulRemoteDebugList +
1588
f_pInstSizes->ulRemoteDebugTree +
1589
f_pInstSizes->ulRemoteDebugPktCache +
1590
f_pInstSizes->ulRemoteDebugDataBuf +
1591
f_pInstSizes->ulTsstEntryList +
1592
f_pInstSizes->ulTsstEntryAlloc +
1593
f_pInstSizes->ulTsstAlloc +
1594
f_pInstSizes->ulApiInstStatic +
1595
ulApiInstProcessSpecific;
1596
1597
return cOCT6100_ERR_OK;
1598
}
1599
#endif
1600
1601
1602
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
1603
1604
Function: Oct6100ApiAllocateInstanceMemory
1605
1606
Description: Allocates the API instance memory to the various members of
1607
the structure f_pApiInstance according to the sizes contained
1608
in f_pInstSizes. No initialization of this memory is
1609
performed.
1610
1611
-------------------------------------------------------------------------------
1612
| Argument | Description
1613
-------------------------------------------------------------------------------
1614
f_pApiInstance Pointer to API instance. This memory is used to keep the
1615
present state of the chip and all its resources.
1616
1617
f_pInstSizes Pointer to structure containing the size of memory needed
1618
by all pointers internal to the API instance. The memory
1619
is needed to keep track of the present state of all the
1620
chip's resources.
1621
1622
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
1623
#if !SKIP_Oct6100ApiAllocateInstanceMemory
1624
UINT32 Oct6100ApiAllocateInstanceMemory(
1625
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance,
1626
IN tPOCT6100_API_INSTANCE_SIZES f_pInstSizes )
1627
{
1628
tPOCT6100_SHARED_INFO pSharedInfo;
1629
UINT32 ulOffset;
1630
1631
/* Get local pointer to shared portion of instance. */
1632
pSharedInfo = f_pApiInstance->pSharedInfo;
1633
1634
/* Get address of first UINT32 of memory in API instance structure following */
1635
/* the static members of the API instance structure. */
1636
ulOffset = f_pInstSizes->ulApiInstStatic;
1637
1638
/*===================================================================*/
1639
/* Allocate memory for the echo channels.*/
1640
pSharedInfo->ulChannelListOfst = ulOffset;
1641
ulOffset += f_pInstSizes->ulChannelList;
1642
pSharedInfo->ulChannelAllocOfst = ulOffset;
1643
ulOffset += f_pInstSizes->ulChannelAlloc;
1644
1645
/*===================================================================*/
1646
/* Allocate memory for the TSI connections */
1647
pSharedInfo->ulTsiCnctListOfst = ulOffset;
1648
ulOffset += f_pInstSizes->ulTsiCnctList;
1649
pSharedInfo->ulTsiCnctAllocOfst = ulOffset;
1650
ulOffset += f_pInstSizes->ulTsiCnctAlloc;
1651
pSharedInfo->ulMixerEventListOfst = ulOffset;
1652
ulOffset += f_pInstSizes->ulMixerEventList;
1653
pSharedInfo->ulMixerEventAllocOfst = ulOffset;
1654
ulOffset += f_pInstSizes->ulMixerEventAlloc;
1655
1656
pSharedInfo->ulBiDirChannelListOfst = ulOffset;
1657
ulOffset += f_pInstSizes->ulBiDirChannelList;
1658
pSharedInfo->ulBiDirChannelAllocOfst = ulOffset;
1659
ulOffset += f_pInstSizes->ulBiDirChannelAlloc;
1660
pSharedInfo->ulCopyEventListOfst = ulOffset;
1661
ulOffset += f_pInstSizes->ulCopyEventList;
1662
pSharedInfo->ulCopyEventAllocOfst = ulOffset;
1663
ulOffset += f_pInstSizes->ulCopyEventAlloc;
1664
1665
/*===================================================================*/
1666
/* Allocate memory for the conference bridges */
1667
pSharedInfo->ulConfBridgeListOfst = ulOffset;
1668
ulOffset += f_pInstSizes->ulConfBridgeList;
1669
pSharedInfo->ulConfBridgeAllocOfst = ulOffset;
1670
ulOffset += f_pInstSizes->ulConfBridgeAlloc;
1671
1672
/*===================================================================*/
1673
/* Allocate memory for the flexible conferencing participants. */
1674
pSharedInfo->ulFlexConfParticipantListOfst = ulOffset;
1675
ulOffset += f_pInstSizes->ulFlexConfParticipantsList;
1676
pSharedInfo->ulFlexConfParticipantAllocOfst = ulOffset;
1677
ulOffset += f_pInstSizes->ulFlexConfParticipantsAlloc;
1678
1679
/*===================================================================*/
1680
/* Allocate memory for the play-out buffers */
1681
pSharedInfo->ulPlayoutBufListOfst = ulOffset;
1682
ulOffset += f_pInstSizes->ulPlayoutBufList;
1683
pSharedInfo->ulPlayoutBufAllocOfst = ulOffset;
1684
ulOffset += f_pInstSizes->ulPlayoutBufAlloc;
1685
pSharedInfo->ulPlayoutBufMemoryNodeListOfst = ulOffset;
1686
ulOffset += f_pInstSizes->ulPlayoutBufMemoryNodeList;
1687
1688
1689
1690
/*===================================================================*/
1691
/* Allocate memory for the phasing TSSTs */
1692
pSharedInfo->ulPhasingTsstListOfst = ulOffset;
1693
ulOffset += f_pInstSizes->ulPhasingTsstList;
1694
pSharedInfo->ulPhasingTsstAllocOfst = ulOffset;
1695
ulOffset += f_pInstSizes->ulPhasingTsstAlloc;
1696
1697
/*===================================================================*/
1698
/* Allocate memory for the ADPCM channel */
1699
pSharedInfo->ulAdpcmChanAllocOfst = ulOffset;
1700
ulOffset += f_pInstSizes->ulAdpcmChannelAlloc;
1701
pSharedInfo->ulAdpcmChanListOfst = ulOffset;
1702
ulOffset += f_pInstSizes->ulAdpcmChannelList;
1703
1704
/*===================================================================*/
1705
/* Allocate memory for the conversion memory */
1706
pSharedInfo->ulConversionMemoryAllocOfst = ulOffset;
1707
ulOffset += f_pInstSizes->ulConversionMemoryAlloc;
1708
1709
/*===================================================================*/
1710
/* Allocate memory for the TSI chariot memory */
1711
pSharedInfo->ulTsiMemoryAllocOfst = ulOffset;
1712
ulOffset += f_pInstSizes->ulTsiMemoryAlloc;
1713
1714
/*===================================================================*/
1715
/* Allocate memory for the TSST management */
1716
pSharedInfo->ulTsstAllocOfst = ulOffset;
1717
ulOffset += f_pInstSizes->ulTsstAlloc;
1718
pSharedInfo->ulTsstListOfst = ulOffset;
1719
ulOffset += f_pInstSizes->ulTsstEntryList;
1720
pSharedInfo->ulTsstListAllocOfst = ulOffset;
1721
ulOffset += f_pInstSizes->ulTsstEntryAlloc;
1722
1723
/*===================================================================*/
1724
pSharedInfo->SoftBufs.ulToneEventBufferMemOfst = ulOffset;
1725
ulOffset += f_pInstSizes->ulSoftToneEventsBuffer;
1726
1727
pSharedInfo->SoftBufs.ulBufPlayoutEventBufferMemOfst = ulOffset;
1728
ulOffset += f_pInstSizes->ulSoftBufPlayoutEventsBuffer;
1729
/*===================================================================*/
1730
pSharedInfo->RemoteDebugInfo.ulSessionListOfst = ulOffset;
1731
ulOffset += f_pInstSizes->ulRemoteDebugList;
1732
1733
pSharedInfo->RemoteDebugInfo.ulSessionTreeOfst = ulOffset;
1734
ulOffset += f_pInstSizes->ulRemoteDebugTree;
1735
1736
pSharedInfo->RemoteDebugInfo.ulDataBufOfst = ulOffset;
1737
ulOffset += f_pInstSizes->ulRemoteDebugDataBuf;
1738
1739
pSharedInfo->RemoteDebugInfo.ulPktCacheOfst = ulOffset;
1740
ulOffset += f_pInstSizes->ulRemoteDebugPktCache;
1741
/*===================================================================*/
1742
1743
return cOCT6100_ERR_OK;
1744
}
1745
#endif
1746
1747
1748
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
1749
1750
Function: Oct6100ApiInitializeInstanceMemory
1751
1752
Description: Initializes the various members of the structure f_pApiInstance
1753
to reflect the current state of the chip and its resources.
1754
1755
-------------------------------------------------------------------------------
1756
| Argument | Description
1757
-------------------------------------------------------------------------------
1758
f_pApiInstance Pointer to API instance. This memory is used to keep the
1759
present state of the chip and all its resources.
1760
1761
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
1762
#if !SKIP_Oct6100ApiInitializeInstanceMemory
1763
UINT32 Oct6100ApiInitializeInstanceMemory(
1764
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
1765
{
1766
UINT32 ulResult;
1767
1768
/*-----------------------------------------------------------------------------*/
1769
/* Initialize API EC channels. */
1770
ulResult = Oct6100ApiChannelsEchoSwInit( f_pApiInstance );
1771
if ( ulResult != cOCT6100_ERR_OK )
1772
return ulResult;
1773
1774
/*-----------------------------------------------------------------------------*/
1775
/* Initialize the API TSI connection structures. */
1776
ulResult = Oct6100ApiTsiCnctSwInit( f_pApiInstance );
1777
if ( ulResult != cOCT6100_ERR_OK )
1778
return ulResult;
1779
1780
/*-----------------------------------------------------------------------------*/
1781
/* Initialize the API conference bridges. */
1782
ulResult = Oct6100ApiConfBridgeSwInit( f_pApiInstance );
1783
if ( ulResult != cOCT6100_ERR_OK )
1784
return ulResult;
1785
1786
/*-----------------------------------------------------------------------------*/
1787
/* Initialize the API buffer playout structures. */
1788
ulResult = Oct6100ApiPlayoutBufferSwInit( f_pApiInstance );
1789
if ( ulResult != cOCT6100_ERR_OK )
1790
return ulResult;
1791
1792
/*-----------------------------------------------------------------------------*/
1793
/* Initialize the API phasing tssts. */
1794
ulResult = Oct6100ApiPhasingTsstSwInit( f_pApiInstance );
1795
if ( ulResult != cOCT6100_ERR_OK )
1796
return ulResult;
1797
1798
/*-----------------------------------------------------------------------------*/
1799
/* Initialize the API ADPCM channels. */
1800
ulResult = Oct6100ApiAdpcmChanSwInit( f_pApiInstance );
1801
if ( ulResult != cOCT6100_ERR_OK )
1802
return ulResult;
1803
1804
/*-----------------------------------------------------------------------------*/
1805
/* Initialize the external memory management structures. */
1806
ulResult = Oct6100ApiMemorySwInit( f_pApiInstance );
1807
if ( ulResult != cOCT6100_ERR_OK )
1808
return ulResult;
1809
1810
/*-----------------------------------------------------------------------------*/
1811
/* Initialize TSST management stuctures. */
1812
ulResult = Oct6100ApiTsstSwInit( f_pApiInstance );
1813
if ( ulResult != cOCT6100_ERR_OK )
1814
return ulResult;
1815
1816
/*-----------------------------------------------------------------------------*/
1817
/* Initialize the mixer management stuctures. */
1818
ulResult = Oct6100ApiMixerSwInit( f_pApiInstance );
1819
if ( ulResult != cOCT6100_ERR_OK )
1820
return ulResult;
1821
1822
/*-----------------------------------------------------------------------------*/
1823
/* Initialize the remote debugging session management variables. */
1824
ulResult = Oct6100ApiRemoteDebuggingSwInit( f_pApiInstance );
1825
if ( ulResult != cOCT6100_ERR_OK )
1826
return ulResult;
1827
1828
/*-----------------------------------------------------------------------------*/
1829
/* Configure the interrupt registers. */
1830
ulResult = Oct6100ApiIsrSwInit( f_pApiInstance );
1831
if ( ulResult != cOCT6100_ERR_OK )
1832
return ulResult;
1833
1834
return cOCT6100_ERR_OK;
1835
}
1836
#endif
1837
1838
1839
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
1840
1841
Function: Oct6100ApiGetChipRevisionNum
1842
1843
Description: Reads the chip's revision number register.
1844
1845
-------------------------------------------------------------------------------
1846
| Argument | Description
1847
-------------------------------------------------------------------------------
1848
f_pApiInstance Pointer to API instance. This memory is used to keep
1849
the present state of the chip and all its resources.
1850
1851
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
1852
#if !SKIP_Oct6100ApiGetChipRevisionNum
1853
UINT32 Oct6100ApiGetChipRevisionNum(
1854
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
1855
{
1856
tPOCT6100_SHARED_INFO pSharedInfo;
1857
tOCT6100_READ_PARAMS ReadParams;
1858
UINT32 ulResult;
1859
UINT16 usReadData;
1860
1861
/* Get local pointer to shared portion of instance. */
1862
pSharedInfo = f_pApiInstance->pSharedInfo;
1863
1864
/* Get the chip revision number. */
1865
ReadParams.pProcessContext = f_pApiInstance->pProcessContext;
1866
1867
ReadParams.ulUserChipId = f_pApiInstance->pSharedInfo->ChipConfig.ulUserChipId;
1868
ReadParams.ulReadAddress = cOCT6100_CHIP_ID_REVISION_REG;
1869
ReadParams.pusReadData = &usReadData;
1870
1871
mOCT6100_DRIVER_READ_API( ReadParams, ulResult )
1872
if ( ulResult != cOCT6100_ERR_OK )
1873
return ulResult;
1874
1875
/* Save the info in the API miscellaneous structure. */
1876
pSharedInfo->MiscVars.usChipId = (UINT16)( usReadData & 0xFF );
1877
pSharedInfo->MiscVars.usChipRevision = (UINT16)( usReadData >> 8 );
1878
1879
return cOCT6100_ERR_OK;
1880
}
1881
#endif
1882
1883
1884
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
1885
1886
Function: Oct6100ApiDecodeKeyAndBist
1887
1888
Description: This function decodes the key and runs the automatic BIST.
1889
1890
-------------------------------------------------------------------------------
1891
| Argument | Description
1892
-------------------------------------------------------------------------------
1893
f_pApiInstance Pointer to API instance. This memory is used to keep the
1894
present state of the chip and all its resources.
1895
1896
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
1897
#if !SKIP_Oct6100ApiDecodeKeyAndBist
1898
UINT32 Oct6100ApiDecodeKeyAndBist(
1899
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
1900
{
1901
tPOCT6100_SHARED_INFO pSharedInfo;
1902
tPOCT6100_API_CHIP_CONFIG pChipConfig;
1903
tOCT6100_WRITE_PARAMS WriteParams;
1904
tOCT6100_READ_PARAMS ReadParams;
1905
UINT16 ausBistData[ 3 ];
1906
UINT16 usReadData;
1907
UINT32 ulResult;
1908
BOOL fBitEqual;
1909
UINT32 i;
1910
1911
/* Get local pointer to shared portion of instance. */
1912
pSharedInfo = f_pApiInstance->pSharedInfo;
1913
1914
/* Obtain a local pointer to the chip config structure */
1915
/* contained in the instance structure. */
1916
pChipConfig = &pSharedInfo->ChipConfig;
1917
1918
/* Set the process context and user chip ID parameters once and for all. */
1919
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
1920
1921
WriteParams.ulUserChipId = pChipConfig->ulUserChipId;
1922
1923
/* Set the process context and user chip ID parameters once and for all. */
1924
ReadParams.pProcessContext = f_pApiInstance->pProcessContext;
1925
1926
ReadParams.ulUserChipId = pChipConfig->ulUserChipId;
1927
1928
/* Write key in CPU internal memory. */
1929
for(i=0; i<8; i++)
1930
{
1931
WriteParams.ulWriteAddress = 0x150;
1932
WriteParams.usWriteData = 0x0000;
1933
if (( i % 2 ) == 0)
1934
{
1935
WriteParams.usWriteData |= ((UINT16)pChipConfig->pbyImageFile[0x100 + ((i/2)*4) + 2]) << 8;
1936
WriteParams.usWriteData |= ((UINT16)pChipConfig->pbyImageFile[0x100 + ((i/2)*4) + 3]) << 0;
1937
}
1938
else
1939
{
1940
WriteParams.usWriteData |= ((UINT16)pChipConfig->pbyImageFile[0x100 + ((i/2)*4) + 0]) << 8;
1941
WriteParams.usWriteData |= ((UINT16)pChipConfig->pbyImageFile[0x100 + ((i/2)*4) + 1]) << 0;
1942
}
1943
1944
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
1945
if ( ulResult != cOCT6100_ERR_OK )
1946
return ulResult;
1947
1948
WriteParams.ulWriteAddress = 0x152;
1949
WriteParams.usWriteData = (UINT16)( 0x8000 | i );
1950
1951
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
1952
if ( ulResult != cOCT6100_ERR_OK )
1953
return ulResult;
1954
}
1955
1956
/* Write one in CPU internal memory. */
1957
for(i=0; i<8; i++)
1958
{
1959
WriteParams.ulWriteAddress = 0x150;
1960
if (i == 0)
1961
{
1962
WriteParams.usWriteData = 0x0001;
1963
}
1964
else
1965
{
1966
WriteParams.usWriteData = 0x0000;
1967
}
1968
1969
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
1970
if ( ulResult != cOCT6100_ERR_OK )
1971
return ulResult;
1972
1973
WriteParams.ulWriteAddress = 0x152;
1974
WriteParams.usWriteData = (UINT16)( 0x8000 | ( i + 8 ));
1975
1976
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
1977
if ( ulResult != cOCT6100_ERR_OK )
1978
return ulResult;
1979
}
1980
1981
/* Clear memory access registers: */
1982
WriteParams.ulWriteAddress = 0x150;
1983
WriteParams.usWriteData = 0x0000;
1984
1985
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
1986
if ( ulResult != cOCT6100_ERR_OK )
1987
return ulResult;
1988
1989
WriteParams.ulWriteAddress = 0x152;
1990
1991
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
1992
if ( ulResult != cOCT6100_ERR_OK )
1993
return ulResult;
1994
1995
/* Run BISTs and key decode. */
1996
WriteParams.ulWriteAddress = 0x160;
1997
WriteParams.usWriteData = 0x0081;
1998
1999
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2000
if ( ulResult != cOCT6100_ERR_OK )
2001
return ulResult;
2002
2003
/* Wait for the key decode PC to clear. */
2004
ulResult = Oct6100ApiWaitForPcRegisterBit( f_pApiInstance, 0x160, 0, 0, 100000, &fBitEqual );
2005
if ( TRUE != fBitEqual )
2006
return cOCT6100_ERR_FATAL_13;
2007
2008
/* Read the key valid bit to make sure everything is ok. */
2009
ReadParams.ulReadAddress = 0x160;
2010
ReadParams.pusReadData = &usReadData;
2011
2012
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
2013
if ( ulResult != cOCT6100_ERR_OK )
2014
return ulResult;
2015
2016
/* Either the firmware image was not loaded correctly (from pointer given by user) */
2017
/* or the channel capacity pins of the chip do not match what the firmware is expecting. */
2018
if ( ( usReadData & 0x4 ) == 0 )
2019
return cOCT6100_ERR_OPEN_INVALID_FIRMWARE_OR_CAPACITY_PINS;
2020
2021
/* Read the result of the internal memory bist. */
2022
ReadParams.ulReadAddress = 0x110;
2023
ReadParams.pusReadData = &ausBistData[ 0 ];
2024
2025
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
2026
if ( ulResult != cOCT6100_ERR_OK )
2027
return ulResult;
2028
2029
ReadParams.ulReadAddress = 0x114;
2030
ReadParams.pusReadData = &ausBistData[ 1 ];
2031
2032
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
2033
if ( ulResult != cOCT6100_ERR_OK )
2034
return ulResult;
2035
2036
ReadParams.ulReadAddress = 0x118;
2037
ReadParams.pusReadData = &ausBistData[ 2 ];
2038
2039
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
2040
if ( ulResult != cOCT6100_ERR_OK )
2041
return ulResult;
2042
2043
/* Check if an error was reported. */
2044
if (ausBistData[0] != 0x0000 || ausBistData[1] != 0x0000 || ausBistData[2] != 0x0000)
2045
return cOCT6100_ERR_OPEN_INTERNAL_MEMORY_BIST;
2046
2047
/* Put key decoder in powerdown. */
2048
WriteParams.ulWriteAddress = 0x160;
2049
WriteParams.usWriteData = 0x008A;
2050
2051
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2052
if ( ulResult != cOCT6100_ERR_OK )
2053
return ulResult;
2054
2055
return cOCT6100_ERR_OK;
2056
}
2057
#endif
2058
2059
2060
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
2061
2062
Function: Oct6100ApiBootFc2Pll
2063
2064
Description: Configures the chip's FC2 PLL.
2065
2066
-------------------------------------------------------------------------------
2067
| Argument | Description
2068
-------------------------------------------------------------------------------
2069
f_pApiInstance Pointer to API instance. This memory is used to keep the
2070
present state of the chip and all its resources.
2071
2072
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
2073
#if !SKIP_Oct6100ApiBootFc2Pll
2074
UINT32 Oct6100ApiBootFc2Pll(
2075
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
2076
{
2077
tPOCT6100_SHARED_INFO pSharedInfo;
2078
tPOCT6100_API_CHIP_CONFIG pChipConfig;
2079
tOCT6100_WRITE_PARAMS WriteParams;
2080
UINT32 aulWaitTime[ 2 ];
2081
UINT32 ulResult;
2082
UINT32 ulFc2PllDivisor = 0;
2083
UINT32 ulMtDivisor = 0;
2084
UINT32 ulFcDivisor = 0;
2085
2086
/* Get local pointer to shared portion of instance. */
2087
pSharedInfo = f_pApiInstance->pSharedInfo;
2088
2089
/* Obtain local pointer to chip configuration structure. */
2090
pChipConfig = &pSharedInfo->ChipConfig;
2091
2092
/* Set the process context and user chip ID parameters once and for all. */
2093
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
2094
2095
WriteParams.ulUserChipId = pChipConfig->ulUserChipId;
2096
2097
/* First put the chip and main registers in soft-reset. */
2098
WriteParams.ulWriteAddress = 0x100;
2099
WriteParams.usWriteData = 0x0;
2100
2101
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
2102
if ( ulResult != cOCT6100_ERR_OK )
2103
return ulResult;
2104
2105
/* Select register configuration based on the memory frequency. */
2106
switch ( f_pApiInstance->pSharedInfo->ChipConfig.ulMemClkFreq )
2107
{
2108
case 133000000:
2109
ulFc2PllDivisor = 0x1050;
2110
ulMtDivisor = 0x4300;
2111
ulFcDivisor = 0x4043;
2112
pSharedInfo->MiscVars.usMaxNumberOfChannels = 672;
2113
pSharedInfo->MiscVars.usMaxH100Speed = 124;
2114
2115
if ( pSharedInfo->ChipConfig.fEnableFastH100Mode == TRUE )
2116
pSharedInfo->MiscVars.usTdmClkBoundary = 0x050B;
2117
else
2118
pSharedInfo->MiscVars.usTdmClkBoundary = 0x0516;
2119
2120
break;
2121
case 125000000:
2122
ulFc2PllDivisor = 0x0F50;
2123
ulMtDivisor = 0x4300;
2124
ulFcDivisor = 0x4043;
2125
pSharedInfo->MiscVars.usMaxNumberOfChannels = 624;
2126
pSharedInfo->MiscVars.usMaxH100Speed = 116;
2127
2128
if ( pSharedInfo->ChipConfig.fEnableFastH100Mode == TRUE )
2129
pSharedInfo->MiscVars.usTdmClkBoundary = 0x04CA;
2130
else
2131
pSharedInfo->MiscVars.usTdmClkBoundary = 0x04D4;
2132
2133
break;
2134
case 117000000:
2135
ulFc2PllDivisor = 0x0E50;
2136
ulMtDivisor = 0x4300;
2137
ulFcDivisor = 0x4043;
2138
pSharedInfo->MiscVars.usMaxNumberOfChannels = 576;
2139
pSharedInfo->MiscVars.usMaxH100Speed = 108;
2140
2141
if ( pSharedInfo->ChipConfig.fEnableFastH100Mode == TRUE )
2142
pSharedInfo->MiscVars.usTdmClkBoundary = 0x0489;
2143
else
2144
pSharedInfo->MiscVars.usTdmClkBoundary = 0x0492;
2145
2146
break;
2147
case 108000000:
2148
ulFc2PllDivisor = 0x0D50;
2149
ulMtDivisor = 0x4300;
2150
ulFcDivisor = 0x4043;
2151
pSharedInfo->MiscVars.usMaxNumberOfChannels = 528;
2152
pSharedInfo->MiscVars.usMaxH100Speed = 99;
2153
2154
if ( pSharedInfo->ChipConfig.fEnableFastH100Mode == TRUE )
2155
pSharedInfo->MiscVars.usTdmClkBoundary = 0x0408;
2156
else
2157
pSharedInfo->MiscVars.usTdmClkBoundary = 0x0410;
2158
2159
break;
2160
case 100000000:
2161
ulFc2PllDivisor = 0x0C50;
2162
ulMtDivisor = 0x4300;
2163
ulFcDivisor = 0x4043;
2164
pSharedInfo->MiscVars.usMaxNumberOfChannels = 480;
2165
pSharedInfo->MiscVars.usMaxH100Speed = 91;
2166
2167
if ( pSharedInfo->ChipConfig.fEnableFastH100Mode == TRUE )
2168
pSharedInfo->MiscVars.usTdmClkBoundary = 0x03C8;
2169
else
2170
pSharedInfo->MiscVars.usTdmClkBoundary = 0x03D0;
2171
2172
break;
2173
case 92000000:
2174
ulFc2PllDivisor = 0x0B50;
2175
ulMtDivisor = 0x4300;
2176
ulFcDivisor = 0x4043;
2177
pSharedInfo->MiscVars.usMaxNumberOfChannels = 432;
2178
pSharedInfo->MiscVars.usMaxH100Speed = 83;
2179
2180
if ( pSharedInfo->ChipConfig.fEnableFastH100Mode == TRUE )
2181
pSharedInfo->MiscVars.usTdmClkBoundary = 0x0387;
2182
else
2183
pSharedInfo->MiscVars.usTdmClkBoundary = 0x038E;
2184
2185
break;
2186
case 83000000:
2187
ulFc2PllDivisor = 0x0A50;
2188
ulMtDivisor = 0x4300;
2189
ulFcDivisor = 0x4043;
2190
pSharedInfo->MiscVars.usMaxNumberOfChannels = 384;
2191
pSharedInfo->MiscVars.usMaxH100Speed = 74;
2192
2193
if ( pSharedInfo->ChipConfig.fEnableFastH100Mode == TRUE )
2194
pSharedInfo->MiscVars.usTdmClkBoundary = 0x0346;
2195
else
2196
pSharedInfo->MiscVars.usTdmClkBoundary = 0x034C;
2197
2198
break;
2199
case 75000000:
2200
ulFc2PllDivisor = 0x0950;
2201
ulMtDivisor = 0x4200;
2202
ulFcDivisor = 0x4043;
2203
pSharedInfo->MiscVars.usMaxNumberOfChannels = 336;
2204
pSharedInfo->MiscVars.usMaxH100Speed = 64;
2205
2206
if ( pSharedInfo->ChipConfig.fEnableFastH100Mode == TRUE )
2207
pSharedInfo->MiscVars.usTdmClkBoundary = 0x0306;
2208
else
2209
pSharedInfo->MiscVars.usTdmClkBoundary = 0x030C;
2210
2211
break;
2212
default:
2213
return cOCT6100_ERR_FATAL_DB;
2214
}
2215
2216
/* Verify that the max channel is not too big based on the chip frequency. */
2217
if ( pSharedInfo->ChipConfig.usMaxChannels > pSharedInfo->MiscVars.usMaxNumberOfChannels )
2218
return cOCT6100_ERR_OPEN_MAX_ECHO_CHANNELS;
2219
2220
/* Setup delay chains. */
2221
if ( (pChipConfig->byMemoryType == cOCT6100_MEM_TYPE_SDR) || (pChipConfig->byMemoryType == cOCT6100_MEM_TYPE_SDR_PLL_BYPASS) )
2222
{
2223
/* SDRAM */
2224
WriteParams.ulWriteAddress = 0x1B0;
2225
WriteParams.usWriteData = 0x1003;
2226
2227
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2228
if ( ulResult != cOCT6100_ERR_OK )
2229
return ulResult;
2230
2231
WriteParams.ulWriteAddress = 0x1B2;
2232
WriteParams.usWriteData = 0x0021;
2233
2234
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2235
if ( ulResult != cOCT6100_ERR_OK )
2236
return ulResult;
2237
2238
WriteParams.ulWriteAddress = 0x1B4;
2239
WriteParams.usWriteData = 0x4030;
2240
2241
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2242
if ( ulResult != cOCT6100_ERR_OK )
2243
return ulResult;
2244
2245
WriteParams.ulWriteAddress = 0x1B6;
2246
WriteParams.usWriteData = 0x0021;
2247
2248
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2249
if ( ulResult != cOCT6100_ERR_OK )
2250
return ulResult;
2251
}
2252
else /* if ( cOCT6100_MEM_TYPE_DDR == pChipConfig->byMemoryType ) */
2253
{
2254
/* DDR */
2255
WriteParams.ulWriteAddress = 0x1B0;
2256
WriteParams.usWriteData = 0x201F;
2257
2258
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2259
if ( ulResult != cOCT6100_ERR_OK )
2260
return ulResult;
2261
2262
WriteParams.ulWriteAddress = 0x1B2;
2263
WriteParams.usWriteData = 0x0021;
2264
2265
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2266
if ( ulResult != cOCT6100_ERR_OK )
2267
return ulResult;
2268
2269
WriteParams.ulWriteAddress = 0x1B4;
2270
WriteParams.usWriteData = 0x1000;
2271
2272
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2273
if ( ulResult != cOCT6100_ERR_OK )
2274
return ulResult;
2275
2276
WriteParams.ulWriteAddress = 0x1B6;
2277
WriteParams.usWriteData = 0x0021;
2278
2279
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2280
if ( ulResult != cOCT6100_ERR_OK )
2281
return ulResult;
2282
}
2283
2284
/* udqs */
2285
WriteParams.ulWriteAddress = 0x1B8;
2286
WriteParams.usWriteData = 0x1003;
2287
2288
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2289
if ( ulResult != cOCT6100_ERR_OK )
2290
return ulResult;
2291
2292
WriteParams.ulWriteAddress = 0x1BA;
2293
WriteParams.usWriteData = 0x0021;
2294
2295
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2296
if ( ulResult != cOCT6100_ERR_OK )
2297
return ulResult;
2298
2299
/* ldqs */
2300
WriteParams.ulWriteAddress = 0x1BC;
2301
WriteParams.usWriteData = 0x1000;
2302
2303
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2304
if ( ulResult != cOCT6100_ERR_OK )
2305
return ulResult;
2306
2307
WriteParams.ulWriteAddress = 0x1BE;
2308
WriteParams.usWriteData = 0x0021;
2309
2310
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2311
if ( ulResult != cOCT6100_ERR_OK )
2312
return ulResult;
2313
2314
WriteParams.ulWriteAddress = 0x12C;
2315
WriteParams.usWriteData = 0x0000;
2316
2317
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2318
if ( ulResult != cOCT6100_ERR_OK )
2319
return ulResult;
2320
2321
WriteParams.ulWriteAddress = 0x12E;
2322
WriteParams.usWriteData = 0x0000;
2323
2324
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2325
if ( ulResult != cOCT6100_ERR_OK )
2326
return ulResult;
2327
2328
/* Select fc2pll for fast_clk and mtsclk sources. Select mem_clk_i for afclk. */
2329
WriteParams.ulWriteAddress = 0x140;
2330
WriteParams.usWriteData = (UINT16)ulMtDivisor;
2331
2332
if ( f_pApiInstance->pSharedInfo->ChipConfig.byMemoryType == cOCT6100_MEM_TYPE_SDR_PLL_BYPASS )
2333
WriteParams.usWriteData |= 0x0001;
2334
else
2335
WriteParams.usWriteData |= 0x0004;
2336
2337
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2338
if ( ulResult != cOCT6100_ERR_OK )
2339
return ulResult;
2340
2341
WriteParams.ulWriteAddress = 0x144;
2342
WriteParams.usWriteData = (UINT16)ulFcDivisor;
2343
2344
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2345
if ( ulResult != cOCT6100_ERR_OK )
2346
return ulResult;
2347
2348
WriteParams.ulWriteAddress = 0x13E;
2349
WriteParams.usWriteData = 0x0001; /* Remove reset from above divisors */
2350
2351
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2352
if ( ulResult != cOCT6100_ERR_OK )
2353
return ulResult;
2354
2355
/* Select upclk directly as ref source for fc2pll. */
2356
WriteParams.ulWriteAddress = 0x134;
2357
WriteParams.usWriteData = 0x0001;
2358
2359
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2360
if ( ulResult != cOCT6100_ERR_OK )
2361
return ulResult;
2362
2363
/* Setup fc2pll. */
2364
WriteParams.ulWriteAddress = 0x132;
2365
WriteParams.usWriteData = (UINT16)ulFc2PllDivisor;
2366
2367
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2368
if ( ulResult != cOCT6100_ERR_OK )
2369
return ulResult;
2370
2371
WriteParams.usWriteData |= 0x02; /* Raise fb divisor reset. */
2372
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2373
if ( ulResult != cOCT6100_ERR_OK )
2374
return ulResult;
2375
2376
WriteParams.usWriteData |= 0x80; /* Raise IDDTN signal.*/
2377
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2378
if ( ulResult != cOCT6100_ERR_OK )
2379
return ulResult;
2380
2381
/* Wait for fc2pll to stabilize. */
2382
aulWaitTime[ 0 ] = 2000;
2383
aulWaitTime[ 1 ] = 0;
2384
ulResult = Oct6100ApiWaitForTime( f_pApiInstance, aulWaitTime );
2385
if ( ulResult != cOCT6100_ERR_OK )
2386
return ulResult;
2387
2388
/* Drive mem_clk_o out on proper interface. */
2389
if ( TRUE == pChipConfig->fEnableMemClkOut )
2390
{
2391
if ( (pChipConfig->byMemoryType == cOCT6100_MEM_TYPE_SDR) || (pChipConfig->byMemoryType == cOCT6100_MEM_TYPE_SDR_PLL_BYPASS) )
2392
{
2393
WriteParams.ulWriteAddress = 0x128;
2394
WriteParams.usWriteData = 0x0301;
2395
2396
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2397
if ( ulResult != cOCT6100_ERR_OK )
2398
return ulResult;
2399
}
2400
2401
if ( pChipConfig->byMemoryType == cOCT6100_MEM_TYPE_DDR || pChipConfig->byMemoryType == cOCT6100_MEM_TYPE_SDR_PLL_BYPASS )
2402
{
2403
WriteParams.ulWriteAddress = 0x12A;
2404
WriteParams.usWriteData = 0x000F;
2405
2406
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2407
if ( ulResult != cOCT6100_ERR_OK )
2408
return ulResult;
2409
}
2410
}
2411
2412
return cOCT6100_ERR_OK;
2413
}
2414
#endif
2415
2416
2417
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
2418
2419
Function: Oct6100ApiProgramFc1Pll
2420
2421
Description: Configures the chip's FC1 PLL.
2422
2423
-------------------------------------------------------------------------------
2424
| Argument | Description
2425
-------------------------------------------------------------------------------
2426
f_pApiInstance Pointer to API instance. This memory is used to keep the
2427
present state of the chip and all its resources.
2428
2429
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
2430
#if !SKIP_Oct6100ApiProgramFc1Pll
2431
UINT32 Oct6100ApiProgramFc1Pll(
2432
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
2433
{
2434
tPOCT6100_SHARED_INFO pSharedInfo;
2435
tPOCT6100_API_CHIP_CONFIG pChipConfig;
2436
tOCT6100_WRITE_PARAMS WriteParams;
2437
UINT32 aulWaitTime[ 2 ];
2438
UINT32 ulResult;
2439
2440
/* Get local pointer to shared portion of instance. */
2441
pSharedInfo = f_pApiInstance->pSharedInfo;
2442
2443
/* Obtain local pointer to chip configuration structure. */
2444
pChipConfig = &pSharedInfo->ChipConfig;
2445
2446
/* Set the process context and user chip ID parameters once and for all. */
2447
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
2448
2449
WriteParams.ulUserChipId = pChipConfig->ulUserChipId;
2450
2451
/* Programm P/Z bits. */
2452
WriteParams.ulWriteAddress = 0x130;
2453
2454
if ( f_pApiInstance->pSharedInfo->ChipConfig.byMemoryType == cOCT6100_MEM_TYPE_SDR_PLL_BYPASS )
2455
WriteParams.usWriteData = 0x0041;
2456
else
2457
WriteParams.usWriteData = 0x0040;
2458
2459
WriteParams.usWriteData |= ( pChipConfig->byMemoryType << 8 );
2460
2461
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2462
if ( ulResult != cOCT6100_ERR_OK )
2463
return ulResult;
2464
2465
/* Raise FB divisor. */
2466
WriteParams.usWriteData |= 0x0002;
2467
2468
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2469
if ( ulResult != cOCT6100_ERR_OK )
2470
return ulResult;
2471
2472
/* Raise IDDTN. */
2473
WriteParams.usWriteData |= 0x0080;
2474
2475
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2476
if ( ulResult != cOCT6100_ERR_OK )
2477
return ulResult;
2478
2479
/* Wait for fc1pll to stabilize. */
2480
aulWaitTime[ 0 ] = 2000;
2481
aulWaitTime[ 1 ] = 0;
2482
ulResult = Oct6100ApiWaitForTime( f_pApiInstance, aulWaitTime );
2483
if ( ulResult != cOCT6100_ERR_OK )
2484
return ulResult;
2485
2486
/* Enable all the clock domains to do reset procedure. */
2487
WriteParams.ulWriteAddress = 0x186;
2488
WriteParams.usWriteData = 0x015F;
2489
2490
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2491
if ( ulResult != cOCT6100_ERR_OK )
2492
return ulResult;
2493
2494
aulWaitTime[ 0 ] = 15000;
2495
aulWaitTime[ 1 ] = 0;
2496
ulResult = Oct6100ApiWaitForTime( f_pApiInstance, aulWaitTime );
2497
if ( ulResult != cOCT6100_ERR_OK )
2498
return ulResult;
2499
2500
return cOCT6100_ERR_OK;
2501
}
2502
#endif
2503
2504
2505
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
2506
2507
Function: Oct6100ApiBootFc1Pll
2508
2509
Description: Boot the chip's FC1 PLL.
2510
2511
-------------------------------------------------------------------------------
2512
| Argument | Description
2513
-------------------------------------------------------------------------------
2514
f_pApiInstance Pointer to API instance. This memory is used to keep the
2515
present state of the chip and all its resources.
2516
2517
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
2518
#if !SKIP_Oct6100ApiBootFc1Pll
2519
UINT32 Oct6100ApiBootFc1Pll(
2520
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
2521
{
2522
tPOCT6100_SHARED_INFO pSharedInfo;
2523
tPOCT6100_API_CHIP_CONFIG pChipConfig;
2524
tOCT6100_WRITE_PARAMS WriteParams;
2525
UINT32 aulWaitTime[ 2 ];
2526
UINT32 ulResult;
2527
2528
/* Get local pointer to shared portion of instance. */
2529
pSharedInfo = f_pApiInstance->pSharedInfo;
2530
2531
/* Obtain local pointer to chip configuration structure. */
2532
pChipConfig = &pSharedInfo->ChipConfig;
2533
2534
/* Set the process context and user chip ID parameters once and for all. */
2535
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
2536
2537
WriteParams.ulUserChipId = pChipConfig->ulUserChipId;
2538
2539
/* Force bist_clk also (it too is used on resetable flops). */
2540
WriteParams.ulWriteAddress = 0x160;
2541
WriteParams.usWriteData = 0x0188;
2542
2543
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2544
if ( ulResult != cOCT6100_ERR_OK )
2545
return ulResult;
2546
2547
/* Force all cpu clocks on chariot controllers. */
2548
WriteParams.ulWriteAddress = 0x182;
2549
WriteParams.usWriteData = 0x0002;
2550
2551
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2552
if ( ulResult != cOCT6100_ERR_OK )
2553
return ulResult;
2554
2555
WriteParams.ulWriteAddress = 0x184;
2556
WriteParams.usWriteData = 0x0202;
2557
2558
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2559
if ( ulResult != cOCT6100_ERR_OK )
2560
return ulResult;
2561
2562
aulWaitTime[ 0 ] = 1000;
2563
aulWaitTime[ 1 ] = 0;
2564
ulResult = Oct6100ApiWaitForTime( f_pApiInstance, aulWaitTime );
2565
if ( ulResult != cOCT6100_ERR_OK )
2566
return ulResult;
2567
2568
/* Remove the reset on the entire chip and disable CPU access caching. */
2569
WriteParams.ulWriteAddress = 0x100;
2570
WriteParams.usWriteData = 0x2003;
2571
2572
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2573
if ( ulResult != cOCT6100_ERR_OK )
2574
return ulResult;
2575
2576
/* Remove the bist_clk. It is no longer needed.*/
2577
WriteParams.ulWriteAddress = 0x160;
2578
WriteParams.usWriteData = 0x0088;
2579
2580
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2581
if ( ulResult != cOCT6100_ERR_OK )
2582
return ulResult;
2583
2584
/* Disable all clks to prepare for bist clock switchover. */
2585
WriteParams.ulWriteAddress = 0x182;
2586
WriteParams.usWriteData = 0x0001;
2587
2588
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2589
if ( ulResult != cOCT6100_ERR_OK )
2590
return ulResult;
2591
2592
WriteParams.ulWriteAddress = 0x186;
2593
WriteParams.usWriteData = 0x0000;
2594
2595
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2596
if ( ulResult != cOCT6100_ERR_OK )
2597
return ulResult;
2598
2599
WriteParams.ulWriteAddress = 0x184;
2600
WriteParams.usWriteData = 0x0101;
2601
2602
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2603
if ( ulResult != cOCT6100_ERR_OK )
2604
return ulResult;
2605
2606
ulResult = Oct6100ApiWaitForTime( f_pApiInstance, aulWaitTime );
2607
if ( ulResult != cOCT6100_ERR_OK )
2608
return ulResult;
2609
2610
/* Deassert bist_active */
2611
WriteParams.ulWriteAddress = 0x160;
2612
WriteParams.usWriteData = 0x0008;
2613
2614
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2615
if ( ulResult != cOCT6100_ERR_OK )
2616
return ulResult;
2617
2618
/* Change CPU interface to normal mode (from boot mode). */
2619
WriteParams.ulWriteAddress = 0x154;
2620
WriteParams.usWriteData = 0x0000;
2621
2622
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2623
if ( ulResult != cOCT6100_ERR_OK )
2624
return ulResult;
2625
2626
ulResult = Oct6100ApiWaitForTime( f_pApiInstance, aulWaitTime );
2627
if ( ulResult != cOCT6100_ERR_OK )
2628
return ulResult;
2629
2630
/* Give a couple of BIST clock cycles to turn off the BIST permanently. */
2631
WriteParams.ulWriteAddress = 0x160;
2632
WriteParams.usWriteData = 0x0108;
2633
2634
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2635
if ( ulResult != cOCT6100_ERR_OK )
2636
return ulResult;
2637
2638
ulResult = Oct6100ApiWaitForTime( f_pApiInstance, aulWaitTime );
2639
if ( ulResult != cOCT6100_ERR_OK )
2640
return ulResult;
2641
2642
/* Turn BIST clock off for the last time. */
2643
WriteParams.ulWriteAddress = 0x160;
2644
WriteParams.usWriteData = 0x0008;
2645
2646
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2647
if ( ulResult != cOCT6100_ERR_OK )
2648
return ulResult;
2649
2650
/* Reset procedure done! */
2651
2652
/* Enable mclk for cpu interface and external memory controller. */
2653
WriteParams.ulWriteAddress = 0x186;
2654
WriteParams.usWriteData = 0x0100;
2655
2656
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2657
if ( ulResult != cOCT6100_ERR_OK )
2658
return ulResult;
2659
2660
return cOCT6100_ERR_OK;
2661
}
2662
#endif
2663
2664
2665
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
2666
2667
Function: Oct6100ApiLoadImage
2668
2669
Description: This function writes the firmware image in the external memory.
2670
2671
-------------------------------------------------------------------------------
2672
| Argument | Description
2673
-------------------------------------------------------------------------------
2674
f_pApiInstance Pointer to API instance. This memory is used to keep the
2675
present state of the chip and all its resources.
2676
2677
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
2678
#if !SKIP_Oct6100ApiLoadImage
2679
UINT32 Oct6100ApiLoadImage(
2680
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
2681
{
2682
tPOCT6100_SHARED_INFO pSharedInfo;
2683
tOCT6100_WRITE_BURST_PARAMS BurstParams;
2684
tOCT6100_READ_PARAMS ReadParams;
2685
UINT32 ulResult;
2686
UINT32 ulTempPtr;
2687
UINT32 ulNumWrites;
2688
PUINT16 pusSuperArray;
2689
PUINT8 pbyImageFile;
2690
UINT32 ulByteCount = 0;
2691
UINT16 usReadData;
2692
UINT32 ulAddressOfst;
2693
UINT32 i;
2694
2695
/* Get local pointer to shared portion of instance. */
2696
pSharedInfo = f_pApiInstance->pSharedInfo;
2697
2698
/* Set the process context and user chip ID parameters once and for all. */
2699
BurstParams.pProcessContext = f_pApiInstance->pProcessContext;
2700
2701
BurstParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
2702
2703
ReadParams.pProcessContext = f_pApiInstance->pProcessContext;
2704
2705
ReadParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
2706
ReadParams.pusReadData = &usReadData;
2707
2708
/* Breakdown image into subcomponents. */
2709
ulTempPtr = cOCT6100_IMAGE_FILE_BASE + cOCT6100_IMAGE_AF_CST_OFFSET;
2710
2711
for(i=0;i<cOCT6100_MAX_IMAGE_REGION;i++)
2712
{
2713
pSharedInfo->ImageRegion[ i ].ulPart1Size = pSharedInfo->ChipConfig.pbyImageFile[ 0x110 + ( i * 4 ) + 0 ];
2714
pSharedInfo->ImageRegion[ i ].ulPart2Size = pSharedInfo->ChipConfig.pbyImageFile[ 0x110 + ( i * 4 ) + 1 ];
2715
pSharedInfo->ImageRegion[ i ].ulClockInfo = pSharedInfo->ChipConfig.pbyImageFile[ 0x110 + ( i * 4 ) + 2 ];
2716
pSharedInfo->ImageRegion[ i ].ulReserved = pSharedInfo->ChipConfig.pbyImageFile[ 0x110 + ( i * 4 ) + 3 ];
2717
2718
if (i == 0) /* AF constant. */
2719
{
2720
pSharedInfo->ImageRegion[ i ].ulPart1BaseAddress = ulTempPtr & 0x07FFFFFF;
2721
pSharedInfo->ImageRegion[ i ].ulPart2BaseAddress = 0;
2722
2723
ulTempPtr += ( pSharedInfo->ImageRegion[ i ].ulPart1Size * 612 );
2724
}
2725
else if (i == 1) /* NLP image */
2726
{
2727
pSharedInfo->ImageRegion[ i ].ulPart1BaseAddress = ulTempPtr & 0x07FFFFFF;
2728
pSharedInfo->ImageRegion[ i ].ulPart2BaseAddress = 0;
2729
2730
ulTempPtr += ( pSharedInfo->ImageRegion[ i ].ulPart1Size * 2056 );
2731
}
2732
else /* Others */
2733
{
2734
pSharedInfo->ImageRegion[ i ].ulPart1BaseAddress = ulTempPtr & 0x07FFFFFF;
2735
ulTempPtr += ( pSharedInfo->ImageRegion[ i ].ulPart1Size * 2064 );
2736
2737
pSharedInfo->ImageRegion[ i ].ulPart2BaseAddress = ulTempPtr & 0x07FFFFFF;
2738
ulTempPtr += ( pSharedInfo->ImageRegion[ i ].ulPart2Size * 2448 );
2739
}
2740
}
2741
2742
/* Write the image in external memory. */
2743
ulNumWrites = pSharedInfo->ChipConfig.ulImageSize / 2;
2744
2745
BurstParams.ulWriteAddress = cOCT6100_IMAGE_FILE_BASE;
2746
BurstParams.pusWriteData = pSharedInfo->MiscVars.ausSuperArray;
2747
2748
pusSuperArray = pSharedInfo->MiscVars.ausSuperArray;
2749
pbyImageFile = pSharedInfo->ChipConfig.pbyImageFile;
2750
2751
while ( ulNumWrites != 0 )
2752
{
2753
if ( ulNumWrites >= pSharedInfo->ChipConfig.usMaxRwAccesses )
2754
BurstParams.ulWriteLength = pSharedInfo->ChipConfig.usMaxRwAccesses;
2755
else
2756
BurstParams.ulWriteLength = ulNumWrites;
2757
2758
for ( i = 0; i < BurstParams.ulWriteLength; i++ )
2759
{
2760
pusSuperArray[ i ] = ( UINT16 )(( pbyImageFile [ ulByteCount++ ]) << 8);
2761
pusSuperArray[ i ] |= ( UINT16 )pbyImageFile [ ulByteCount++ ];
2762
}
2763
2764
mOCT6100_DRIVER_WRITE_BURST_API( BurstParams, ulResult )
2765
if ( ulResult != cOCT6100_ERR_OK )
2766
return ulResult;
2767
2768
BurstParams.ulWriteAddress += 2 * BurstParams.ulWriteLength;
2769
ulNumWrites -= BurstParams.ulWriteLength;
2770
}
2771
2772
/* Perform a serie of reads to make sure the image was correclty written into memory. */
2773
ulAddressOfst = ( pSharedInfo->ChipConfig.ulImageSize / 2 ) & 0xFFFFFFFE;
2774
while ( ulAddressOfst != 0 )
2775
{
2776
ReadParams.ulReadAddress = cOCT6100_IMAGE_FILE_BASE + ulAddressOfst;
2777
2778
mOCT6100_DRIVER_READ_API( ReadParams, ulResult )
2779
if ( ulResult != cOCT6100_ERR_OK )
2780
return ulResult;
2781
2782
if ( (usReadData >> 8) != pbyImageFile[ ulAddressOfst ] )
2783
return cOCT6100_ERR_OPEN_IMAGE_WRITE_FAILED;
2784
2785
ulAddressOfst = (ulAddressOfst / 2) & 0xFFFFFFFE;
2786
}
2787
2788
return cOCT6100_ERR_OK;
2789
}
2790
#endif
2791
2792
2793
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
2794
2795
Function: Oct6100ApiCpuRegisterBist
2796
2797
Description: Tests the operation of the CPU registers.
2798
2799
-------------------------------------------------------------------------------
2800
| Argument | Description
2801
-------------------------------------------------------------------------------
2802
f_pApiInstance Pointer to API instance. This memory is used to keep the
2803
present state of the chip and all its resources.
2804
2805
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
2806
#if !SKIP_Oct6100ApiCpuRegisterBist
2807
UINT32 Oct6100ApiCpuRegisterBist(
2808
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
2809
{
2810
tPOCT6100_SHARED_INFO pSharedInfo;
2811
tOCT6100_WRITE_PARAMS WriteParams;
2812
tOCT6100_READ_PARAMS ReadParams;
2813
UINT32 ulResult;
2814
UINT16 i;
2815
UINT16 usReadData;
2816
2817
/* Get local pointer to shared portion of instance. */
2818
pSharedInfo = f_pApiInstance->pSharedInfo;
2819
2820
/* Set the process context and user chip ID parameters once and for all. */
2821
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
2822
2823
WriteParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
2824
2825
ReadParams.pProcessContext = f_pApiInstance->pProcessContext;
2826
2827
ReadParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
2828
2829
/* Assign read data pointer that will be used throughout the function. */
2830
ReadParams.pusReadData = &usReadData;
2831
2832
/* Start with a walking bit test. */
2833
for ( i = 0; i < 16; i ++ )
2834
{
2835
/* Write at address 0x150.*/
2836
WriteParams.ulWriteAddress = 0x150;
2837
WriteParams.usWriteData = (UINT16)( 0x1 << i );
2838
2839
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2840
if ( ulResult != cOCT6100_ERR_OK )
2841
return ulResult;
2842
2843
/* Write at address 0x180.*/
2844
WriteParams.ulWriteAddress = 0x180;
2845
WriteParams.usWriteData = (UINT16)( 0x1 << ( 15 - i ) );
2846
2847
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2848
if ( ulResult != cOCT6100_ERR_OK )
2849
return ulResult;
2850
2851
/* Now read back the two registers to make sure the acceses were successfull. */
2852
ReadParams.ulReadAddress = 0x150;
2853
2854
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
2855
if ( ulResult != cOCT6100_ERR_OK )
2856
return ulResult;
2857
2858
if ( usReadData != ( 0x1 << i ) )
2859
return cOCT6100_ERR_OPEN_CPU_REG_BIST_ERROR;
2860
2861
ReadParams.ulReadAddress = 0x180;
2862
2863
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
2864
if ( ulResult != cOCT6100_ERR_OK )
2865
return ulResult;
2866
2867
if ( usReadData != ( 0x1 << ( 15 - i ) ) )
2868
return cOCT6100_ERR_OPEN_CPU_REG_BIST_ERROR;
2869
}
2870
2871
/* Write at address 0x150. */
2872
WriteParams.ulWriteAddress = 0x150;
2873
WriteParams.usWriteData = 0xCAFE;
2874
2875
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2876
if ( ulResult != cOCT6100_ERR_OK )
2877
return ulResult;
2878
2879
/* Write at address 0x180. */
2880
WriteParams.ulWriteAddress = 0x180;
2881
WriteParams.usWriteData = 0xDECA;
2882
2883
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2884
if ( ulResult != cOCT6100_ERR_OK )
2885
return ulResult;
2886
2887
/* Now read back the two registers to make sure the acceses were successfull. */
2888
ReadParams.ulReadAddress = 0x150;
2889
2890
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
2891
if ( ulResult != cOCT6100_ERR_OK )
2892
return ulResult;
2893
2894
if ( usReadData != 0xCAFE )
2895
return cOCT6100_ERR_OPEN_CPU_REG_BIST_ERROR;
2896
2897
ReadParams.ulReadAddress = 0x180;
2898
2899
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
2900
if ( ulResult != cOCT6100_ERR_OK )
2901
return ulResult;
2902
2903
if ( usReadData != 0xDECA )
2904
return cOCT6100_ERR_OPEN_CPU_REG_BIST_ERROR;
2905
2906
return cOCT6100_ERR_OK;
2907
}
2908
#endif
2909
2910
2911
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
2912
2913
Function: Oct6100ApiBootSdram
2914
2915
Description: Configure and test the SDRAM.
2916
2917
-------------------------------------------------------------------------------
2918
| Argument | Description
2919
-------------------------------------------------------------------------------
2920
f_pApiInstance Pointer to API instance. This memory is used to keep the
2921
present state of the chip and all its resources.
2922
2923
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
2924
#if !SKIP_Oct6100ApiBootSdram
2925
UINT32 Oct6100ApiBootSdram(
2926
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
2927
{
2928
tPOCT6100_SHARED_INFO pSharedInfo;
2929
tPOCT6100_API_CHIP_CONFIG pChipConfig;
2930
tOCT6100_WRITE_PARAMS WriteParams;
2931
tOCT6100_READ_PARAMS ReadParams;
2932
UINT32 ulResult;
2933
UINT16 usReadData;
2934
UINT16 usWriteData23E;
2935
UINT16 usWriteData230;
2936
UINT32 i;
2937
2938
/* Get local pointer to shared portion of instance. */
2939
pSharedInfo = f_pApiInstance->pSharedInfo;
2940
2941
/* Get local pointer to the chip configuration structure.*/
2942
pChipConfig = &f_pApiInstance->pSharedInfo->ChipConfig;
2943
2944
/* Set the process context and user chip ID parameters once and for all. */
2945
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
2946
2947
WriteParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
2948
2949
ReadParams.pProcessContext = f_pApiInstance->pProcessContext;
2950
2951
ReadParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
2952
ReadParams.pusReadData = &usReadData;
2953
2954
usWriteData23E = 0x0000;
2955
usWriteData230 = 0x0000;
2956
2957
if ( (pSharedInfo->ChipConfig.byMemoryType == cOCT6100_MEM_TYPE_SDR) || (pSharedInfo->ChipConfig.byMemoryType == cOCT6100_MEM_TYPE_SDR_PLL_BYPASS) )
2958
{
2959
/* SDRAM: */
2960
switch( pChipConfig->ulMemoryChipSize )
2961
{
2962
case cOCT6100_MEMORY_CHIP_SIZE_8MB:
2963
usWriteData230 |= ( cOCT6100_16MB_MEMORY_BANKS << 2 );
2964
break;
2965
case cOCT6100_MEMORY_CHIP_SIZE_16MB:
2966
usWriteData230 |= ( cOCT6100_32MB_MEMORY_BANKS << 2 );
2967
break;
2968
case cOCT6100_MEMORY_CHIP_SIZE_32MB:
2969
usWriteData230 |= ( cOCT6100_64MB_MEMORY_BANKS << 2 );
2970
break;
2971
case cOCT6100_MEMORY_CHIP_SIZE_64MB:
2972
usWriteData230 |= ( cOCT6100_128MB_MEMORY_BANKS << 2 );
2973
break;
2974
default:
2975
return cOCT6100_ERR_FATAL_16;
2976
}
2977
2978
usWriteData230 |= 0x0002;
2979
2980
WriteParams.ulWriteAddress = 0x230;
2981
WriteParams.usWriteData = usWriteData230;
2982
2983
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2984
if ( ulResult != cOCT6100_ERR_OK )
2985
return ulResult;
2986
2987
/* Precharge all banks. */
2988
usWriteData230 &= 0x000C;
2989
usWriteData230 |= 0x0010;
2990
2991
WriteParams.ulWriteAddress = 0x230;
2992
WriteParams.usWriteData = usWriteData230;
2993
2994
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
2995
if ( ulResult != cOCT6100_ERR_OK )
2996
return ulResult;
2997
2998
usWriteData230 |= 0x0002;
2999
3000
WriteParams.usWriteData = usWriteData230;
3001
3002
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3003
if ( ulResult != cOCT6100_ERR_OK )
3004
return ulResult;
3005
3006
WriteParams.ulWriteAddress = 0x23E;
3007
WriteParams.usWriteData = usWriteData23E;
3008
for ( i = 0; i < 5; i++ )
3009
{
3010
/* Wait cycle. */
3011
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3012
if ( ulResult != cOCT6100_ERR_OK )
3013
return ulResult;
3014
}
3015
3016
/* Program the mode register. */
3017
usWriteData23E = 0x0030;
3018
WriteParams.usWriteData = usWriteData23E;
3019
3020
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3021
if ( ulResult != cOCT6100_ERR_OK )
3022
return ulResult;
3023
3024
usWriteData230 &= 0x000C;
3025
usWriteData230 |= 0x0000;
3026
3027
WriteParams.ulWriteAddress = 0x230;
3028
WriteParams.usWriteData = usWriteData230;
3029
3030
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3031
if ( ulResult != cOCT6100_ERR_OK )
3032
return ulResult;
3033
3034
usWriteData230 |= 0x0002;
3035
3036
WriteParams.usWriteData = usWriteData230;
3037
3038
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3039
if ( ulResult != cOCT6100_ERR_OK )
3040
return ulResult;
3041
3042
WriteParams.ulWriteAddress = 0x23E;
3043
WriteParams.usWriteData = usWriteData23E;
3044
for ( i = 0; i < 5; i++ )
3045
{
3046
/* Wait cycle. */
3047
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3048
if ( ulResult != cOCT6100_ERR_OK )
3049
return ulResult;
3050
}
3051
3052
/* Do CBR refresh (twice) */
3053
usWriteData230 &= 0x000C;
3054
usWriteData230 |= 0x0040;
3055
3056
WriteParams.ulWriteAddress = 0x230;
3057
WriteParams.usWriteData = usWriteData230;
3058
3059
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3060
if ( ulResult != cOCT6100_ERR_OK )
3061
return ulResult;
3062
3063
usWriteData230 |= 0x0002;
3064
3065
WriteParams.usWriteData = usWriteData230;
3066
3067
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3068
if ( ulResult != cOCT6100_ERR_OK )
3069
return ulResult;
3070
3071
WriteParams.ulWriteAddress = 0x23E;
3072
WriteParams.usWriteData = usWriteData23E;
3073
for ( i = 0; i < 5; i++ )
3074
{
3075
/* Wait cycle. */
3076
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3077
if ( ulResult != cOCT6100_ERR_OK )
3078
return ulResult;
3079
}
3080
3081
WriteParams.ulWriteAddress = 0x230;
3082
WriteParams.usWriteData = usWriteData230;
3083
3084
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3085
if ( ulResult != cOCT6100_ERR_OK )
3086
return ulResult;
3087
3088
WriteParams.ulWriteAddress = 0x23E;
3089
WriteParams.usWriteData = usWriteData23E;
3090
for ( i = 0; i < 5; i++ )
3091
{
3092
/* Wait cycle. */
3093
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3094
if ( ulResult != cOCT6100_ERR_OK )
3095
return ulResult;
3096
}
3097
}
3098
else
3099
{
3100
/* DDR: */
3101
switch( pChipConfig->ulMemoryChipSize )
3102
{
3103
case cOCT6100_MEMORY_CHIP_SIZE_16MB:
3104
usWriteData230 |= ( cOCT6100_16MB_MEMORY_BANKS << 2 );
3105
break;
3106
case cOCT6100_MEMORY_CHIP_SIZE_32MB:
3107
usWriteData230 |= ( cOCT6100_32MB_MEMORY_BANKS << 2 );
3108
break;
3109
case cOCT6100_MEMORY_CHIP_SIZE_64MB:
3110
usWriteData230 |= ( cOCT6100_64MB_MEMORY_BANKS << 2 );
3111
break;
3112
case cOCT6100_MEMORY_CHIP_SIZE_128MB:
3113
usWriteData230 |= ( cOCT6100_128MB_MEMORY_BANKS << 2 );
3114
break;
3115
default:
3116
return cOCT6100_ERR_FATAL_17;
3117
}
3118
WriteParams.ulWriteAddress = 0x230;
3119
WriteParams.usWriteData = usWriteData230;
3120
3121
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3122
if ( ulResult != cOCT6100_ERR_OK )
3123
return ulResult;
3124
3125
/* Precharge all banks. */
3126
usWriteData230 &= 0x000C;
3127
usWriteData230 |= 0x0010;
3128
3129
WriteParams.ulWriteAddress = 0x230;
3130
WriteParams.usWriteData = usWriteData230;
3131
3132
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3133
if ( ulResult != cOCT6100_ERR_OK )
3134
return ulResult;
3135
3136
usWriteData230 |= 0x0002;
3137
3138
WriteParams.usWriteData = usWriteData230;
3139
3140
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3141
if ( ulResult != cOCT6100_ERR_OK )
3142
return ulResult;
3143
3144
WriteParams.ulWriteAddress = 0x23E;
3145
WriteParams.usWriteData = usWriteData23E;
3146
for ( i = 0; i < 5; i++ )
3147
{
3148
/* Wait cycle. */
3149
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3150
if ( ulResult != cOCT6100_ERR_OK )
3151
return ulResult;
3152
}
3153
3154
/* Program DDR mode register. */
3155
usWriteData23E = 0x4000;
3156
3157
WriteParams.ulWriteAddress = 0x23E;
3158
WriteParams.usWriteData = usWriteData23E;
3159
3160
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3161
if ( ulResult != cOCT6100_ERR_OK )
3162
return ulResult;
3163
3164
usWriteData230 &= 0x000C;
3165
usWriteData230 |= 0x0000;
3166
3167
WriteParams.ulWriteAddress = 0x230;
3168
WriteParams.usWriteData = usWriteData230;
3169
3170
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3171
if ( ulResult != cOCT6100_ERR_OK )
3172
return ulResult;
3173
3174
usWriteData230 |= 0x0002;
3175
3176
WriteParams.usWriteData = usWriteData230;
3177
3178
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3179
if ( ulResult != cOCT6100_ERR_OK )
3180
return ulResult;
3181
3182
WriteParams.ulWriteAddress = 0x23E;
3183
WriteParams.usWriteData = usWriteData23E;
3184
for ( i = 0; i < 5; i++ )
3185
{
3186
/* Wait cycle. */
3187
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3188
if ( ulResult != cOCT6100_ERR_OK )
3189
return ulResult;
3190
}
3191
3192
/* Program SDR mode register. */
3193
usWriteData23E = 0x0161;
3194
3195
WriteParams.ulWriteAddress = 0x23E;
3196
WriteParams.usWriteData = usWriteData23E;
3197
3198
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3199
if ( ulResult != cOCT6100_ERR_OK )
3200
return ulResult;
3201
3202
usWriteData230 &= 0x000C;
3203
usWriteData230 |= 0x0000;
3204
3205
WriteParams.ulWriteAddress = 0x230;
3206
WriteParams.usWriteData = usWriteData230;
3207
3208
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3209
if ( ulResult != cOCT6100_ERR_OK )
3210
return ulResult;
3211
3212
usWriteData230 |= 0x0002;
3213
3214
WriteParams.usWriteData = usWriteData230;
3215
3216
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3217
if ( ulResult != cOCT6100_ERR_OK )
3218
return ulResult;
3219
3220
WriteParams.ulWriteAddress = 0x23E;
3221
WriteParams.usWriteData = usWriteData23E;
3222
for ( i = 0; i < 5; i++ )
3223
{
3224
/* Wait cycle. */
3225
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3226
if ( ulResult != cOCT6100_ERR_OK )
3227
return ulResult;
3228
}
3229
3230
/* Precharge all banks. */
3231
usWriteData23E = 0xFFFF;
3232
3233
WriteParams.ulWriteAddress = 0x23E;
3234
WriteParams.usWriteData = usWriteData23E;
3235
3236
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3237
if ( ulResult != cOCT6100_ERR_OK )
3238
return ulResult;
3239
3240
usWriteData230 &= 0x000C;
3241
usWriteData230 |= 0x0010;
3242
3243
WriteParams.ulWriteAddress = 0x230;
3244
WriteParams.usWriteData = usWriteData230;
3245
3246
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3247
if ( ulResult != cOCT6100_ERR_OK )
3248
return ulResult;
3249
3250
usWriteData230 |= 0x0002;
3251
3252
WriteParams.usWriteData = usWriteData230;
3253
3254
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3255
if ( ulResult != cOCT6100_ERR_OK )
3256
return ulResult;
3257
3258
WriteParams.ulWriteAddress = 0x23E;
3259
WriteParams.usWriteData = usWriteData23E;
3260
for ( i = 0; i < 5; i++ )
3261
{
3262
/* Wait cycle. */
3263
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3264
if ( ulResult != cOCT6100_ERR_OK )
3265
return ulResult;
3266
}
3267
3268
/* Do CBR refresh (twice) */
3269
usWriteData230 &= 0x000C;
3270
usWriteData230 |= 0x0040;
3271
3272
WriteParams.ulWriteAddress = 0x230;
3273
WriteParams.usWriteData = usWriteData230;
3274
3275
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3276
if ( ulResult != cOCT6100_ERR_OK )
3277
return ulResult;
3278
3279
usWriteData230 |= 0x0002;
3280
3281
WriteParams.usWriteData = usWriteData230;
3282
3283
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3284
if ( ulResult != cOCT6100_ERR_OK )
3285
return ulResult;
3286
3287
WriteParams.ulWriteAddress = 0x23E;
3288
WriteParams.usWriteData = usWriteData23E;
3289
for ( i = 0; i < 5; i++ )
3290
{
3291
/* Wait cycle. */
3292
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3293
if ( ulResult != cOCT6100_ERR_OK )
3294
return ulResult;
3295
}
3296
3297
WriteParams.ulWriteAddress = 0x230;
3298
WriteParams.usWriteData = usWriteData230;
3299
3300
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3301
if ( ulResult != cOCT6100_ERR_OK )
3302
return ulResult;
3303
3304
WriteParams.ulWriteAddress = 0x23E;
3305
WriteParams.usWriteData = usWriteData23E;
3306
for ( i = 0; i < 5; i++ )
3307
{
3308
/* Wait cycle.*/
3309
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3310
if ( ulResult != cOCT6100_ERR_OK )
3311
return ulResult;
3312
}
3313
3314
/* Program SDR mode register. */
3315
usWriteData23E = 0x0061;
3316
3317
WriteParams.ulWriteAddress = 0x23E;
3318
WriteParams.usWriteData = usWriteData23E;
3319
3320
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3321
if ( ulResult != cOCT6100_ERR_OK )
3322
return ulResult;
3323
3324
usWriteData230 &= 0x000C;
3325
usWriteData230 |= 0x0000;
3326
3327
WriteParams.ulWriteAddress = 0x230;
3328
WriteParams.usWriteData = usWriteData230;
3329
3330
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3331
if ( ulResult != cOCT6100_ERR_OK )
3332
return ulResult;
3333
3334
usWriteData230 |= 0x0002;
3335
3336
WriteParams.usWriteData = usWriteData230;
3337
3338
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3339
if ( ulResult != cOCT6100_ERR_OK )
3340
return ulResult;
3341
3342
WriteParams.ulWriteAddress = 0x23E;
3343
WriteParams.usWriteData = usWriteData23E;
3344
for ( i = 0; i < 5; i++ )
3345
{
3346
/* Wait cycle. */
3347
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3348
if ( ulResult != cOCT6100_ERR_OK )
3349
return ulResult;
3350
}
3351
}
3352
3353
/* Set the refresh frequency. */
3354
WriteParams.ulWriteAddress = 0x242;
3355
WriteParams.usWriteData = 0x0400;
3356
3357
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3358
if ( ulResult != cOCT6100_ERR_OK )
3359
return ulResult;
3360
3361
WriteParams.ulWriteAddress = 0x244;
3362
WriteParams.usWriteData = 0x0200;
3363
3364
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3365
if ( ulResult != cOCT6100_ERR_OK )
3366
return ulResult;
3367
3368
WriteParams.ulWriteAddress = 0x248;
3369
WriteParams.usWriteData = 0x800;
3370
3371
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3372
if ( ulResult != cOCT6100_ERR_OK )
3373
return ulResult;
3374
3375
WriteParams.ulWriteAddress = 0x246;
3376
WriteParams.usWriteData = 0x0012;
3377
3378
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3379
if ( ulResult != cOCT6100_ERR_OK )
3380
return ulResult;
3381
3382
/* Enable the SDRAM and refreshes. */
3383
usWriteData230 &= 0x000C;
3384
usWriteData230 |= 0x0001;
3385
3386
WriteParams.ulWriteAddress = 0x230;
3387
WriteParams.usWriteData = usWriteData230;
3388
3389
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3390
if ( ulResult != cOCT6100_ERR_OK )
3391
return ulResult;
3392
3393
WriteParams.ulWriteAddress = 0x246;
3394
WriteParams.usWriteData = 0x0013;
3395
3396
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3397
if ( ulResult != cOCT6100_ERR_OK )
3398
return ulResult;
3399
3400
return cOCT6100_ERR_OK;
3401
}
3402
#endif
3403
3404
3405
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
3406
3407
Function: Oct6100ApiEnableClocks
3408
3409
Description: This function will disable clock masking for all the modules
3410
of the chip.
3411
3412
-------------------------------------------------------------------------------
3413
| Argument | Description
3414
-------------------------------------------------------------------------------
3415
f_pApiInstance Pointer to API instance. This memory is used to keep the
3416
present state of the chip and all its resources.
3417
3418
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
3419
#if !SKIP_Oct6100ApiEnableClocks
3420
UINT32 Oct6100ApiEnableClocks(
3421
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
3422
{
3423
tOCT6100_WRITE_PARAMS WriteParams;
3424
UINT32 ulResult;
3425
3426
/* Initialize the process context and user chip ID once and for all. */
3427
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
3428
3429
WriteParams.ulUserChipId = f_pApiInstance->pSharedInfo->ChipConfig.ulUserChipId;
3430
3431
/* Enable tdmie / adpcm mclk clocks. */
3432
WriteParams.ulWriteAddress = 0x186;
3433
WriteParams.usWriteData = 0x015F;
3434
3435
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3436
if ( ulResult != cOCT6100_ERR_OK )
3437
return ulResult;
3438
3439
/* Configure the DQS register for the DDR memory */
3440
WriteParams.ulWriteAddress = 0x180;
3441
WriteParams.usWriteData = 0xFF00;
3442
3443
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3444
if ( ulResult != cOCT6100_ERR_OK )
3445
return ulResult;
3446
3447
/* Enable pgsp chariot clocks */
3448
WriteParams.ulWriteAddress = 0x182;
3449
WriteParams.usWriteData = 0x0000;
3450
3451
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3452
if ( ulResult != cOCT6100_ERR_OK )
3453
return ulResult;
3454
3455
/* Enable af/mt chariot clocks */
3456
WriteParams.ulWriteAddress = 0x184;
3457
WriteParams.usWriteData = 0x0000;
3458
3459
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3460
if ( ulResult != cOCT6100_ERR_OK )
3461
return ulResult;
3462
3463
return cOCT6100_ERR_OK;
3464
}
3465
#endif
3466
3467
3468
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
3469
3470
Function: Oct6100ApiProgramNLP
3471
3472
Description: This function will write image values to configure the NLP.
3473
3474
-------------------------------------------------------------------------------
3475
| Argument | Description
3476
-------------------------------------------------------------------------------
3477
f_pApiInstance Pointer to API instance. This memory is used to keep the
3478
present state of the chip and all its resources.
3479
3480
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
3481
#if !SKIP_Oct6100ApiProgramNLP
3482
UINT32 Oct6100ApiProgramNLP(
3483
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
3484
{
3485
tOCT6100_WRITE_PARAMS WriteParams;
3486
tOCT6100_READ_PARAMS ReadParams;
3487
tPOCT6100_SHARED_INFO pSharedInfo;
3488
tPOCT6100_API_CHIP_CONFIG pChipConfig;
3489
UINT32 ulResult;
3490
UINT16 usReadData;
3491
UINT16 usReadHighData;
3492
BOOL fBitEqual;
3493
UINT32 ulEgoEntry[4];
3494
UINT32 ulTempAddress;
3495
UINT32 ulAfCpuUp = FALSE;
3496
UINT32 i;
3497
UINT32 ulLoopCounter = 0;
3498
3499
/* Get local pointer to shared portion of instance. */
3500
pSharedInfo = f_pApiInstance->pSharedInfo;
3501
3502
/* Get local pointer to the chip configuration structure.*/
3503
pChipConfig = &f_pApiInstance->pSharedInfo->ChipConfig;
3504
3505
/* Initialize the process context and user chip ID once and for all. */
3506
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
3507
3508
WriteParams.ulUserChipId = f_pApiInstance->pSharedInfo->ChipConfig.ulUserChipId;
3509
3510
/* Initialize the process context and user chip ID once and for all. */
3511
ReadParams.pProcessContext = f_pApiInstance->pProcessContext;
3512
3513
ReadParams.ulUserChipId = f_pApiInstance->pSharedInfo->ChipConfig.ulUserChipId;
3514
ReadParams.pusReadData = &usReadData;
3515
3516
if ( pSharedInfo->ChipConfig.fEnableProductionBist == TRUE )
3517
{
3518
UINT32 ulReadData;
3519
UINT32 ulBitPattern;
3520
UINT32 j, k;
3521
3522
/* Since the pouch section (256 bytes) will not be tested by the firmware, */
3523
/* the API has to make sure this section is working correctly. */
3524
for ( k = 0; k < 2; k ++ )
3525
{
3526
if ( k == 0 )
3527
ulBitPattern = 0x1;
3528
else
3529
ulBitPattern = 0xFFFFFFFE;
3530
3531
for ( j = 0; j < 32; j ++ )
3532
{
3533
/* Write the DWORDs. */
3534
for ( i = 0; i < 64; i ++ )
3535
{
3536
ulResult = Oct6100ApiWriteDword( f_pApiInstance, cOCT6100_POUCH_BASE + i * 4, ulBitPattern << j );
3537
if ( ulResult != cOCT6100_ERR_OK )
3538
return ulResult;
3539
}
3540
3541
/* Read the DWORDs. */
3542
for ( i = 0; i < 64; i ++ )
3543
{
3544
ulResult = Oct6100ApiReadDword( f_pApiInstance, cOCT6100_POUCH_BASE + i * 4, &ulReadData );
3545
if ( ulResult != cOCT6100_ERR_OK )
3546
return ulResult;
3547
3548
/* Check if the value matches. */
3549
if ( ( ulBitPattern << j ) != ulReadData )
3550
return cOCT6100_ERR_OPEN_PRODUCTION_BIST_POUCH_ERROR;
3551
}
3552
}
3553
}
3554
}
3555
3556
/* Write the image info in the chip. */
3557
WriteParams.ulWriteAddress = cOCT6100_PART1_END_STATICS_BASE;
3558
WriteParams.usWriteData = (UINT16)( ( pSharedInfo->ImageRegion[ 0 ].ulPart1BaseAddress >> 16 ) & 0xFFFF );
3559
3560
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3561
if ( ulResult != cOCT6100_ERR_OK )
3562
return ulResult;
3563
3564
WriteParams.ulWriteAddress += 2;
3565
WriteParams.usWriteData = (UINT16)( pSharedInfo->ImageRegion[ 0 ].ulPart1BaseAddress & 0xFFFF );
3566
3567
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3568
if ( ulResult != cOCT6100_ERR_OK )
3569
return ulResult;
3570
3571
for( i = 0; i < 8; i++ )
3572
{
3573
if ( pSharedInfo->ImageRegion[ i + 2 ].ulPart1Size != 0 )
3574
{
3575
WriteParams.ulWriteAddress = cOCT6100_PART1_END_STATICS_BASE + 0x4 + ( i * 0xC );
3576
WriteParams.usWriteData = (UINT16)(( pSharedInfo->ImageRegion[ i + 2 ].ulPart1BaseAddress >> 16 ) & 0xFFFF );
3577
3578
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3579
if ( ulResult != cOCT6100_ERR_OK )
3580
return ulResult;
3581
3582
WriteParams.ulWriteAddress += 2;
3583
WriteParams.usWriteData = (UINT16)( pSharedInfo->ImageRegion[ i + 2 ].ulPart1BaseAddress & 0xFFFF );
3584
3585
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3586
if ( ulResult != cOCT6100_ERR_OK )
3587
return ulResult;
3588
}
3589
3590
if ( pSharedInfo->ImageRegion[ i + 2 ].ulPart2Size != 0 )
3591
{
3592
WriteParams.ulWriteAddress = cOCT6100_PART1_END_STATICS_BASE + 0x4 + ( i * 0xC ) + 4;
3593
WriteParams.usWriteData = (UINT16)(( pSharedInfo->ImageRegion[ i + 2 ].ulPart2BaseAddress >> 16 ) & 0xFFFF );
3594
3595
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3596
if ( ulResult != cOCT6100_ERR_OK )
3597
return ulResult;
3598
3599
WriteParams.ulWriteAddress += 2;
3600
WriteParams.usWriteData = (UINT16)( pSharedInfo->ImageRegion[ i + 2 ].ulPart2BaseAddress & 0xFFFF );
3601
3602
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3603
if ( ulResult != cOCT6100_ERR_OK )
3604
return ulResult;
3605
}
3606
3607
WriteParams.ulWriteAddress = cOCT6100_PART1_END_STATICS_BASE + 0x4 + ( i * 0xC ) + 8;
3608
WriteParams.usWriteData = 0x0000;
3609
WriteParams.usWriteData |= ( pSharedInfo->ImageRegion[ i + 2 ].ulPart1Size << 8 );
3610
WriteParams.usWriteData |= pSharedInfo->ImageRegion[ i + 2 ].ulPart2Size;
3611
3612
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3613
if ( ulResult != cOCT6100_ERR_OK )
3614
return ulResult;
3615
3616
WriteParams.ulWriteAddress += 2;
3617
WriteParams.usWriteData = 0x0000;
3618
WriteParams.usWriteData |= ( pSharedInfo->ImageRegion[ i + 2 ].ulClockInfo << 8 );
3619
WriteParams.usWriteData |= pSharedInfo->ImageRegion[ i + 2 ].ulReserved;
3620
3621
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3622
if ( ulResult != cOCT6100_ERR_OK )
3623
return ulResult;
3624
}
3625
3626
/* Put NLP in config mode. */
3627
WriteParams.ulWriteAddress = 0x2C2;
3628
WriteParams.usWriteData = 0x160E;
3629
3630
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3631
if ( ulResult != cOCT6100_ERR_OK )
3632
return ulResult;
3633
3634
WriteParams.ulWriteAddress = 0x692;
3635
WriteParams.usWriteData = 0x010A;
3636
3637
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3638
if ( ulResult != cOCT6100_ERR_OK )
3639
return ulResult;
3640
3641
/* Upload the up to 8 NLP pages + 1 AF page (for timing reasons). */
3642
for ( i = 0; i < pSharedInfo->ImageRegion[ 1 ].ulPart1Size; i++ )
3643
{
3644
ulResult = Oct6100ApiCreateEgoEntry( cOCT6100_EXTERNAL_MEM_BASE_ADDRESS + pSharedInfo->ImageRegion[ 1 ].ulPart1BaseAddress + 1028 * ( i * 2 ), 0x1280, 1024, &(ulEgoEntry[0]));
3645
if ( ulResult != cOCT6100_ERR_OK )
3646
return ulResult;
3647
3648
ulResult = Oct6100ApiCreateEgoEntry( cOCT6100_EXTERNAL_MEM_BASE_ADDRESS + pSharedInfo->ImageRegion[ 1 ].ulPart1BaseAddress + 1028 * (( i * 2 ) + 1 ), 0x1680, 1024, &(ulEgoEntry[2]));
3649
if ( ulResult != cOCT6100_ERR_OK )
3650
return ulResult;
3651
3652
ulResult = Oct6100ApiRunEgo( f_pApiInstance, FALSE, 2, ulEgoEntry );
3653
if ( ulResult != cOCT6100_ERR_OK )
3654
return ulResult;
3655
3656
/* Shift mt chariot memories. This process will complete by the time */
3657
/* the next LSU transfer is done. */
3658
WriteParams.ulWriteAddress = 0x692;
3659
WriteParams.usWriteData = 0x010B;
3660
3661
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3662
if ( ulResult != cOCT6100_ERR_OK )
3663
return ulResult;
3664
3665
ulResult = Oct6100ApiWaitForPcRegisterBit( f_pApiInstance, 0x692, 0, 0, 100000, &fBitEqual );
3666
if ( ulResult != cOCT6100_ERR_OK )
3667
return ulResult;
3668
if ( TRUE != fBitEqual )
3669
return cOCT6100_ERR_FATAL_1A;
3670
}
3671
3672
/* 1 AF page (for timing reasons). */
3673
ulResult = Oct6100ApiCreateEgoEntry( cOCT6100_EXTERNAL_MEM_BASE_ADDRESS + pSharedInfo->ImageRegion[ 2 ].ulPart1BaseAddress + (516 * 0), 0x1280, 512, &(ulEgoEntry[0]));
3674
if ( ulResult != cOCT6100_ERR_OK )
3675
return ulResult;
3676
3677
ulResult = Oct6100ApiCreateEgoEntry( cOCT6100_EXTERNAL_MEM_BASE_ADDRESS + pSharedInfo->ImageRegion[ 2 ].ulPart1BaseAddress + (516 * 1), 0x1480, 512, &(ulEgoEntry[2]));
3678
if ( ulResult != cOCT6100_ERR_OK )
3679
return ulResult;
3680
3681
ulResult = Oct6100ApiRunEgo( f_pApiInstance, FALSE, 2, ulEgoEntry );
3682
if ( ulResult != cOCT6100_ERR_OK )
3683
return ulResult;
3684
3685
ulResult = Oct6100ApiCreateEgoEntry( cOCT6100_EXTERNAL_MEM_BASE_ADDRESS + pSharedInfo->ImageRegion[ 2 ].ulPart1BaseAddress + (516 * 2), 0x1680, 512, &(ulEgoEntry[0]));
3686
if ( ulResult != cOCT6100_ERR_OK )
3687
return ulResult;
3688
3689
ulResult = Oct6100ApiCreateEgoEntry( cOCT6100_EXTERNAL_MEM_BASE_ADDRESS + pSharedInfo->ImageRegion[ 2 ].ulPart1BaseAddress + (516 * 3), 0x1880, 512, &(ulEgoEntry[2]));
3690
if ( ulResult != cOCT6100_ERR_OK )
3691
return ulResult;
3692
3693
ulResult = Oct6100ApiRunEgo( f_pApiInstance, FALSE, 2, ulEgoEntry );
3694
if ( ulResult != cOCT6100_ERR_OK )
3695
return ulResult;
3696
3697
/* Write constant memory init context position in channel "672" for pgsp. */
3698
WriteParams.ulWriteAddress = 0x71A;
3699
WriteParams.usWriteData = 0x8000;
3700
3701
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3702
if ( ulResult != cOCT6100_ERR_OK )
3703
return ulResult;
3704
3705
/* Set fixed PGSP event_in base address to 800 on a 2k boundary */
3706
WriteParams.ulWriteAddress = 0x716;
3707
WriteParams.usWriteData = 0x800 >> 11;
3708
3709
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3710
if ( ulResult != cOCT6100_ERR_OK )
3711
return ulResult;
3712
3713
/* Set fixed PGSP event_out to 0x2C0000h on a 16k boundary */
3714
WriteParams.ulWriteAddress = 0x71C;
3715
WriteParams.usWriteData = 0x2C0000 >> 14;
3716
3717
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3718
if ( ulResult != cOCT6100_ERR_OK )
3719
return ulResult;
3720
3721
/* Give chariot control of the chip. */
3722
WriteParams.ulWriteAddress = 0x712;
3723
WriteParams.usWriteData = 0x0000;
3724
3725
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3726
if ( ulResult != cOCT6100_ERR_OK )
3727
return ulResult;
3728
3729
WriteParams.ulWriteAddress = cOCT6100_EXTERNAL_MEM_BASE_ADDRESS + 0x2C0000 + 0xC;
3730
ulTempAddress = 0x300000 + 0x0800;
3731
WriteParams.usWriteData = (UINT16)( ( ulTempAddress >> 16 ) & 0x07FF );
3732
3733
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3734
if ( ulResult != cOCT6100_ERR_OK )
3735
return ulResult;
3736
3737
WriteParams.ulWriteAddress = cOCT6100_EXTERNAL_MEM_BASE_ADDRESS + 0x2C0000 + 0xE;
3738
WriteParams.usWriteData = (UINT16)( ( ulTempAddress >> 0 ) & 0xFF00 );
3739
3740
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3741
if ( ulResult != cOCT6100_ERR_OK )
3742
return ulResult;
3743
3744
/* Write the init PGSP event in place. */
3745
WriteParams.ulWriteAddress = cOCT6100_EXTERNAL_MEM_BASE_ADDRESS + 0x800;
3746
WriteParams.usWriteData = 0x0200;
3747
3748
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3749
if ( ulResult != cOCT6100_ERR_OK )
3750
return ulResult;
3751
3752
WriteParams.ulWriteAddress = cOCT6100_EXTERNAL_MEM_BASE_ADDRESS + 0x802;
3753
WriteParams.usWriteData = 0x02A0;
3754
3755
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3756
if ( ulResult != cOCT6100_ERR_OK )
3757
return ulResult;
3758
3759
/* Also write the register 710, which tells PGSP how many tones are supported. */
3760
WriteParams.ulWriteAddress = 0x710;
3761
WriteParams.usWriteData = 0x0000;
3762
WriteParams.usWriteData |= pChipConfig->pbyImageFile[ 0x7FA ] << 8;
3763
WriteParams.usWriteData |= pChipConfig->pbyImageFile[ 0x7FB ] << 0;
3764
3765
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3766
if ( ulResult != cOCT6100_ERR_OK )
3767
return ulResult;
3768
3769
/* Start both processors in the NLP. */
3770
WriteParams.ulWriteAddress = 0x373FE;
3771
WriteParams.usWriteData = 0x00FF;
3772
3773
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3774
if ( ulResult != cOCT6100_ERR_OK )
3775
return ulResult;
3776
3777
WriteParams.ulWriteAddress = 0x37BFE;
3778
WriteParams.usWriteData = 0x00FE; /* Tell processor 1 to just go to sleep. */
3779
3780
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3781
if ( ulResult != cOCT6100_ERR_OK )
3782
return ulResult;
3783
3784
WriteParams.ulWriteAddress = 0x37FC6;
3785
WriteParams.usWriteData = 0x8004; /* First PC.*/
3786
3787
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3788
if ( ulResult != cOCT6100_ERR_OK )
3789
return ulResult;
3790
3791
WriteParams.ulWriteAddress = 0x37FD0;
3792
WriteParams.usWriteData = 0x0002; /* Take out of reset. */
3793
3794
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3795
if ( ulResult != cOCT6100_ERR_OK )
3796
return ulResult;
3797
3798
WriteParams.ulWriteAddress = 0x37FD2;
3799
WriteParams.usWriteData = 0x0002; /* Take out of reset. */
3800
3801
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3802
if ( ulResult != cOCT6100_ERR_OK )
3803
return ulResult;
3804
3805
/* Start processor in the AF. */
3806
for ( i = 0; i < 16; i ++ )
3807
{
3808
WriteParams.ulWriteAddress = cOCT6100_POUCH_BASE + ( i * 2 );
3809
if ( i == 9 )
3810
{
3811
if ( pSharedInfo->ChipConfig.fEnableProductionBist == TRUE )
3812
{
3813
WriteParams.usWriteData = cOCT6100_PRODUCTION_BOOT_TYPE;
3814
}
3815
else
3816
{
3817
WriteParams.usWriteData = cOCT6100_AF_BOOT_TYPE;
3818
}
3819
}
3820
else
3821
WriteParams.usWriteData = 0x0000;
3822
3823
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3824
if ( ulResult != cOCT6100_ERR_OK )
3825
return ulResult;
3826
}
3827
3828
/* Check if the production BIST mode was requested. */
3829
if ( pSharedInfo->ChipConfig.fEnableProductionBist == TRUE )
3830
{
3831
UINT32 ulTotalElements = 3;
3832
UINT32 ulCrcKey;
3833
UINT32 aulMessage[ 4 ];
3834
UINT32 ulWriteAddress = 0x20 + cOCT6100_EXTERNAL_MEM_BASE_ADDRESS;
3835
3836
/* Magic key. */
3837
aulMessage[ 0 ] = 0xCAFECAFE;
3838
/* Memory size. */
3839
aulMessage[ 1 ] = pSharedInfo->MiscVars.ulTotalMemSize;
3840
/* Loop count. */
3841
aulMessage[ 2 ] = pSharedInfo->ChipConfig.ulNumProductionBistLoops;
3842
/* CRC initialized. */
3843
aulMessage[ 3 ] = 0;
3844
3845
ulResult = Oct6100ApiProductionCrc( f_pApiInstance, aulMessage, ulTotalElements, &ulCrcKey );
3846
if ( ulResult != cOCT6100_ERR_OK )
3847
return ulResult;
3848
3849
aulMessage[ 3 ] = ulCrcKey;
3850
3851
/* Write the message to the external memory. */
3852
for ( i = 0; i < ulTotalElements + 1; i ++ )
3853
{
3854
ulResult = Oct6100ApiWriteDword( f_pApiInstance, ulWriteAddress + i * 4, aulMessage[ i ] );
3855
if ( ulResult != cOCT6100_ERR_OK )
3856
return ulResult;
3857
}
3858
}
3859
3860
WriteParams.ulWriteAddress = 0xFFFC6;
3861
WriteParams.usWriteData = 0x1284; /* First PC.*/
3862
3863
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3864
if ( ulResult != cOCT6100_ERR_OK )
3865
return ulResult;
3866
3867
WriteParams.ulWriteAddress = 0xFFFD0;
3868
WriteParams.usWriteData = 0x0002; /* Take out of reset. */
3869
3870
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3871
if ( ulResult != cOCT6100_ERR_OK )
3872
return ulResult;
3873
3874
while ( ulAfCpuUp == FALSE )
3875
{
3876
if ( ulAfCpuUp == FALSE )
3877
{
3878
ReadParams.ulReadAddress = cOCT6100_POUCH_BASE;
3879
ReadParams.pusReadData = &usReadHighData;
3880
3881
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
3882
if ( ulResult != cOCT6100_ERR_OK )
3883
return ulResult;
3884
3885
ReadParams.ulReadAddress += 2;
3886
ReadParams.pusReadData = &usReadData;
3887
3888
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
3889
if ( ulResult != cOCT6100_ERR_OK )
3890
return ulResult;
3891
3892
if ( pSharedInfo->ChipConfig.fEnableProductionBist == TRUE )
3893
{
3894
/* Should read 0x0007 when bisting. */
3895
if ( ( usReadHighData & 0xFFFF ) == cOCT6100_PRODUCTION_BOOT_TYPE )
3896
{
3897
/* Verify if the bist has started successfully. */
3898
if ( ( usReadData & 0xFFFF ) == 0x0002 )
3899
return cOCT6100_ERR_OPEN_PRODUCTION_BIST_CONF_FAILED;
3900
else if ( ( usReadData & 0xFFFF ) != 0xEEEE )
3901
return cOCT6100_ERR_OPEN_PRODUCTION_BOOT_FAILED;
3902
3903
ulAfCpuUp = TRUE;
3904
}
3905
}
3906
else /* if ( pSharedInfo->ChipConfig.fEnableProductionBist == FALSE ) */
3907
{
3908
if ( ( usReadHighData & 0xFFFF ) == cOCT6100_AF_BOOT_TYPE )
3909
{
3910
/* Verify if the bist succeeded. */
3911
if ( ( usReadData & 0xFFFF ) != 0x0000 )
3912
return cOCT6100_ERR_OPEN_FUNCTIONAL_BIST_FAILED; /* Bad chip. */
3913
3914
ulAfCpuUp = TRUE;
3915
}
3916
}
3917
}
3918
3919
ulLoopCounter++;
3920
3921
if ( ulLoopCounter == cOCT6100_MAX_LOOP_CPU_TIMEOUT )
3922
return cOCT6100_ERR_OPEN_AF_CPU_TIMEOUT;
3923
}
3924
3925
/* Return NLP in operationnal mode. */
3926
WriteParams.ulWriteAddress = 0x2C2;
3927
WriteParams.usWriteData = 0x060E;
3928
3929
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3930
if ( ulResult != cOCT6100_ERR_OK )
3931
return ulResult;
3932
3933
WriteParams.ulWriteAddress = 0x692;
3934
WriteParams.usWriteData = 0x0000;
3935
3936
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
3937
if ( ulResult != cOCT6100_ERR_OK )
3938
return ulResult;
3939
3940
return cOCT6100_ERR_OK;
3941
}
3942
#endif
3943
3944
3945
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
3946
3947
Function: Oct6100ApiSetH100Register
3948
3949
Description: This function will configure the H.100 registers.
3950
3951
-------------------------------------------------------------------------------
3952
| Argument | Description
3953
-------------------------------------------------------------------------------
3954
f_pApiInstance Pointer to API instance. This memory is used to keep the
3955
present state of the chip and all its resources.
3956
3957
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
3958
#if !SKIP_Oct6100ApiSetH100Register
3959
UINT32 Oct6100ApiSetH100Register(
3960
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
3961
{
3962
tOCT6100_WRITE_PARAMS WriteParams;
3963
UINT32 ulResult;
3964
tPOCT6100_SHARED_INFO pSharedInfo;
3965
tPOCT6100_API_CHIP_CONFIG pChipConfig;
3966
UINT32 i;
3967
UINT32 ulOffset;
3968
BOOL fAllStreamAt2Mhz = TRUE;
3969
const UINT16 ausAdpcmResetContext[32] = { 0x1100, 0x0220, 0x0000, 0x0000, 0x0000, 0x0020, 0x0000, 0x0000, 0x0008, 0x0000, 0x0000, 0x0100, 0x0000, 0x0020, 0x0000, 0x0000, 0x0000, 0x0002, 0x0000, 0x0000, 0x0040,
3970
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x8000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000};
3971
3972
/* Get local pointer to shared portion of instance. */
3973
pSharedInfo = f_pApiInstance->pSharedInfo;
3974
3975
/* Get local pointer to the chip configuration structure. */
3976
pChipConfig = &f_pApiInstance->pSharedInfo->ChipConfig;
3977
3978
/* Initialize the process context and user chip ID once and for all. */
3979
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
3980
3981
WriteParams.ulUserChipId = f_pApiInstance->pSharedInfo->ChipConfig.ulUserChipId;
3982
3983
/* Set the Global OE bit. */
3984
WriteParams.ulWriteAddress = 0x300;
3985
WriteParams.usWriteData = 0x0004;
3986
3987
/* Set the number of streams. */
3988
switch( pChipConfig->byMaxTdmStreams )
3989
{
3990
case 32:
3991
WriteParams.usWriteData |= ( 0 << 3 );
3992
break;
3993
case 16:
3994
WriteParams.usWriteData |= ( 1 << 3 );
3995
break;
3996
case 8:
3997
WriteParams.usWriteData |= ( 2 << 3 );
3998
break;
3999
case 4:
4000
WriteParams.usWriteData |= ( 3 << 3 );
4001
break;
4002
default:
4003
break;
4004
}
4005
4006
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4007
if ( ulResult != cOCT6100_ERR_OK )
4008
return ulResult;
4009
4010
/* Configure the stream frequency. */
4011
WriteParams.ulWriteAddress = 0x330;
4012
WriteParams.usWriteData = 0x0000;
4013
for ( i = 0; i < (UINT32)(pChipConfig->byMaxTdmStreams / 4); i++)
4014
{
4015
ulOffset = i*2;
4016
switch( pChipConfig->aulTdmStreamFreqs[ i ] )
4017
{
4018
case cOCT6100_TDM_STREAM_FREQ_2MHZ:
4019
WriteParams.usWriteData |= ( 0x0 << ulOffset );
4020
break;
4021
case cOCT6100_TDM_STREAM_FREQ_4MHZ:
4022
WriteParams.usWriteData |= ( 0x1 << ulOffset );
4023
fAllStreamAt2Mhz = FALSE;
4024
break;
4025
case cOCT6100_TDM_STREAM_FREQ_8MHZ:
4026
WriteParams.usWriteData |= ( 0x2 << ulOffset );
4027
fAllStreamAt2Mhz = FALSE;
4028
break;
4029
default:
4030
break;
4031
}
4032
}
4033
4034
/* Set the stream to 16 MHz if the fast H.100 mode is selected. */
4035
if ( pChipConfig->fEnableFastH100Mode == TRUE )
4036
{
4037
fAllStreamAt2Mhz = FALSE;
4038
WriteParams.usWriteData = 0xFFFF;
4039
}
4040
4041
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4042
if ( ulResult != cOCT6100_ERR_OK )
4043
return ulResult;
4044
4045
if ( pSharedInfo->ChipConfig.fEnableFastH100Mode == TRUE )
4046
{
4047
/* Make the chip track both clock A and B to perform fast H.100 mode. */
4048
WriteParams.ulWriteAddress = 0x322;
4049
WriteParams.usWriteData = 0x0004;
4050
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4051
if ( ulResult != cOCT6100_ERR_OK )
4052
return ulResult;
4053
4054
/* Enable the fast H.100 mode. */
4055
WriteParams.ulWriteAddress = 0x332;
4056
WriteParams.usWriteData = 0x0003;
4057
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4058
if ( ulResult != cOCT6100_ERR_OK )
4059
return ulResult;
4060
}
4061
4062
WriteParams.ulWriteAddress = 0x376;
4063
WriteParams.usWriteData = (UINT16)( pSharedInfo->MiscVars.usTdmClkBoundary );
4064
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4065
if ( ulResult != cOCT6100_ERR_OK )
4066
return ulResult;
4067
4068
/* Select delay for early clock (90 and 110). */
4069
WriteParams.ulWriteAddress = 0x378;
4070
if ( pSharedInfo->ChipConfig.fEnableFastH100Mode == TRUE )
4071
WriteParams.usWriteData = 0x000A;
4072
else
4073
{
4074
/* Set the TDM sampling. */
4075
if ( pSharedInfo->ChipConfig.byTdmSampling == cOCT6100_TDM_SAMPLE_AT_RISING_EDGE )
4076
{
4077
WriteParams.usWriteData = 0x0AF0;
4078
}
4079
else if ( pSharedInfo->ChipConfig.byTdmSampling == cOCT6100_TDM_SAMPLE_AT_FALLING_EDGE )
4080
{
4081
WriteParams.usWriteData = 0x0A0F;
4082
}
4083
else /* pSharedInfo->ChipConfig.ulTdmSampling == cOCT6100_TDM_SAMPLE_AT_3_QUARTERS */
4084
{
4085
WriteParams.usWriteData = 0x0A08;
4086
}
4087
}
4088
4089
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4090
if ( ulResult != cOCT6100_ERR_OK )
4091
return ulResult;
4092
4093
/* Protect chip by preventing too rapid timeslot arrival (mclk == 133 MHz). */
4094
WriteParams.ulWriteAddress = 0x37A;
4095
WriteParams.usWriteData = (UINT16)pSharedInfo->MiscVars.usMaxH100Speed;
4096
4097
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4098
if ( ulResult != cOCT6100_ERR_OK )
4099
return ulResult;
4100
4101
/* Allow H.100 TS to progress. */
4102
WriteParams.ulWriteAddress = 0x382;
4103
WriteParams.usWriteData = 0x0000;
4104
4105
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4106
if ( ulResult != cOCT6100_ERR_OK )
4107
return ulResult;
4108
4109
/* Set by-pass mode. */
4110
WriteParams.ulWriteAddress = 0x50E;
4111
WriteParams.usWriteData = 0x0001;
4112
4113
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4114
if ( ulResult != cOCT6100_ERR_OK )
4115
return ulResult;
4116
4117
/* TDMIE bits. */
4118
WriteParams.ulWriteAddress = 0x500;
4119
WriteParams.usWriteData = 0x0003;
4120
4121
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4122
if ( ulResult != cOCT6100_ERR_OK )
4123
return ulResult;
4124
4125
/* Write normal ADPCM reset values in ADPCM context 1344. */
4126
for(i=0;i<32;i++)
4127
{
4128
WriteParams.ulWriteAddress = 0x140000 + ( 0x40 * 1344 ) + ( i * 2 );
4129
WriteParams.usWriteData = ausAdpcmResetContext[i];
4130
4131
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4132
if ( ulResult != cOCT6100_ERR_OK )
4133
return ulResult;
4134
}
4135
4136
/* Make sure delay flops are configured correctly if all streams are at 2 MHz. */
4137
if ( fAllStreamAt2Mhz == TRUE )
4138
{
4139
/* Setup H.100 sampling to lowest value. */
4140
WriteParams.ulWriteAddress = 0x144;
4141
WriteParams.usWriteData = 0x4041;
4142
4143
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4144
if ( ulResult != cOCT6100_ERR_OK )
4145
return ulResult;
4146
4147
WriteParams.ulWriteAddress = 0x378;
4148
WriteParams.usWriteData = 0x0A00;
4149
4150
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4151
if ( ulResult != cOCT6100_ERR_OK )
4152
return ulResult;
4153
}
4154
4155
return cOCT6100_ERR_OK;
4156
}
4157
#endif
4158
4159
4160
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
4161
4162
Function: Oct6100ApiWriteMiscellaneousRegisters
4163
4164
Description: This function will write to various registers to activate the chip.
4165
4166
-------------------------------------------------------------------------------
4167
| Argument | Description
4168
-------------------------------------------------------------------------------
4169
f_pApiInstance Pointer to API instance. This memory is used to keep the
4170
present state of the chip and all its resources.
4171
4172
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
4173
#if !SKIP_Oct6100ApiWriteMiscellaneousRegisters
4174
UINT32 Oct6100ApiWriteMiscellaneousRegisters(
4175
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
4176
{
4177
tOCT6100_WRITE_PARAMS WriteParams;
4178
UINT32 ulResult;
4179
4180
/* Initialize the process context and user chip ID once and for all. */
4181
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
4182
4183
WriteParams.ulUserChipId = f_pApiInstance->pSharedInfo->ChipConfig.ulUserChipId;
4184
4185
/* Free the interrupt pin of the chip (i.e. remove minimum time requirement between interrupts). */
4186
WriteParams.ulWriteAddress = 0x214;
4187
WriteParams.usWriteData = 0x0000;
4188
if ( f_pApiInstance->pSharedInfo->ChipConfig.byInterruptPolarity == cOCT6100_ACTIVE_HIGH_POLARITY )
4189
WriteParams.usWriteData |= 0x4000;
4190
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
4191
if ( ulResult != cOCT6100_ERR_OK )
4192
return ulResult;
4193
4194
/* Write MT chariot interval */
4195
WriteParams.ulWriteAddress = 0x2C2;
4196
if ( f_pApiInstance->pSharedInfo->ImageInfo.usMaxNumberOfChannels > 640 )
4197
WriteParams.usWriteData = 0x05EA;
4198
else if ( f_pApiInstance->pSharedInfo->ImageInfo.usMaxNumberOfChannels > 513 )
4199
WriteParams.usWriteData = 0x0672;
4200
else /* if ( f_pApiInstance->pSharedInfo->ImageInfo.usMaxNumberOfChannels <= 513 ) */
4201
WriteParams.usWriteData = 0x0750;
4202
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4203
if ( ulResult != cOCT6100_ERR_OK )
4204
return ulResult;
4205
4206
/* Write set second part5 time. */
4207
WriteParams.ulWriteAddress = 0x2C4;
4208
WriteParams.usWriteData = 0x04A0;
4209
4210
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4211
if ( ulResult != cOCT6100_ERR_OK )
4212
return ulResult;
4213
4214
/* Write CPU bucket timer to guarantee 200 cycles between each CPU access. */
4215
WriteParams.ulWriteAddress = 0x234;
4216
WriteParams.usWriteData = 0x0804;
4217
4218
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4219
if ( ulResult != cOCT6100_ERR_OK )
4220
return ulResult;
4221
4222
WriteParams.ulWriteAddress = 0x236;
4223
WriteParams.usWriteData = 0x0100;
4224
4225
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4226
if ( ulResult != cOCT6100_ERR_OK )
4227
return ulResult;
4228
4229
return cOCT6100_ERR_OK;
4230
}
4231
#endif
4232
4233
4234
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
4235
4236
Function: Oct6100ApiCreateSerializeObjects
4237
4238
Description: Creates a handle to each serialization object used by the API.
4239
4240
Note that in a multi-process system the user's process context
4241
structure pointer is needed by this function. Thus, the
4242
pointer must be valid.
4243
4244
-------------------------------------------------------------------------------
4245
| Argument | Description
4246
-------------------------------------------------------------------------------
4247
f_pApiInstance Pointer to API instance. This memory is used to keep the
4248
present state of the chip and all its resources.
4249
4250
f_ulUserChipId User chip ID for this serialization object.
4251
4252
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
4253
#if !SKIP_Oct6100ApiCreateSerializeObjects
4254
UINT32 Oct6100ApiCreateSerializeObjects(
4255
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance,
4256
IN UINT32 f_ulUserChipId )
4257
{
4258
tOCT6100_CREATE_SERIALIZE_OBJECT CreateSerObj;
4259
UINT32 ulResult;
4260
CHAR szSerObjName[ 64 ] = "Oct6100ApiXXXXXXXXApiSerObj";
4261
4262
4263
/* Set some parameters of the create structure once and for all. */
4264
CreateSerObj.pProcessContext = f_pApiInstance->pProcessContext;
4265
CreateSerObj.pszSerialObjName = szSerObjName;
4266
4267
/*----------------------------------------------------------------------*/
4268
/* Set the chip ID in the semaphore name. */
4269
szSerObjName[ 10 ] = (CHAR) Oct6100ApiHexToAscii( (f_ulUserChipId >> 28 ) & 0xFF );
4270
szSerObjName[ 11 ] = (CHAR) Oct6100ApiHexToAscii( (f_ulUserChipId >> 24 ) & 0xFF );
4271
szSerObjName[ 12 ] = (CHAR) Oct6100ApiHexToAscii( (f_ulUserChipId >> 20 ) & 0xFF );
4272
szSerObjName[ 13 ] = (CHAR) Oct6100ApiHexToAscii( (f_ulUserChipId >> 16 ) & 0xFF );
4273
szSerObjName[ 14 ] = (CHAR) Oct6100ApiHexToAscii( (f_ulUserChipId >> 12 ) & 0xFF );
4274
szSerObjName[ 15 ] = (CHAR) Oct6100ApiHexToAscii( (f_ulUserChipId >> 8 ) & 0xFF );
4275
szSerObjName[ 16 ] = (CHAR) Oct6100ApiHexToAscii( (f_ulUserChipId >> 4 ) & 0xFF );
4276
szSerObjName[ 17 ] = (CHAR) Oct6100ApiHexToAscii( (f_ulUserChipId >> 0 ) & 0xFF );
4277
4278
ulResult = Oct6100UserCreateSerializeObject( &CreateSerObj );
4279
if ( ulResult != cOCT6100_ERR_OK )
4280
return ulResult;
4281
f_pApiInstance->ulApiSerObj = CreateSerObj.ulSerialObjHndl;
4282
/*----------------------------------------------------------------------*/
4283
4284
4285
4286
return cOCT6100_ERR_OK;
4287
}
4288
#endif
4289
4290
4291
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
4292
4293
Function: Oct6100ApiDestroySerializeObjects
4294
4295
Description: Destroy handles to each serialization object used by the API.
4296
4297
Note that in a multi-process system the user's process context
4298
structure pointer is needed by this function. Thus, the
4299
pointer must be valid.
4300
4301
-------------------------------------------------------------------------------
4302
| Argument | Description
4303
-------------------------------------------------------------------------------
4304
f_pApiInstance Pointer to API instance. This memory is used to keep the
4305
present state of the chip and all its resources.
4306
4307
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
4308
#if !SKIP_Oct6100ApiDestroySerializeObjects
4309
UINT32 Oct6100ApiDestroySerializeObjects(
4310
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
4311
{
4312
tOCT6100_DESTROY_SERIALIZE_OBJECT DestroySerObj;
4313
UINT32 ulResult;
4314
4315
/* Set some parameters of the create structure once and for all. */
4316
DestroySerObj.pProcessContext = f_pApiInstance->pProcessContext;
4317
DestroySerObj.ulSerialObjHndl = f_pApiInstance->ulApiSerObj;
4318
4319
ulResult = Oct6100UserDestroySerializeObject( &DestroySerObj );
4320
if ( ulResult != cOCT6100_ERR_OK )
4321
return ulResult;
4322
4323
return cOCT6100_ERR_OK;
4324
}
4325
#endif
4326
4327
4328
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
4329
4330
Function: Oct6100ApiRunEgo
4331
4332
Description: Private function used to communicate with the internal processors.
4333
4334
-------------------------------------------------------------------------------
4335
| Argument | Description
4336
-------------------------------------------------------------------------------
4337
f_pApiInstance Pointer to API instance. This memory is used to keep the
4338
present state of the chip and all its resources.
4339
4340
f_fStoreFlag Type of access performed. (Load or Store)
4341
f_ulNumEntry Number of access.
4342
f_aulEntry Array of access to perform.
4343
4344
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
4345
#if !SKIP_Oct6100ApiRunEgo
4346
UINT32 Oct6100ApiRunEgo(
4347
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance,
4348
IN BOOL f_fStoreFlag,
4349
IN UINT32 f_ulNumEntry,
4350
OUT PUINT32 f_aulEntry )
4351
{
4352
tPOCT6100_SHARED_INFO pSharedInfo;
4353
tPOCT6100_API_CHIP_CONFIG pChipConfig;
4354
tOCT6100_WRITE_PARAMS WriteParams;
4355
tOCT6100_READ_PARAMS ReadParams;
4356
UINT32 ulResult;
4357
UINT32 aulCpuLsuCmd[ 2 ];
4358
UINT16 usReadData;
4359
UINT32 i;
4360
BOOL fConditionFlag = TRUE;
4361
UINT32 ulLoopCounter = 0;
4362
4363
/* Get local pointer to shared portion of instance. */
4364
pSharedInfo = f_pApiInstance->pSharedInfo;
4365
4366
/* Get local pointer to the chip configuration structure. */
4367
pChipConfig = &f_pApiInstance->pSharedInfo->ChipConfig;
4368
4369
/* Set the process context and user chip ID parameters once and for all. */
4370
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
4371
4372
WriteParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
4373
4374
ReadParams.pProcessContext = f_pApiInstance->pProcessContext;
4375
4376
ReadParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
4377
ReadParams.pusReadData = &usReadData;
4378
4379
/* No more than 2 entries may be requested. */
4380
if ( f_ulNumEntry > 2 )
4381
return cOCT6100_ERR_FATAL_1B;
4382
4383
/* Write the requested entries at address reserved for CPU. */
4384
for( i = 0; i < f_ulNumEntry; i++ )
4385
{
4386
WriteParams.ulWriteAddress = cOCT6100_PART1_API_SCRATCH_PAD + ( 0x8 * i );
4387
WriteParams.usWriteData = (UINT16)(( f_aulEntry[ i * 2 ] >> 16 ) & 0xFFFF );
4388
4389
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4390
if ( ulResult != cOCT6100_ERR_OK )
4391
return ulResult;
4392
4393
WriteParams.ulWriteAddress += 2;
4394
WriteParams.usWriteData = (UINT16)( f_aulEntry[ i * 2 ] & 0xFFFF );
4395
4396
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4397
if ( ulResult != cOCT6100_ERR_OK )
4398
return ulResult;
4399
4400
WriteParams.ulWriteAddress += 2;
4401
WriteParams.usWriteData = (UINT16)(( f_aulEntry[ (i * 2) + 1] >> 16 ) & 0xFFFF );
4402
4403
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4404
if ( ulResult != cOCT6100_ERR_OK )
4405
return ulResult;
4406
4407
WriteParams.ulWriteAddress += 2;
4408
WriteParams.usWriteData = (UINT16)( f_aulEntry[ (i * 2) + 1] & 0xFFFF );
4409
4410
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4411
if ( ulResult != cOCT6100_ERR_OK )
4412
return ulResult;
4413
}
4414
4415
/* Preincrement code point. */
4416
pSharedInfo->MiscVars.usCodepoint++;
4417
4418
/* Create DWORD 0 of command. */
4419
aulCpuLsuCmd[0] = 0x00000000;
4420
if ( f_fStoreFlag == FALSE )
4421
aulCpuLsuCmd[0] |= 0xC0000000; /* EGO load. */
4422
else
4423
aulCpuLsuCmd[0] |= 0xE0000000; /* EGO store. */
4424
4425
aulCpuLsuCmd[0] |= (f_ulNumEntry - 1) << 19;
4426
aulCpuLsuCmd[0] |= cOCT6100_PART1_API_SCRATCH_PAD;
4427
4428
/* Create DWORD 1 of command. */
4429
aulCpuLsuCmd[1] = 0x00000000;
4430
aulCpuLsuCmd[1] |= ( ( cOCT6100_PART1_API_SCRATCH_PAD + 0x10 ) & 0xFFFF ) << 16;
4431
aulCpuLsuCmd[1] |= pSharedInfo->MiscVars.usCodepoint;
4432
4433
/* Write the EGO command in the LSU CB. */
4434
WriteParams.ulWriteAddress = cOCT6100_PART1_CPU_LSU_CB_BASE + ((pSharedInfo->MiscVars.usCpuLsuWritePtr & 0x7) * 0x8 );
4435
WriteParams.usWriteData = (UINT16)(( aulCpuLsuCmd[ 0 ] >> 16 ) & 0xFFFF );
4436
4437
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4438
if ( ulResult != cOCT6100_ERR_OK )
4439
return ulResult;
4440
4441
WriteParams.ulWriteAddress += 2;
4442
WriteParams.usWriteData = (UINT16)( aulCpuLsuCmd[ 0 ] & 0xFFFF );
4443
4444
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4445
if ( ulResult != cOCT6100_ERR_OK )
4446
return ulResult;
4447
4448
WriteParams.ulWriteAddress += 2;
4449
WriteParams.usWriteData = (UINT16)(( aulCpuLsuCmd[ 1 ] >> 16 ) & 0xFFFF );
4450
4451
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4452
if ( ulResult != cOCT6100_ERR_OK )
4453
return ulResult;
4454
4455
WriteParams.ulWriteAddress += 2;
4456
WriteParams.usWriteData = (UINT16)( aulCpuLsuCmd[ 1 ] & 0xFFFF );
4457
4458
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4459
if ( ulResult != cOCT6100_ERR_OK )
4460
return ulResult;
4461
4462
/* Post increment the write pointer. */
4463
pSharedInfo->MiscVars.usCpuLsuWritePtr++;
4464
4465
/* Indicate new write pointer position to HW. */
4466
WriteParams.ulWriteAddress = cOCT6100_PART1_EGO_REG + 0x5A;
4467
WriteParams.usWriteData = (UINT16)( pSharedInfo->MiscVars.usCpuLsuWritePtr & 0x7 );
4468
4469
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4470
if ( ulResult != cOCT6100_ERR_OK )
4471
return ulResult;
4472
4473
/* Wait for codepoint to be updated before returning. */
4474
while( fConditionFlag )
4475
{
4476
ReadParams.ulReadAddress = cOCT6100_PART1_API_SCRATCH_PAD + 0x12;
4477
usReadData = (UINT16)( pSharedInfo->MiscVars.usCodepoint );
4478
4479
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
4480
if ( ulResult != cOCT6100_ERR_OK )
4481
return ulResult;
4482
4483
if ( usReadData == pSharedInfo->MiscVars.usCodepoint )
4484
fConditionFlag = FALSE;
4485
4486
ulLoopCounter++;
4487
4488
if ( ulLoopCounter == cOCT6100_MAX_LOOP )
4489
return cOCT6100_ERR_OPEN_EGO_TIMEOUT;
4490
}
4491
4492
/* CRC error bit must be zero. */
4493
ReadParams.ulReadAddress = 0x202;
4494
4495
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
4496
if ( ulResult != cOCT6100_ERR_OK )
4497
return ulResult;
4498
4499
if ( ( usReadData & 0x0400 ) != 0 )
4500
return cOCT6100_ERR_OPEN_CORRUPTED_IMAGE;
4501
4502
return cOCT6100_ERR_OK;
4503
}
4504
#endif
4505
4506
4507
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
4508
4509
Function: Oct6100ApiCreateEgoEntry
4510
4511
Description: Private function used to create an access structure to be sent
4512
to the internal processors.
4513
4514
-------------------------------------------------------------------------------
4515
| Argument | Description
4516
-------------------------------------------------------------------------------
4517
f_ulExternalAddress External memory address for the access.
4518
f_ulInternalAddress Which process should receive the command.
4519
f_ulNumBytes Number of bytes associated to the access.
4520
f_aulEntry Array of access to perform.
4521
4522
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
4523
#if !SKIP_Oct6100ApiCreateEgoEntry
4524
UINT32 Oct6100ApiCreateEgoEntry(
4525
IN UINT32 f_ulExternalAddress,
4526
IN UINT32 f_ulInternalAddress,
4527
IN UINT32 f_ulNumBytes,
4528
OUT UINT32 f_aulEntry[ 2 ] )
4529
{
4530
f_aulEntry[0] = 0x80000000;
4531
f_aulEntry[0] |= f_ulExternalAddress & 0x07FFFFFC;
4532
4533
f_aulEntry[1] = 0x0011C000;
4534
f_aulEntry[1] |= (f_ulNumBytes / 8) << 23;
4535
f_aulEntry[1] |= (f_ulInternalAddress >> 2) & 0x3FFF;
4536
4537
return cOCT6100_ERR_OK;
4538
}
4539
#endif
4540
4541
4542
4543
4544
4545
4546
4547
4548
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
4549
4550
Function: Oct6100ApiInitChannels
4551
4552
Description: This function will initialize all the channels to power down.
4553
4554
-------------------------------------------------------------------------------
4555
| Argument | Description
4556
-------------------------------------------------------------------------------
4557
f_pApiInstance Pointer to API instance. This memory is used to keep the
4558
present state of the chip and all its resources.
4559
4560
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
4561
#if !SKIP_Oct6100ApiInitChannels
4562
UINT32 Oct6100ApiInitChannels(
4563
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
4564
{
4565
tPOCT6100_SHARED_INFO pSharedInfo;
4566
UINT32 i;
4567
UINT32 ulResult;
4568
tOCT6100_WRITE_BURST_PARAMS BurstParams;
4569
tOCT6100_WRITE_PARAMS WriteParams;
4570
tOCT6100_READ_PARAMS ReadParams;
4571
UINT16 usReadData;
4572
UINT32 ulTempData;
4573
UINT32 ulBaseAddress;
4574
UINT32 ulFeatureBytesOffset;
4575
UINT32 ulFeatureBitOffset;
4576
UINT32 ulFeatureFieldLength;
4577
UINT32 ulMask;
4578
UINT16 ausWriteData[ 4 ];
4579
UINT16 usLoopCount = 0;
4580
UINT16 usWriteData = 0;
4581
UINT16 usMclkRead;
4582
UINT16 usLastMclkRead;
4583
UINT16 usMclkDiff;
4584
UINT32 ulNumberOfCycleToWait;
4585
UINT32 ulTimeoutCounter;
4586
4587
pSharedInfo = f_pApiInstance->pSharedInfo;
4588
4589
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
4590
4591
WriteParams.ulUserChipId = f_pApiInstance->pSharedInfo->ChipConfig.ulUserChipId;
4592
4593
BurstParams.pProcessContext = f_pApiInstance->pProcessContext;
4594
4595
BurstParams.ulUserChipId = f_pApiInstance->pSharedInfo->ChipConfig.ulUserChipId;
4596
BurstParams.pusWriteData = ausWriteData;
4597
4598
ReadParams.pProcessContext = f_pApiInstance->pProcessContext;
4599
4600
ReadParams.ulUserChipId = f_pApiInstance->pSharedInfo->ChipConfig.ulUserChipId;
4601
ReadParams.pusReadData = &usReadData;
4602
4603
/* Verify that the image has enough memory to work correctly. */
4604
if ( ( pSharedInfo->MiscVars.ulTotalMemSize + cOCT6100_EXTERNAL_MEM_BASE_ADDRESS ) < pSharedInfo->MemoryMap.ulFreeMemBaseAddress )
4605
return cOCT6100_ERR_OPEN_INSUFFICIENT_EXTERNAL_MEMORY;
4606
4607
/* Verify that the tail length is supported by the device.*/
4608
if ( pSharedInfo->ChipConfig.usTailDisplacement > pSharedInfo->ImageInfo.usMaxTailDisplacement )
4609
return cOCT6100_ERR_NOT_SUPPORTED_OPEN_TAIL_DISPLACEMENT_VALUE;
4610
4611
/* Verify that acoustic echo is supported by the device. */
4612
if ( pSharedInfo->ChipConfig.fEnableAcousticEcho == TRUE && pSharedInfo->ImageInfo.fAcousticEcho == FALSE )
4613
return cOCT6100_ERR_NOT_SUPPORTED_OPEN_ACOUSTIC_ECHO;
4614
4615
/* Verify that the image supports all the requested channels. */
4616
if ( pSharedInfo->ChipConfig.usMaxChannels > pSharedInfo->ImageInfo.usMaxNumberOfChannels )
4617
return cOCT6100_ERR_NOT_SUPPORTED_OPEN_MAX_ECHO_CHANNELS_VALUE;
4618
4619
/* Max number of channels the image supports + 1 for channel recording, if requested */
4620
if ( ( pSharedInfo->ChipConfig.fEnableChannelRecording == TRUE )
4621
&& ( pSharedInfo->ImageInfo.usMaxNumberOfChannels < cOCT6100_MAX_ECHO_CHANNELS )
4622
&& ( pSharedInfo->ChipConfig.usMaxChannels == pSharedInfo->ImageInfo.usMaxNumberOfChannels ) )
4623
return cOCT6100_ERR_NOT_SUPPORTED_OPEN_MAX_ECHO_CHANNELS_VALUE;
4624
4625
/* Initialize the memory for all required channels. */
4626
for( i = 0; i < f_pApiInstance->pSharedInfo->ChipConfig.usMaxChannels; i++ )
4627
{
4628
/*==============================================================================*/
4629
/* Configure the Global Static Configuration memory of the channel. */
4630
4631
ulBaseAddress = cOCT6100_CHANNEL_ROOT_BASE + ( i * cOCT6100_CHANNEL_ROOT_SIZE ) + cOCT6100_CHANNEL_ROOT_GLOBAL_CONF_OFFSET;
4632
4633
/* Set the PGSP context base address. */
4634
ulTempData = pSharedInfo->MemoryMap.ulChanMainMemBase + ( i * pSharedInfo->MemoryMap.ulChanMainMemSize ) + cOCT6100_CH_MAIN_PGSP_CONTEXT_OFFSET;
4635
4636
WriteParams.ulWriteAddress = ulBaseAddress + cOCT6100_GSC_PGSP_CONTEXT_BASE_ADD_OFFSET;
4637
WriteParams.usWriteData = (UINT16)( ulTempData >> 16 );
4638
4639
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4640
if ( ulResult != cOCT6100_ERR_OK )
4641
return ulResult;
4642
4643
WriteParams.ulWriteAddress += 2;
4644
WriteParams.usWriteData = (UINT16)( ulTempData & 0xFFFF );
4645
4646
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4647
if ( ulResult != cOCT6100_ERR_OK )
4648
return ulResult;
4649
4650
/* Set the PGSP init context base address. */
4651
ulTempData = ( cOCT6100_IMAGE_FILE_BASE + 0x200 ) & 0x07FFFFFF;
4652
4653
WriteParams.ulWriteAddress = ulBaseAddress + cOCT6100_GSC_PGSP_INIT_CONTEXT_BASE_ADD_OFFSET;
4654
WriteParams.usWriteData = (UINT16)( ulTempData >> 16 );
4655
4656
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4657
if ( ulResult != cOCT6100_ERR_OK )
4658
return ulResult;
4659
4660
WriteParams.ulWriteAddress += 2;
4661
WriteParams.usWriteData = (UINT16)( ulTempData & 0xFFFF );
4662
4663
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4664
if ( ulResult != cOCT6100_ERR_OK )
4665
return ulResult;
4666
4667
/* Set the RIN circular buffer base address. */
4668
ulTempData = pSharedInfo->MemoryMap.ulChanMainMemBase + ( i * pSharedInfo->MemoryMap.ulChanMainMemSize ) + pSharedInfo->MemoryMap.ulChanMainRinCBMemOfst;
4669
4670
/* Set the circular buffer size. */
4671
ulTempData &= 0xFFFFFF00;
4672
if (( pSharedInfo->MemoryMap.ulChanMainRinCBMemSize & 0xFFFF00FF ) != 0 )
4673
return cOCT6100_ERR_CHANNEL_INVALID_RIN_CB_SIZE;
4674
ulTempData |= pSharedInfo->MemoryMap.ulChanMainRinCBMemSize >> 8;
4675
4676
WriteParams.ulWriteAddress = ulBaseAddress + cOCT6100_GSC_RIN_CIRC_BUFFER_BASE_ADD_OFFSET;
4677
WriteParams.usWriteData = (UINT16)( ulTempData >> 16 );
4678
4679
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4680
if ( ulResult != cOCT6100_ERR_OK )
4681
return ulResult;
4682
4683
WriteParams.ulWriteAddress += 2;
4684
WriteParams.usWriteData = (UINT16)( ulTempData & 0xFFFF );
4685
4686
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4687
if ( ulResult != cOCT6100_ERR_OK )
4688
return ulResult;
4689
4690
/* Set the SIN circular buffer base address. */
4691
ulTempData = pSharedInfo->MemoryMap.ulChanMainMemBase + ( i * pSharedInfo->MemoryMap.ulChanMainMemSize ) + pSharedInfo->MemoryMap.ulChanMainSinCBMemOfst;
4692
4693
WriteParams.ulWriteAddress = ulBaseAddress + cOCT6100_GSC_SIN_CIRC_BUFFER_BASE_ADD_OFFSET;
4694
WriteParams.usWriteData = (UINT16)( ulTempData >> 16 );
4695
4696
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4697
if ( ulResult != cOCT6100_ERR_OK )
4698
return ulResult;
4699
4700
WriteParams.ulWriteAddress += 2;
4701
WriteParams.usWriteData = (UINT16)( ulTempData & 0xFFFF );
4702
4703
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4704
if ( ulResult != cOCT6100_ERR_OK )
4705
return ulResult;
4706
4707
/* Set the SOUT circular buffer base address. */
4708
ulTempData = pSharedInfo->MemoryMap.ulChanMainMemBase + ( i * pSharedInfo->MemoryMap.ulChanMainMemSize ) + pSharedInfo->MemoryMap.ulChanMainSoutCBMemOfst;;
4709
4710
WriteParams.ulWriteAddress = ulBaseAddress + cOCT6100_GSC_SOUT_CIRC_BUFFER_BASE_ADD_OFFSET;
4711
WriteParams.usWriteData = (UINT16)( ulTempData >> 16 );
4712
4713
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4714
if ( ulResult != cOCT6100_ERR_OK )
4715
return ulResult;
4716
4717
WriteParams.ulWriteAddress += 2;
4718
WriteParams.usWriteData = (UINT16)( ulTempData & 0xFFFF );
4719
4720
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4721
if ( ulResult != cOCT6100_ERR_OK )
4722
return ulResult;
4723
4724
/*==============================================================================*/
4725
}
4726
4727
/* Put all channel in powerdown mode "3". */
4728
for( i = 0; i < f_pApiInstance->pSharedInfo->ChipConfig.usMaxChannels; i++ )
4729
{
4730
WriteParams.ulWriteAddress = 0x014000 + (i*4) + 0;
4731
WriteParams.usWriteData = 0x85FF; /* TSI index 1535 reserved for power-down mode */
4732
4733
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4734
if ( ulResult != cOCT6100_ERR_OK )
4735
return ulResult;
4736
4737
WriteParams.ulWriteAddress = 0x014000 + (i*4) + 2;
4738
WriteParams.usWriteData = 0xC5FF; /* TSI index 1535 reserved for power-down mode */
4739
4740
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4741
if ( ulResult != cOCT6100_ERR_OK )
4742
return ulResult;
4743
}
4744
4745
/* Set the maximum number of channels. */
4746
WriteParams.ulWriteAddress = 0x690;
4747
if ( pSharedInfo->ImageInfo.usMaxNumberOfChannels < 384 )
4748
WriteParams.usWriteData = 384;
4749
else
4750
WriteParams.usWriteData = (UINT16)pSharedInfo->ImageInfo.usMaxNumberOfChannels;
4751
4752
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4753
if ( ulResult != cOCT6100_ERR_OK )
4754
return ulResult;
4755
4756
/* Set power-dowm TSI chariot memory to silence. */
4757
for( i = 0; i < 6; i++ )
4758
{
4759
WriteParams.ulWriteAddress = 0x20000 + ( i * 0x1000 ) + ( 1534 * 2 );
4760
WriteParams.usWriteData = 0xFF;
4761
4762
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4763
if ( ulResult != cOCT6100_ERR_OK )
4764
return ulResult;
4765
4766
WriteParams.ulWriteAddress = 0x20000 + ( i * 0x1000 ) + ( 1535 * 2 );
4767
WriteParams.usWriteData = 0xFF;
4768
4769
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4770
if ( ulResult != cOCT6100_ERR_OK )
4771
return ulResult;
4772
}
4773
4774
/* Remove chariot hold. */
4775
WriteParams.ulWriteAddress = 0x500;
4776
WriteParams.usWriteData = 0x0001;
4777
4778
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4779
if ( ulResult != cOCT6100_ERR_OK )
4780
return ulResult;
4781
4782
for( usLoopCount = 0; usLoopCount < 4096; usLoopCount++ )
4783
{
4784
if ( (usLoopCount % 16) < 8 )
4785
{
4786
usWriteData = (UINT16)((usLoopCount / 16) << 7);
4787
usWriteData |= (UINT16)((usLoopCount % 8));
4788
}
4789
else
4790
{
4791
usWriteData = (UINT16)((usLoopCount / 16) << 7);
4792
usWriteData |= (UINT16)((usLoopCount % 8));
4793
usWriteData |= 0x78;
4794
}
4795
4796
/* Set timeslot pointer. */
4797
WriteParams.ulWriteAddress = 0x50E;
4798
WriteParams.usWriteData = 0x0003;
4799
WriteParams.usWriteData |= usWriteData << 2;
4800
4801
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4802
if ( ulResult != cOCT6100_ERR_OK )
4803
return ulResult;
4804
4805
/* Now read the mclk counter. */
4806
ReadParams.ulReadAddress = 0x30A;
4807
ReadParams.pusReadData = &usLastMclkRead;
4808
4809
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
4810
if ( ulResult != cOCT6100_ERR_OK )
4811
return ulResult;
4812
4813
/* Reset loop timeout counter. */
4814
ulTimeoutCounter = 0x0;
4815
4816
do {
4817
ReadParams.pusReadData = &usMclkRead;
4818
4819
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
4820
if ( ulResult != cOCT6100_ERR_OK )
4821
return ulResult;
4822
4823
if ( ( usLoopCount % 16 ) != 15 )
4824
{
4825
ulNumberOfCycleToWait = 133;
4826
}
4827
else
4828
{
4829
ulNumberOfCycleToWait = 20000;
4830
}
4831
4832
/* Evaluate the difference. */
4833
usMclkDiff = (UINT16)(( usMclkRead - usLastMclkRead ) & 0xFFFF);
4834
4835
/* Check for loop timeout. Bad mclk? */
4836
ulTimeoutCounter++;
4837
if ( ulTimeoutCounter == cOCT6100_MAX_LOOP_CPU_TIMEOUT )
4838
return cOCT6100_ERR_FATAL_EA;
4839
4840
} while( usMclkDiff <= ulNumberOfCycleToWait );
4841
}
4842
4843
/* Back to normal mode. */
4844
WriteParams.ulWriteAddress = 0x50E;
4845
WriteParams.usWriteData = 0x0000;
4846
4847
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4848
if ( ulResult != cOCT6100_ERR_OK )
4849
return ulResult;
4850
4851
/* Check for CRC errors. */
4852
ReadParams.pusReadData = &usReadData;
4853
ReadParams.ulReadAddress = 0x202;
4854
4855
mOCT6100_DRIVER_READ_API( ReadParams, ulResult );
4856
if ( ulResult != cOCT6100_ERR_OK )
4857
return ulResult;
4858
4859
if ( (usReadData & 0x400) != 0x0000 )
4860
return cOCT6100_ERR_OPEN_CRC_ERROR;
4861
4862
/* Clear the error rol raised by manually moving the clocks. */
4863
WriteParams.ulWriteAddress = 0x502;
4864
WriteParams.usWriteData = 0x0002;
4865
4866
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult );
4867
if ( ulResult != cOCT6100_ERR_OK )
4868
return ulResult;
4869
4870
/*======================================================================*/
4871
/* Write the tail displacement value in external memory. */
4872
4873
ulFeatureBytesOffset = pSharedInfo->MemoryMap.PouchTailDisplOfst.usDwordOffset * 4;
4874
ulFeatureBitOffset = pSharedInfo->MemoryMap.PouchTailDisplOfst.byBitOffset;
4875
ulFeatureFieldLength = pSharedInfo->MemoryMap.PouchTailDisplOfst.byFieldSize;
4876
4877
ulResult = Oct6100ApiReadDword( f_pApiInstance,
4878
cOCT6100_POUCH_BASE + ulFeatureBytesOffset,
4879
&ulTempData );
4880
4881
/* Clear previous value set in the feature field.*/
4882
mOCT6100_CREATE_FEATURE_MASK( ulFeatureFieldLength, ulFeatureBitOffset, &ulMask );
4883
4884
ulTempData &= (~ulMask);
4885
4886
/* Set the tail displacement. */
4887
ulTempData |= (pSharedInfo->ChipConfig.usTailDisplacement << ulFeatureBitOffset );
4888
4889
/* Write the DWORD where the field is located. */
4890
ulResult = Oct6100ApiWriteDword( f_pApiInstance,
4891
cOCT6100_POUCH_BASE + ulFeatureBytesOffset,
4892
ulTempData );
4893
if ( ulResult != cOCT6100_ERR_OK )
4894
return ulResult;
4895
4896
/*======================================================================*/
4897
4898
4899
/*======================================================================*/
4900
/* Clear the pouch counter, if present. */
4901
4902
if ( pSharedInfo->DebugInfo.fPouchCounter == TRUE )
4903
{
4904
ulFeatureBytesOffset = pSharedInfo->MemoryMap.PouchCounterFieldOfst.usDwordOffset * 4;
4905
ulFeatureBitOffset = pSharedInfo->MemoryMap.PouchCounterFieldOfst.byBitOffset;
4906
ulFeatureFieldLength = pSharedInfo->MemoryMap.PouchCounterFieldOfst.byFieldSize;
4907
4908
ulResult = Oct6100ApiReadDword( f_pApiInstance,
4909
cOCT6100_POUCH_BASE + ulFeatureBytesOffset,
4910
&ulTempData );
4911
4912
/* Clear previous value set in the feature field.*/
4913
mOCT6100_CREATE_FEATURE_MASK( ulFeatureFieldLength, ulFeatureBitOffset, &ulMask );
4914
4915
/* Clear counter! */
4916
ulTempData &= (~ulMask);
4917
4918
/* Write the DWORD where the field is located.*/
4919
ulResult = Oct6100ApiWriteDword( f_pApiInstance,
4920
cOCT6100_POUCH_BASE + ulFeatureBytesOffset,
4921
ulTempData );
4922
if ( ulResult != cOCT6100_ERR_OK )
4923
return ulResult;
4924
}
4925
4926
/* The ISR has not yet been called. Set the appropriate bit in external memory. */
4927
if ( pSharedInfo->DebugInfo.fIsIsrCalledField == TRUE )
4928
{
4929
ulFeatureBytesOffset = pSharedInfo->MemoryMap.IsIsrCalledFieldOfst.usDwordOffset * 4;
4930
ulFeatureBitOffset = pSharedInfo->MemoryMap.IsIsrCalledFieldOfst.byBitOffset;
4931
ulFeatureFieldLength = pSharedInfo->MemoryMap.IsIsrCalledFieldOfst.byFieldSize;
4932
4933
ulResult = Oct6100ApiReadDword( f_pApiInstance,
4934
cOCT6100_POUCH_BASE + ulFeatureBytesOffset,
4935
&ulTempData );
4936
4937
/* Read previous value set in the feature field.*/
4938
mOCT6100_CREATE_FEATURE_MASK( ulFeatureFieldLength, ulFeatureBitOffset, &ulMask );
4939
4940
/* Toggle the bit to '1'. */
4941
ulTempData |= 1 << ulFeatureBitOffset;
4942
4943
/* Write the DWORD where the field is located.*/
4944
ulResult = Oct6100ApiWriteDword( f_pApiInstance,
4945
cOCT6100_POUCH_BASE + ulFeatureBytesOffset,
4946
ulTempData );
4947
if ( ulResult != cOCT6100_ERR_OK )
4948
return ulResult;
4949
}
4950
4951
/*======================================================================*/
4952
4953
return cOCT6100_ERR_OK;
4954
}
4955
#endif
4956
4957
4958
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
4959
4960
Function: Oct6100ApiInitToneInfo
4961
4962
Description: This function will parse the software image and retrieve
4963
the information about the tones that it supports.
4964
4965
-------------------------------------------------------------------------------
4966
| Argument | Description
4967
-------------------------------------------------------------------------------
4968
f_pApiInstance Pointer to API instance. This memory is used to keep the
4969
present state of the chip and all its resources.
4970
4971
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
4972
#if !SKIP_Oct6100ApiInitToneInfo
4973
UINT32 Oct6100ApiInitToneInfo(
4974
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
4975
{
4976
UINT32 ulResult;
4977
4978
PUINT8 pszToneInfoStart = NULL;
4979
PUINT8 pszToneInfoEnd = NULL;
4980
4981
PUINT8 pszCurrentInfo;
4982
PUINT8 pszNextInfo;
4983
4984
UINT32 ulToneEventNumber;
4985
UINT32 ulTempValue;
4986
UINT32 ulNumCharForValue;
4987
UINT32 ulUniqueToneId;
4988
UINT32 ulToneNameSize;
4989
UINT32 ulOffset = 0;
4990
4991
UINT32 i;
4992
4993
/* Init the tone detector parameter. */
4994
f_pApiInstance->pSharedInfo->ImageInfo.byNumToneDetectors = 0;
4995
4996
/* Find the start and the end of the tone info section. */
4997
if ( f_pApiInstance->pSharedInfo->ChipConfig.ulImageSize > 4096 )
4998
{
4999
/* For performance reasons, and since the tone detector information */
5000
/* is always located at the end of the image file, try to start from the end */
5001
/* of the buffer. */
5002
5003
ulOffset = f_pApiInstance->pSharedInfo->ChipConfig.ulImageSize - 2048;
5004
pszToneInfoStart = Oct6100ApiStrStr( f_pApiInstance->pSharedInfo->ChipConfig.pbyImageFile + ulOffset,
5005
(PUINT8)cOCT6100_TONE_INFO_START_STRING,
5006
f_pApiInstance->pSharedInfo->ChipConfig.pbyImageFile + f_pApiInstance->pSharedInfo->ChipConfig.ulImageSize );
5007
5008
/* Check if the information was found. */
5009
if ( pszToneInfoStart == NULL )
5010
{
5011
/* Try again, but giving a larger string to search. */
5012
ulOffset = f_pApiInstance->pSharedInfo->ChipConfig.ulImageSize - 4096;
5013
pszToneInfoStart = Oct6100ApiStrStr( f_pApiInstance->pSharedInfo->ChipConfig.pbyImageFile + ulOffset,
5014
(PUINT8)cOCT6100_TONE_INFO_START_STRING,
5015
f_pApiInstance->pSharedInfo->ChipConfig.pbyImageFile + f_pApiInstance->pSharedInfo->ChipConfig.ulImageSize );
5016
5017
}
5018
}
5019
5020
if ( pszToneInfoStart == NULL )
5021
{
5022
/* Travel through the whole file buffer. */
5023
pszToneInfoStart = Oct6100ApiStrStr( f_pApiInstance->pSharedInfo->ChipConfig.pbyImageFile,
5024
(PUINT8)cOCT6100_TONE_INFO_START_STRING,
5025
f_pApiInstance->pSharedInfo->ChipConfig.pbyImageFile + f_pApiInstance->pSharedInfo->ChipConfig.ulImageSize );
5026
}
5027
/* We have to return immediatly if no tones are found. */
5028
if ( pszToneInfoStart == NULL )
5029
return cOCT6100_ERR_OK;
5030
5031
/* The end of the tone detector information is after the beginning of the tone information. */
5032
pszToneInfoEnd = Oct6100ApiStrStr( pszToneInfoStart,
5033
(PUINT8)cOCT6100_TONE_INFO_STOP_STRING,
5034
f_pApiInstance->pSharedInfo->ChipConfig.pbyImageFile + f_pApiInstance->pSharedInfo->ChipConfig.ulImageSize );
5035
if ( pszToneInfoEnd == NULL )
5036
return cOCT6100_ERR_OPEN_TONE_INFO_STOP_TAG_NOT_FOUND;
5037
5038
/* Find and process all tone events within the region. */
5039
pszCurrentInfo = Oct6100ApiStrStr( pszToneInfoStart, (PUINT8)cOCT6100_TONE_INFO_EVENT_STRING, pszToneInfoEnd );
5040
5041
while ( pszCurrentInfo != NULL )
5042
{
5043
/* Skip the string. */
5044
pszCurrentInfo += ( Oct6100ApiStrLen( (PUINT8)cOCT6100_TONE_INFO_EVENT_STRING ) );
5045
5046
/* Extract the number of char used to represent the tone event number ( 1 or 2 ). */
5047
pszNextInfo = Oct6100ApiStrStr( pszCurrentInfo, (PUINT8)",", pszToneInfoEnd );
5048
ulNumCharForValue = (UINT32)( pszNextInfo - pszCurrentInfo );
5049
5050
/* Retreive the event number */
5051
ulToneEventNumber = 0;
5052
for ( i = ulNumCharForValue; i > 0; i-- )
5053
{
5054
ulResult = Oct6100ApiAsciiToHex( *pszCurrentInfo, &ulTempValue );
5055
if ( ulResult != cOCT6100_ERR_OK )
5056
return ulResult;
5057
5058
ulToneEventNumber |= ( ulTempValue << (( i - 1) * 4 ) );
5059
pszCurrentInfo++;
5060
}
5061
5062
if ( ulToneEventNumber >= cOCT6100_MAX_TONE_EVENT )
5063
return cOCT6100_ERR_OPEN_INVALID_TONE_EVENT;
5064
5065
/* Skip the comma and the 0x. */
5066
pszCurrentInfo += 3;
5067
5068
/*======================================================================*/
5069
/* Retreive the unique tone id. */
5070
ulUniqueToneId = 0;
5071
for ( i = 0; i < 8; i++ )
5072
{
5073
ulResult = Oct6100ApiAsciiToHex( *pszCurrentInfo, &ulTempValue );
5074
if ( ulResult != cOCT6100_ERR_OK )
5075
return ulResult;
5076
5077
ulOffset = 28 - ( i * 4 );
5078
ulUniqueToneId |= ( ulTempValue << ulOffset );
5079
pszCurrentInfo++;
5080
}
5081
5082
/*======================================================================*/
5083
5084
/* Skip the comma. */
5085
pszCurrentInfo++;
5086
5087
/* Find out where the next event info starts */
5088
pszNextInfo = Oct6100ApiStrStr( pszCurrentInfo,(PUINT8) cOCT6100_TONE_INFO_EVENT_STRING, pszToneInfoEnd );
5089
if ( pszNextInfo == NULL )
5090
pszNextInfo = pszToneInfoEnd;
5091
5092
/* Extract the name size. */
5093
ulToneNameSize = (UINT32)( pszNextInfo - pszCurrentInfo - 2 ); /* - 2 for 0x0D and 0x0A.*/
5094
5095
if ( ulToneNameSize > cOCT6100_TLV_MAX_TONE_NAME_SIZE )
5096
return cOCT6100_ERR_OPEN_INVALID_TONE_NAME;
5097
5098
/* Copy the tone name into the image info structure. */
5099
ulResult = Oct6100UserMemCopy( f_pApiInstance->pSharedInfo->ImageInfo.aToneInfo[ ulToneEventNumber ].aszToneName,
5100
pszCurrentInfo,
5101
ulToneNameSize );
5102
5103
5104
5105
/* Update the tone info into the image info structure. */
5106
f_pApiInstance->pSharedInfo->ImageInfo.aToneInfo[ ulToneEventNumber ].ulToneID = ulUniqueToneId;
5107
/* Find out the port on which this tone detector is associated. */
5108
switch( (ulUniqueToneId >> 28) & 0xF )
5109
{
5110
case 1:
5111
f_pApiInstance->pSharedInfo->ImageInfo.aToneInfo[ ulToneEventNumber ].ulDetectionPort = cOCT6100_CHANNEL_PORT_ROUT;
5112
break;
5113
5114
case 2:
5115
f_pApiInstance->pSharedInfo->ImageInfo.aToneInfo[ ulToneEventNumber ].ulDetectionPort = cOCT6100_CHANNEL_PORT_SIN;
5116
break;
5117
5118
case 4:
5119
f_pApiInstance->pSharedInfo->ImageInfo.aToneInfo[ ulToneEventNumber ].ulDetectionPort = cOCT6100_CHANNEL_PORT_SOUT;
5120
break;
5121
5122
case 5:
5123
f_pApiInstance->pSharedInfo->ImageInfo.aToneInfo[ ulToneEventNumber ].ulDetectionPort = cOCT6100_CHANNEL_PORT_ROUT_SOUT;
5124
break;
5125
5126
default:
5127
f_pApiInstance->pSharedInfo->ImageInfo.aToneInfo[ ulToneEventNumber ].ulDetectionPort = cOCT6100_INVALID_PORT;
5128
break;
5129
}
5130
5131
/* Find out where the next event info starts */
5132
pszNextInfo = Oct6100ApiStrStr( pszCurrentInfo,(PUINT8) cOCT6100_TONE_INFO_EVENT_STRING, pszToneInfoEnd );
5133
/* Update the current info pointer. */
5134
pszCurrentInfo = pszNextInfo;
5135
5136
f_pApiInstance->pSharedInfo->ImageInfo.byNumToneDetectors++;
5137
}
5138
5139
return cOCT6100_ERR_OK;
5140
}
5141
#endif
5142
5143
5144
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
5145
5146
Function: Oct6100ApiExternalMemoryBist
5147
5148
Description: Tests the functionality of the external memories.
5149
5150
-------------------------------------------------------------------------------
5151
| Argument | Description
5152
-------------------------------------------------------------------------------
5153
f_pApiInstance Pointer to API instance. This memory is used to keep the
5154
present state of the chip and all its resources.
5155
5156
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
5157
#if !SKIP_Oct6100ApiExternalMemoryBist
5158
UINT32 Oct6100ApiExternalMemoryBist(
5159
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
5160
{
5161
tPOCT6100_SHARED_INFO pSharedInfo;
5162
UINT32 ulMemSize = 0;
5163
UINT32 ulResult;
5164
5165
/* Get local pointer to shared portion of instance. */
5166
pSharedInfo = f_pApiInstance->pSharedInfo;
5167
5168
/* Test the external memory. */
5169
switch ( pSharedInfo->ChipConfig.ulMemoryChipSize )
5170
{
5171
case cOCT6100_MEMORY_CHIP_SIZE_8MB:
5172
ulMemSize = cOCT6100_SIZE_8M;
5173
break;
5174
case cOCT6100_MEMORY_CHIP_SIZE_16MB:
5175
ulMemSize = cOCT6100_SIZE_16M;
5176
break;
5177
case cOCT6100_MEMORY_CHIP_SIZE_32MB:
5178
ulMemSize = cOCT6100_SIZE_32M;
5179
break;
5180
case cOCT6100_MEMORY_CHIP_SIZE_64MB:
5181
ulMemSize = cOCT6100_SIZE_64M;
5182
break;
5183
case cOCT6100_MEMORY_CHIP_SIZE_128MB:
5184
ulMemSize = cOCT6100_SIZE_128M;
5185
break;
5186
default:
5187
return cOCT6100_ERR_FATAL_D9;
5188
}
5189
5190
ulMemSize *= pSharedInfo->ChipConfig.byNumMemoryChips;
5191
5192
ulResult = Oct6100ApiRandomMemoryWrite( f_pApiInstance, cOCT6100_EXTERNAL_MEM_BASE_ADDRESS, ulMemSize, 16, 1000, cOCT6100_ERR_OPEN_EXTERNAL_MEM_BIST_FAILED );
5193
if ( ulResult != cOCT6100_ERR_OK )
5194
return ulResult;
5195
5196
/* Make sure the user I/O functions are working as required. */
5197
ulResult = Oct6100ApiUserIoTest( f_pApiInstance );
5198
if ( ulResult != cOCT6100_ERR_OK )
5199
return ulResult;
5200
5201
return cOCT6100_ERR_OK;
5202
}
5203
#endif
5204
5205
5206
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
5207
5208
Function: Oct6100ApiGenerateNumber
5209
5210
Description: Generate a number using an index. Passing the same
5211
index generates the same number.
5212
5213
-------------------------------------------------------------------------------
5214
| Argument | Description
5215
-------------------------------------------------------------------------------
5216
f_pApiInstance Pointer to API instance. This memory is used to keep the
5217
present state of the chip and all its resources.
5218
f_ulIndex Index used to generate the random number.
5219
f_ulDataMask Data mask to apply to generated number.
5220
5221
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
5222
#if !SKIP_Oct6100ApiGenerateNumber
5223
UINT16 Oct6100ApiGenerateNumber(
5224
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance,
5225
IN UINT32 f_ulIndex,
5226
IN UINT32 f_ulDataMask )
5227
{
5228
UINT16 usGeneratedNumber;
5229
5230
usGeneratedNumber = (UINT16)( ( ( ~( f_ulIndex - 1 ) ) & 0xFF00 ) | ( ( f_ulIndex + 1 ) & 0xFF ) );
5231
5232
return (UINT16)( usGeneratedNumber & f_ulDataMask );
5233
}
5234
#endif
5235
5236
5237
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
5238
5239
Function: Oct6100ApiRandomMemoryWrite
5240
5241
Description: Writes to f_ulNumAccesses random locations in the indicated
5242
memory and read back to test the operation of that memory.
5243
5244
-------------------------------------------------------------------------------
5245
| Argument | Description
5246
-------------------------------------------------------------------------------
5247
f_pApiInstance Pointer to API instance. This memory is used to keep the
5248
present state of the chip and all its resources.
5249
f_ulMemBase Base address of the memory access.
5250
f_ulMemSize Size of the memory to be tested.
5251
f_ulNumDataBits Number of data bits.
5252
f_ulNumAccesses Number of random access to be perform.
5253
f_ulErrorCode Error code to be returned if the bist fails.
5254
5255
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
5256
#if !SKIP_Oct6100ApiRandomMemoryWrite
5257
UINT32 Oct6100ApiRandomMemoryWrite(
5258
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance,
5259
IN UINT32 f_ulMemBase,
5260
IN UINT32 f_ulMemSize,
5261
IN UINT32 f_ulNumDataBits,
5262
IN UINT32 f_ulNumAccesses,
5263
IN UINT32 f_ulErrorCode )
5264
{
5265
tPOCT6100_SHARED_INFO pSharedInfo;
5266
tOCT6100_WRITE_PARAMS WriteParams;
5267
tOCT6100_READ_PARAMS ReadParams;
5268
UINT32 ulDataMask;
5269
UINT32 ulResult, i, j;
5270
UINT32 ulBistAddress;
5271
UINT16 usReadData;
5272
5273
/* Get local pointer to shared portion of instance. */
5274
pSharedInfo = f_pApiInstance->pSharedInfo;
5275
5276
/* Set the process context and user chip ID parameters once and for all. */
5277
WriteParams.pProcessContext = f_pApiInstance->pProcessContext;
5278
5279
WriteParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
5280
5281
ReadParams.pProcessContext = f_pApiInstance->pProcessContext;
5282
5283
ReadParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
5284
5285
/* Make sure we don't perform more access then the size of our BIST resources. */
5286
if ( f_ulNumAccesses > 1024 )
5287
return cOCT6100_ERR_FATAL_C0;
5288
5289
/* Determine mask for number of data bits. */
5290
ulDataMask = (1 << f_ulNumDataBits) - 1;
5291
5292
/* Bist all data pin. */
5293
for ( i = 0; i < 32; i += 2 )
5294
{
5295
WriteParams.ulWriteAddress = f_ulMemBase + i * 2;
5296
WriteParams.usWriteData = (UINT16)(0x1 << (i / 2));
5297
5298
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
5299
if ( ulResult != cOCT6100_ERR_OK )
5300
return ulResult;
5301
5302
WriteParams.ulWriteAddress = f_ulMemBase + i * 2 + 2;
5303
WriteParams.usWriteData = (UINT16)(0x1 << (i / 2));
5304
5305
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
5306
if ( ulResult != cOCT6100_ERR_OK )
5307
return ulResult;
5308
}
5309
5310
/* Read back the data written. */
5311
for ( i = 0; i < 32; i += 2 )
5312
{
5313
ReadParams.ulReadAddress = f_ulMemBase + i * 2;
5314
ReadParams.pusReadData = &usReadData;
5315
mOCT6100_DRIVER_READ_API( ReadParams, ulResult )
5316
if ( ulResult != cOCT6100_ERR_OK )
5317
return ulResult;
5318
5319
if ( usReadData != (UINT16)(0x1 << (i / 2)) )
5320
return f_ulErrorCode;
5321
5322
ReadParams.ulReadAddress = f_ulMemBase + i * 2 + 2;
5323
ReadParams.pusReadData = &usReadData;
5324
mOCT6100_DRIVER_READ_API( ReadParams, ulResult )
5325
if ( ulResult != cOCT6100_ERR_OK )
5326
return ulResult;
5327
5328
if ( usReadData != (UINT16)(0x1 << (i / 2)) )
5329
return f_ulErrorCode;
5330
}
5331
5332
/* Perform the first write at address 0 + mem base */
5333
j = 0;
5334
WriteParams.ulWriteAddress = f_ulMemBase;
5335
WriteParams.usWriteData = Oct6100ApiGenerateNumber( f_pApiInstance, j, ulDataMask );
5336
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
5337
if ( ulResult != cOCT6100_ERR_OK )
5338
return ulResult;
5339
5340
/* Try each address line of the memory. */
5341
for ( i = 2, j = 1; i < f_ulMemSize; i <<= 1, j++ )
5342
{
5343
WriteParams.ulWriteAddress = ( f_ulMemBase + i );
5344
WriteParams.usWriteData = Oct6100ApiGenerateNumber( f_pApiInstance, j, ulDataMask );
5345
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
5346
if ( ulResult != cOCT6100_ERR_OK )
5347
return ulResult;
5348
}
5349
5350
for ( i = 0; i < j; i++ )
5351
{
5352
if ( i > 0 )
5353
ReadParams.ulReadAddress = ( f_ulMemBase + ( 0x1 << i ) );
5354
else
5355
ReadParams.ulReadAddress = f_ulMemBase;
5356
ReadParams.pusReadData = &usReadData;
5357
mOCT6100_DRIVER_READ_API( ReadParams, ulResult )
5358
if ( ulResult != cOCT6100_ERR_OK )
5359
return ulResult;
5360
5361
if ( usReadData != Oct6100ApiGenerateNumber( f_pApiInstance, i, ulDataMask ) )
5362
return f_ulErrorCode;
5363
}
5364
5365
/* Write to random addresses of the memory. */
5366
for ( i = 0; i < f_ulNumAccesses; i++ )
5367
{
5368
ulBistAddress = (UINT16)Oct6100ApiGenerateNumber( f_pApiInstance, i, 0xFFFF ) << 16;
5369
ulBistAddress |= (UINT16)Oct6100ApiGenerateNumber( f_pApiInstance, i, 0xFFFF );
5370
ulBistAddress &= f_ulMemSize - 2;
5371
ulBistAddress |= f_ulMemBase;
5372
5373
WriteParams.ulWriteAddress = ulBistAddress;
5374
WriteParams.usWriteData = Oct6100ApiGenerateNumber( f_pApiInstance, i, 0xFFFF );
5375
mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult )
5376
if ( ulResult != cOCT6100_ERR_OK )
5377
return ulResult;
5378
}
5379
5380
for ( i = 0; i < f_ulNumAccesses; i++ )
5381
{
5382
ulBistAddress = (UINT16)Oct6100ApiGenerateNumber( f_pApiInstance, i, 0xFFFF ) << 16;
5383
ulBistAddress |= (UINT16)Oct6100ApiGenerateNumber( f_pApiInstance, i, 0xFFFF );
5384
ulBistAddress &= f_ulMemSize - 2;
5385
ulBistAddress |= f_ulMemBase;
5386
5387
ReadParams.ulReadAddress = ulBistAddress;
5388
ReadParams.pusReadData = &usReadData;
5389
mOCT6100_DRIVER_READ_API( ReadParams, ulResult )
5390
if ( ulResult != cOCT6100_ERR_OK )
5391
return ulResult;
5392
5393
if ( ( usReadData & ulDataMask ) != ( Oct6100ApiGenerateNumber( f_pApiInstance, i, 0xFFFF ) & ulDataMask ) )
5394
return f_ulErrorCode;
5395
}
5396
5397
return cOCT6100_ERR_OK;
5398
}
5399
#endif
5400
5401
5402
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
5403
5404
Function: Oct6100ApiUserIoTest
5405
5406
Description: This function will verify the correct functionality of
5407
the following user functions:
5408
5409
- Oct6100UserDriverWriteBurstApi
5410
- Oct6100UserDriverWriteSmearApi
5411
- Oct6100UserDriverReadBurstApi
5412
5413
The Oct6100UserDriverWriteApi and Oct6100UserDriverReadApi
5414
functions do not need to be tested here as this has be done in
5415
the external memory bisting function above.
5416
5417
-------------------------------------------------------------------------------
5418
| Argument | Description
5419
-------------------------------------------------------------------------------
5420
f_pApiInstance Pointer to API instance. This memory is used to keep the
5421
present state of the chip and all its resources.
5422
5423
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
5424
#if !SKIP_Oct6100ApiUserIoTest
5425
UINT32 Oct6100ApiUserIoTest(
5426
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
5427
{
5428
tPOCT6100_SHARED_INFO pSharedInfo;
5429
tOCT6100_WRITE_BURST_PARAMS WriteBurstParams;
5430
tOCT6100_WRITE_SMEAR_PARAMS WriteSmearParams;
5431
tOCT6100_READ_PARAMS ReadParams;
5432
tOCT6100_READ_BURST_PARAMS ReadBurstParams;
5433
UINT32 ulResult, i;
5434
UINT16 usReadData;
5435
5436
/* Get local pointer to shared portion of instance. */
5437
pSharedInfo = f_pApiInstance->pSharedInfo;
5438
5439
/* Set the process context and user chip ID parameters once and for all. */
5440
WriteBurstParams.pProcessContext = f_pApiInstance->pProcessContext;
5441
5442
WriteBurstParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
5443
/* Test what the user has specified is the maximum that can be used for a burst. */
5444
WriteBurstParams.ulWriteLength = pSharedInfo->ChipConfig.usMaxRwAccesses;
5445
WriteBurstParams.pusWriteData = pSharedInfo->MiscVars.ausSuperArray;
5446
5447
WriteSmearParams.pProcessContext = f_pApiInstance->pProcessContext;
5448
5449
WriteSmearParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
5450
/* Test what the user has specified is the maximum that can be used for a smear. */
5451
WriteSmearParams.ulWriteLength = pSharedInfo->ChipConfig.usMaxRwAccesses;
5452
5453
ReadParams.pProcessContext = f_pApiInstance->pProcessContext;
5454
5455
ReadParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
5456
ReadParams.pusReadData = &usReadData;
5457
5458
ReadBurstParams.pProcessContext = f_pApiInstance->pProcessContext;
5459
5460
ReadBurstParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
5461
/* Test what the user has specified is the maximum that can be used for a burst. */
5462
ReadBurstParams.ulReadLength = pSharedInfo->ChipConfig.usMaxRwAccesses;
5463
ReadBurstParams.pusReadData = pSharedInfo->MiscVars.ausSuperArray;
5464
5465
5466
/*======================================================================*/
5467
/* Write burst check. */
5468
5469
WriteBurstParams.ulWriteAddress = cOCT6100_EXTERNAL_MEM_BASE_ADDRESS;
5470
/* Set the random data to be written. */
5471
for ( i = 0; i < WriteBurstParams.ulWriteLength; i++ )
5472
{
5473
WriteBurstParams.pusWriteData[ i ] = Oct6100ApiGenerateNumber( f_pApiInstance, i, 0xFFFF );
5474
}
5475
mOCT6100_DRIVER_WRITE_BURST_API( WriteBurstParams, ulResult )
5476
if ( ulResult != cOCT6100_ERR_OK )
5477
return ulResult;
5478
5479
/* Read back pattern using simple read function and make sure we are reading what's expected. */
5480
ReadParams.ulReadAddress = WriteBurstParams.ulWriteAddress;
5481
for ( i = 0; i < WriteBurstParams.ulWriteLength; i++ )
5482
{
5483
mOCT6100_DRIVER_READ_API( ReadParams, ulResult )
5484
if ( ulResult != cOCT6100_ERR_OK )
5485
return ulResult;
5486
5487
/* Check if the data matches. */
5488
if ( usReadData != WriteBurstParams.pusWriteData[ i ] )
5489
{
5490
/* The values do not match. Something seems to be wrong with the WriteBurst user function. */
5491
return cOCT6100_ERR_OPEN_USER_WRITE_BURST_FAILED;
5492
}
5493
5494
/* Next address to check. */
5495
ReadParams.ulReadAddress += 2;
5496
}
5497
5498
/*======================================================================*/
5499
5500
5501
/*======================================================================*/
5502
/* Write smear check. */
5503
5504
WriteSmearParams.ulWriteAddress = cOCT6100_EXTERNAL_MEM_BASE_ADDRESS + ( WriteBurstParams.ulWriteLength * 2 );
5505
/* Set the random data to be written. */
5506
WriteSmearParams.usWriteData = Oct6100ApiGenerateNumber( f_pApiInstance, Oct6100ApiRand( 0xFFFF ), 0xFFFF );
5507
mOCT6100_DRIVER_WRITE_SMEAR_API( WriteSmearParams, ulResult )
5508
if ( ulResult != cOCT6100_ERR_OK )
5509
return ulResult;
5510
5511
/* Read back pattern using simple read function and make sure we are reading what's expected. */
5512
ReadParams.ulReadAddress = WriteSmearParams.ulWriteAddress;
5513
for ( i = 0; i < WriteSmearParams.ulWriteLength; i++ )
5514
{
5515
mOCT6100_DRIVER_READ_API( ReadParams, ulResult )
5516
if ( ulResult != cOCT6100_ERR_OK )
5517
return ulResult;
5518
5519
/* Check if the data matches. */
5520
if ( usReadData != WriteSmearParams.usWriteData )
5521
{
5522
/* The values do not match. Something seems to be wrong with the WriteSmear user function. */
5523
return cOCT6100_ERR_OPEN_USER_WRITE_SMEAR_FAILED;
5524
}
5525
5526
/* Next address to check. */
5527
ReadParams.ulReadAddress += 2;
5528
}
5529
5530
/*======================================================================*/
5531
5532
5533
/*======================================================================*/
5534
/* Read burst check. */
5535
5536
/* First check with what the WriteBurst function wrote. */
5537
ReadBurstParams.ulReadAddress = WriteBurstParams.ulWriteAddress;
5538
mOCT6100_DRIVER_READ_BURST_API( ReadBurstParams, ulResult )
5539
if ( ulResult != cOCT6100_ERR_OK )
5540
return ulResult;
5541
5542
for ( i = 0; i < ReadBurstParams.ulReadLength; i++ )
5543
{
5544
/* Check if the data matches. */
5545
if ( ReadBurstParams.pusReadData[ i ] != Oct6100ApiGenerateNumber( f_pApiInstance, i, 0xFFFF ) )
5546
{
5547
/* The values do not match. Something seems to be wrong with the ReadBurst user function. */
5548
return cOCT6100_ERR_OPEN_USER_READ_BURST_FAILED;
5549
}
5550
}
5551
5552
/* Then check with what the WriteSmear function wrote. */
5553
ReadBurstParams.ulReadAddress = WriteSmearParams.ulWriteAddress;
5554
mOCT6100_DRIVER_READ_BURST_API( ReadBurstParams, ulResult )
5555
if ( ulResult != cOCT6100_ERR_OK )
5556
return ulResult;
5557
5558
for ( i = 0; i < ReadBurstParams.ulReadLength; i++ )
5559
{
5560
/* Check if the data matches. */
5561
if ( ReadBurstParams.pusReadData[ i ] != WriteSmearParams.usWriteData )
5562
{
5563
/* The values do not match. Something seems to be wrong with the ReadBurst user function. */
5564
return cOCT6100_ERR_OPEN_USER_READ_BURST_FAILED;
5565
}
5566
}
5567
5568
/*======================================================================*/
5569
5570
return cOCT6100_ERR_OK;
5571
}
5572
#endif
5573
5574
5575
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
5576
5577
Function: Oct6100ApiExternalMemoryInit
5578
5579
Description: Initialize the external memory before uploading the image.
5580
5581
-------------------------------------------------------------------------------
5582
| Argument | Description
5583
-------------------------------------------------------------------------------
5584
f_pApiInstance Pointer to API instance. This memory is used to keep the
5585
present state of the chip and all its resources.
5586
5587
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
5588
#if !SKIP_Oct6100ApiExternalMemoryInit
5589
UINT32 Oct6100ApiExternalMemoryInit(
5590
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
5591
{
5592
tPOCT6100_SHARED_INFO pSharedInfo;
5593
tOCT6100_WRITE_SMEAR_PARAMS SmearParams;
5594
UINT32 ulTotalWordToWrite;
5595
UINT32 ulResult;
5596
5597
/* Get local pointer to shared portion of instance. */
5598
pSharedInfo = f_pApiInstance->pSharedInfo;
5599
5600
SmearParams.pProcessContext = f_pApiInstance->pProcessContext;
5601
5602
SmearParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId;
5603
5604
/* Clear the first part of the memory. */
5605
ulTotalWordToWrite = 0x400;
5606
SmearParams.ulWriteAddress = cOCT6100_EXTERNAL_MEM_BASE_ADDRESS;
5607
5608
while ( ulTotalWordToWrite != 0 )
5609
{
5610
if ( ulTotalWordToWrite >= pSharedInfo->ChipConfig.usMaxRwAccesses )
5611
SmearParams.ulWriteLength = pSharedInfo->ChipConfig.usMaxRwAccesses;
5612
else
5613
SmearParams.ulWriteLength = ulTotalWordToWrite;
5614
5615
SmearParams.usWriteData = 0x0;
5616
5617
mOCT6100_DRIVER_WRITE_SMEAR_API( SmearParams, ulResult );
5618
if ( ulResult != cOCT6100_ERR_OK )
5619
return ulResult;
5620
5621
/* Update the number of words to write. */
5622
ulTotalWordToWrite -= SmearParams.ulWriteLength;
5623
/* Update the address. */
5624
SmearParams.ulWriteAddress += ( SmearParams.ulWriteLength * 2 );
5625
}
5626
5627
/* Clear the TLV flag.*/
5628
ulResult = Oct6100ApiWriteDword( f_pApiInstance, cOCT6100_TLV_BASE, 0x0 );
5629
if ( ulResult != cOCT6100_ERR_OK )
5630
return ulResult;
5631
5632
return cOCT6100_ERR_OK;
5633
}
5634
#endif
5635
5636
5637
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
5638
5639
Function: Oct6100ApiInitMixer
5640
5641
Description: This function will initialize the mixer memory.
5642
5643
-------------------------------------------------------------------------------
5644
| Argument | Description
5645
-------------------------------------------------------------------------------
5646
f_pApiInstance Pointer to API instance. This memory is used to keep the
5647
present state of the chip and all its resources.
5648
5649
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
5650
#if !SKIP_Oct6100ApiInitMixer
5651
UINT32 Oct6100ApiInitMixer(
5652
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
5653
{
5654
tPOCT6100_SHARED_INFO pSharedInfo;
5655
tOCT6100_WRITE_BURST_PARAMS BurstParams;
5656
UINT16 ausWriteData[ 4 ];
5657
UINT32 ulResult;
5658
5659
pSharedInfo = f_pApiInstance->pSharedInfo;
5660
5661
BurstParams.pProcessContext = f_pApiInstance->pProcessContext;
5662
5663
BurstParams.ulUserChipId = f_pApiInstance->pSharedInfo->ChipConfig.ulUserChipId;
5664
BurstParams.pusWriteData = ausWriteData;
5665
/*======================================================================*/
5666
/* Initialize the mixer memory if required. */
5667
if ( pSharedInfo->ChipConfig.fEnableChannelRecording == TRUE )
5668
{
5669
/* Modify the mixer pointer by adding the record event into the link list. */
5670
pSharedInfo->MixerInfo.usFirstSinCopyEventPtr = pSharedInfo->MixerInfo.usRecordSinEventIndex;
5671
pSharedInfo->MixerInfo.usLastSinCopyEventPtr = pSharedInfo->MixerInfo.usRecordSinEventIndex;
5672
pSharedInfo->MixerInfo.usFirstSoutCopyEventPtr = pSharedInfo->MixerInfo.usRecordCopyEventIndex;
5673
pSharedInfo->MixerInfo.usLastSoutCopyEventPtr = pSharedInfo->MixerInfo.usRecordCopyEventIndex;
5674
5675
/* Program the Sin copy event. */
5676
BurstParams.ulWriteAddress = cOCT6100_MIXER_CONTROL_MEM_BASE + ( pSharedInfo->MixerInfo.usRecordSinEventIndex * cOCT6100_MIXER_CONTROL_MEM_ENTRY_SIZE );
5677
BurstParams.ulWriteLength = 4;
5678
5679
ausWriteData[ 0 ] = 0x0000;
5680
ausWriteData[ 1 ] = 0x0000;
5681
ausWriteData[ 2 ] = (UINT16)(cOCT6100_MIXER_TAIL_NODE & 0x7FF); /* Head node.*/
5682
ausWriteData[ 3 ] = 0x0000;
5683
5684
mOCT6100_DRIVER_WRITE_BURST_API( BurstParams, ulResult );
5685
if ( ulResult != cOCT6100_ERR_OK )
5686
return ulResult;
5687
5688
/* Program the Sout copy event. */
5689
BurstParams.ulWriteAddress = cOCT6100_MIXER_CONTROL_MEM_BASE + ( pSharedInfo->MixerInfo.usRecordCopyEventIndex * cOCT6100_MIXER_CONTROL_MEM_ENTRY_SIZE );
5690
BurstParams.ulWriteLength = 4;
5691
5692
ausWriteData[ 0 ] = 0x0000;
5693
ausWriteData[ 1 ] = 0x0000;
5694
ausWriteData[ 2 ] = (UINT16)(pSharedInfo->MixerInfo.usRecordSinEventIndex & 0x7FF);
5695
ausWriteData[ 3 ] = 0x0000;
5696
5697
mOCT6100_DRIVER_WRITE_BURST_API( BurstParams, ulResult );
5698
if ( ulResult != cOCT6100_ERR_OK )
5699
return ulResult;
5700
5701
/* Configure the head node. */
5702
BurstParams.ulWriteAddress = cOCT6100_MIXER_CONTROL_MEM_BASE;
5703
BurstParams.ulWriteLength = 4;
5704
5705
ausWriteData[ 0 ] = 0x0000;
5706
ausWriteData[ 1 ] = 0x0000;
5707
ausWriteData[ 2 ] = (UINT16)(pSharedInfo->MixerInfo.usRecordCopyEventIndex & 0x7FF);
5708
ausWriteData[ 3 ] = 0x0000;
5709
5710
mOCT6100_DRIVER_WRITE_BURST_API( BurstParams, ulResult );
5711
if ( ulResult != cOCT6100_ERR_OK )
5712
return ulResult;
5713
5714
/* Init the mixer pointer */
5715
pSharedInfo->MixerInfo.usFirstSinCopyEventPtr = pSharedInfo->MixerInfo.usRecordSinEventIndex;
5716
}
5717
else
5718
{
5719
/* Configure the head node. */
5720
BurstParams.ulWriteAddress = cOCT6100_MIXER_CONTROL_MEM_BASE;
5721
BurstParams.ulWriteLength = 4;
5722
5723
ausWriteData[ 0 ] = 0x0000;
5724
ausWriteData[ 1 ] = 0x0000;
5725
ausWriteData[ 2 ] = (UINT16)(cOCT6100_MIXER_TAIL_NODE & 0x7FF); /* Head node. */
5726
ausWriteData[ 3 ] = 0x0000;
5727
5728
mOCT6100_DRIVER_WRITE_BURST_API( BurstParams, ulResult );
5729
if ( ulResult != cOCT6100_ERR_OK )
5730
return ulResult;
5731
5732
/* Configure the tail node. */
5733
BurstParams.ulWriteAddress = cOCT6100_MIXER_CONTROL_MEM_BASE + 0x10;
5734
BurstParams.ulWriteLength = 4;
5735
5736
ausWriteData[ 0 ] = 0x0000;
5737
ausWriteData[ 1 ] = 0x0000;
5738
ausWriteData[ 2 ] = (UINT16)(cOCT6100_MIXER_HEAD_NODE & 0x7FF); /* Head node. */
5739
ausWriteData[ 3 ] = 0x0000;
5740
5741
mOCT6100_DRIVER_WRITE_BURST_API( BurstParams, ulResult );
5742
if ( ulResult != cOCT6100_ERR_OK )
5743
return ulResult;
5744
}
5745
5746
return cOCT6100_ERR_OK;
5747
}
5748
#endif
5749
5750
5751
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
5752
5753
Function: Oct6100ApiInitRecordResources
5754
5755
Description: This function will initialize the resources required to
5756
perform recording on a debug channel.
5757
5758
-------------------------------------------------------------------------------
5759
| Argument | Description
5760
-------------------------------------------------------------------------------
5761
f_pApiInstance Pointer to API instance. This memory is used to keep the
5762
present state of the chip and all its resources.
5763
5764
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
5765
#if !SKIP_Oct6100ApiInitRecordResources
5766
UINT32 Oct6100ApiInitRecordResources(
5767
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance )
5768
{
5769
tPOCT6100_SHARED_INFO pSharedInfo;
5770
UINT32 ulResult;
5771
5772
pSharedInfo = f_pApiInstance->pSharedInfo;
5773
5774
/* Check if recording is enabled. */
5775
if ( pSharedInfo->ChipConfig.fEnableChannelRecording == FALSE )
5776
return cOCT6100_ERR_OK;
5777
5778
if ( pSharedInfo->DebugInfo.usRecordMemIndex == cOCT6100_INVALID_INDEX )
5779
return cOCT6100_ERR_NOT_SUPPORTED_OPEN_DEBUG_RECORD;
5780
5781
/* Check the provided recording memory index within the SSPX. */
5782
if ( pSharedInfo->DebugInfo.usRecordMemIndex != ( pSharedInfo->ImageInfo.usMaxNumberOfChannels - 1 ) )
5783
return cOCT6100_ERR_OPEN_DEBUG_MEM_INDEX;
5784
5785
/* Reserve the TSI entries for the channel. */
5786
ulResult = Oct6100ApiReserveTsiMemEntry( f_pApiInstance, &pSharedInfo->DebugInfo.usRecordRinRoutTsiMemIndex );
5787
if ( ulResult != cOCT6100_ERR_OK )
5788
return ulResult;
5789
5790
ulResult = Oct6100ApiReserveTsiMemEntry( f_pApiInstance, &pSharedInfo->DebugInfo.usRecordSinSoutTsiMemIndex );
5791
if ( ulResult != cOCT6100_ERR_OK )
5792
return ulResult;
5793
5794
/* Open the debug channel. */
5795
ulResult = Oct6100ApiDebugChannelOpen( f_pApiInstance );
5796
if ( ulResult != cOCT6100_ERR_OK )
5797
return ulResult;
5798
5799
return cOCT6100_ERR_OK;
5800
}
5801
#endif
5802
5803
5804
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
5805
5806
Function: Oct6100FreeResourcesSer
5807
5808
Description: This function closes all opened channels and frees all
5809
specified global resources used by the chip.
5810
5811
-------------------------------------------------------------------------------
5812
| Argument | Description
5813
-------------------------------------------------------------------------------
5814
f_pApiInstance Pointer to API instance. This memory is used to keep
5815
the present state of the chip and all its resources.
5816
5817
f_pFreeResources Pointer to user structure in which to choose what
5818
to free.
5819
5820
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
5821
#if !SKIP_Oct6100FreeResourcesSer
5822
UINT32 Oct6100FreeResourcesSer(
5823
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance,
5824
IN tPOCT6100_FREE_RESOURCES f_pFreeResources )
5825
{
5826
tPOCT6100_SHARED_INFO pSharedInfo;
5827
tPOCT6100_API_CHANNEL pChanEntry;
5828
5829
UINT32 ulResult;
5830
UINT32 i;
5831
5832
/* Obtain local pointer to shared portion of instance. */
5833
pSharedInfo = f_pApiInstance->pSharedInfo;
5834
5835
/* Close all bidirectional channels. */
5836
for ( i = 0; i < pSharedInfo->ChipConfig.usMaxBiDirChannels; i ++ )
5837
{
5838
tPOCT6100_API_BIDIR_CHANNEL pBiDirChanEntry;
5839
5840
mOCT6100_GET_BIDIR_CHANNEL_ENTRY_PNT( pSharedInfo, pBiDirChanEntry, i );
5841
5842
if ( pBiDirChanEntry->fReserved == TRUE )
5843
{
5844
tOCT6100_CHANNEL_DESTROY_BIDIR DestroyBidir;
5845
5846
Oct6100ChannelDestroyBiDirDef( &DestroyBidir );
5847
5848
DestroyBidir.ulBiDirChannelHndl = cOCT6100_HNDL_TAG_BIDIR_CHANNEL | (pBiDirChanEntry->byEntryOpenCnt << cOCT6100_ENTRY_OPEN_CNT_SHIFT) | i;
5849
5850
ulResult = Oct6100ChannelDestroyBiDirSer( f_pApiInstance, &DestroyBidir );
5851
if ( ulResult != cOCT6100_ERR_OK )
5852
return ulResult;
5853
}
5854
}
5855
5856
/* Close all bridge participants. */
5857
for ( i = 0; i < pSharedInfo->ChipConfig.usMaxChannels; i ++ )
5858
{
5859
mOCT6100_GET_CHANNEL_ENTRY_PNT( pSharedInfo, pChanEntry, i );
5860
if ( pChanEntry->fReserved == TRUE && pChanEntry->usBridgeIndex != cOCT6100_INVALID_INDEX )
5861
{
5862
/* This channel is on a bridge. */
5863
tOCT6100_CONF_BRIDGE_CHAN_REMOVE BridgeChanRemove;
5864
tPOCT6100_API_CONF_BRIDGE pBridgeEntry;
5865
5866
Oct6100ConfBridgeChanRemoveDef( &BridgeChanRemove );
5867
5868
/* Obtain a pointer to the conference bridge's list entry. */
5869
mOCT6100_GET_CONF_BRIDGE_ENTRY_PNT( f_pApiInstance->pSharedInfo, pBridgeEntry, pChanEntry->usBridgeIndex );
5870
5871
BridgeChanRemove.fRemoveAll = TRUE;
5872
BridgeChanRemove.ulConfBridgeHndl = cOCT6100_HNDL_TAG_CONF_BRIDGE | (pBridgeEntry->byEntryOpenCnt << cOCT6100_ENTRY_OPEN_CNT_SHIFT) | pChanEntry->usBridgeIndex;
5873
5874
ulResult = Oct6100ConfBridgeChanRemoveSer( f_pApiInstance, &BridgeChanRemove );
5875
if ( ulResult != cOCT6100_ERR_OK )
5876
return ulResult;
5877
}
5878
}
5879
5880
/* Close all opened channels. This will bring the broadcast TSSTs with it. */
5881
for ( i = 0; i < pSharedInfo->ChipConfig.usMaxChannels; i ++ )
5882
{
5883
mOCT6100_GET_CHANNEL_ENTRY_PNT( pSharedInfo, pChanEntry, i );
5884
5885
if ( pChanEntry->fReserved == TRUE )
5886
{
5887
tOCT6100_CHANNEL_CLOSE ChannelClose;
5888
5889
/* Generate handle. */
5890
ChannelClose.ulChannelHndl = cOCT6100_HNDL_TAG_CHANNEL | (pChanEntry->byEntryOpenCnt << cOCT6100_ENTRY_OPEN_CNT_SHIFT) | i;
5891
5892
/* Call serialized close channel function. */
5893
ulResult = Oct6100ChannelCloseSer( f_pApiInstance, &ChannelClose );
5894
if ( ulResult != cOCT6100_ERR_OK )
5895
return ulResult;
5896
}
5897
}
5898
5899
/* Close all TSI connections. */
5900
if ( f_pFreeResources->fFreeTsiConnections == TRUE )
5901
{
5902
tPOCT6100_API_TSI_CNCT pTsiCnct;
5903
tOCT6100_TSI_CNCT_CLOSE TsiCnctClose;
5904
5905
Oct6100TsiCnctCloseDef( &TsiCnctClose );
5906
5907
for ( i = 0; i < pSharedInfo->ChipConfig.usMaxTsiCncts; i ++ )
5908
{
5909
/* Obtain a pointer to the TSI connection list entry. */
5910
mOCT6100_GET_TSI_CNCT_ENTRY_PNT( f_pApiInstance->pSharedInfo, pTsiCnct, i );
5911
5912
if ( pTsiCnct->fReserved == TRUE )
5913
{
5914
TsiCnctClose.ulTsiCnctHndl = cOCT6100_HNDL_TAG_TSI_CNCT | (pTsiCnct->byEntryOpenCnt << cOCT6100_ENTRY_OPEN_CNT_SHIFT) | i;
5915
5916
ulResult = Oct6100TsiCnctCloseSer( f_pApiInstance, &TsiCnctClose );
5917
if ( ulResult != cOCT6100_ERR_OK )
5918
return ulResult;
5919
}
5920
}
5921
}
5922
5923
/* Close all conference bridges. */
5924
if ( f_pFreeResources->fFreeConferenceBridges == TRUE )
5925
{
5926
tPOCT6100_API_CONF_BRIDGE pConfBridge;
5927
tOCT6100_CONF_BRIDGE_CLOSE ConfBridgeClose;
5928
5929
Oct6100ConfBridgeCloseDef( &ConfBridgeClose );
5930
5931
for ( i = 0; i < pSharedInfo->ChipConfig.usMaxConfBridges; i ++ )
5932
{
5933
/* Obtain a pointer to the conference bridge's list entry. */
5934
mOCT6100_GET_CONF_BRIDGE_ENTRY_PNT( f_pApiInstance->pSharedInfo, pConfBridge, i );
5935
5936
if ( pConfBridge->fReserved == TRUE )
5937
{
5938
ConfBridgeClose.ulConfBridgeHndl = cOCT6100_HNDL_TAG_CONF_BRIDGE | (pConfBridge->byEntryOpenCnt << cOCT6100_ENTRY_OPEN_CNT_SHIFT) | i;
5939
5940
ulResult = Oct6100ConfBridgeCloseSer( f_pApiInstance, &ConfBridgeClose );
5941
if ( ulResult != cOCT6100_ERR_OK )
5942
return ulResult;
5943
}
5944
}
5945
}
5946
5947
/* Free all playout buffers loaded in external memory. */
5948
if ( f_pFreeResources->fFreePlayoutBuffers == TRUE )
5949
{
5950
tPOCT6100_API_BUFFER pBuffer;
5951
tOCT6100_BUFFER_UNLOAD BufferUnload;
5952
5953
Oct6100BufferPlayoutUnloadDef( &BufferUnload );
5954
5955
for ( i = 0; i < pSharedInfo->ChipConfig.usMaxPlayoutBuffers; i ++ )
5956
{
5957
5958
5959
/* Obtain a pointer to the buffer list entry. */
5960
mOCT6100_GET_BUFFER_ENTRY_PNT( f_pApiInstance->pSharedInfo, pBuffer, i );
5961
5962
if ( pBuffer->fReserved == TRUE )
5963
{
5964
BufferUnload.ulBufferIndex = i;
5965
ulResult = Oct6100BufferUnloadSer( f_pApiInstance, &BufferUnload, TRUE );
5966
if ( ulResult != cOCT6100_ERR_OK )
5967
return ulResult;
5968
}
5969
}
5970
}
5971
5972
5973
/* Close all phasing TSSTs. */
5974
if ( f_pFreeResources->fFreePhasingTssts == TRUE )
5975
{
5976
tPOCT6100_API_PHASING_TSST pPhasingTsst;
5977
tOCT6100_PHASING_TSST_CLOSE PhasingTsstClose;
5978
5979
Oct6100PhasingTsstCloseDef( &PhasingTsstClose );
5980
5981
for ( i = 0; i < pSharedInfo->ChipConfig.usMaxPhasingTssts; i ++ )
5982
{
5983
mOCT6100_GET_PHASING_TSST_ENTRY_PNT( pSharedInfo, pPhasingTsst, i );
5984
5985
if ( pPhasingTsst->fReserved == TRUE )
5986
{
5987
PhasingTsstClose.ulPhasingTsstHndl = cOCT6100_HNDL_TAG_PHASING_TSST | (pPhasingTsst->byEntryOpenCnt << cOCT6100_ENTRY_OPEN_CNT_SHIFT) | i;
5988
5989
ulResult = Oct6100PhasingTsstCloseSer( f_pApiInstance, &PhasingTsstClose );
5990
if ( ulResult != cOCT6100_ERR_OK )
5991
return ulResult;
5992
}
5993
}
5994
}
5995
5996
/* Close all ADPCM channels. */
5997
if ( f_pFreeResources->fFreeAdpcmChannels == TRUE )
5998
{
5999
tPOCT6100_API_ADPCM_CHAN pAdpcmChannel;
6000
tOCT6100_ADPCM_CHAN_CLOSE AdpcmChanClose;
6001
6002
Oct6100AdpcmChanCloseDef( &AdpcmChanClose );
6003
6004
for ( i = 0; i < pSharedInfo->ChipConfig.usMaxAdpcmChannels; i ++ )
6005
{
6006
mOCT6100_GET_ADPCM_CHAN_ENTRY_PNT( pSharedInfo, pAdpcmChannel, i );
6007
if ( pAdpcmChannel->fReserved == TRUE )
6008
{
6009
AdpcmChanClose.ulChanHndl = cOCT6100_HNDL_TAG_ADPCM_CHANNEL | (pAdpcmChannel->byEntryOpenCnt << cOCT6100_ENTRY_OPEN_CNT_SHIFT) | i;
6010
6011
ulResult = Oct6100AdpcmChanCloseSer( f_pApiInstance, &AdpcmChanClose );
6012
if ( ulResult != cOCT6100_ERR_OK )
6013
return ulResult;
6014
}
6015
}
6016
}
6017
6018
6019
return cOCT6100_ERR_OK;
6020
}
6021
#endif
6022
6023
6024
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
6025
6026
Function: Oct6100ProductionBistSer
6027
6028
Description: This function returns the instantaneous production BIST status.
6029
6030
-------------------------------------------------------------------------------
6031
| Argument | Description
6032
-------------------------------------------------------------------------------
6033
f_pApiInstance Pointer to API instance. This memory is used to keep
6034
the present state of the chip and all its resources.
6035
6036
f_pProductionBist Pointer to user structure in which BIST status will
6037
be returned.
6038
6039
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
6040
#if !SKIP_Oct6100ProductionBistSer
6041
UINT32 Oct6100ProductionBistSer(
6042
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance,
6043
IN OUT tPOCT6100_PRODUCTION_BIST f_pProductionBist )
6044
{
6045
UINT32 ulCalculatedCrc = cOCT6100_INVALID_VALUE;
6046
UINT32 ulResult;
6047
UINT32 ulLoopCnt = 0x0;
6048
UINT32 i = 1;
6049
UINT32 ulTotalElements = 4;
6050
UINT32 ulReadAddress = cOCT6100_POUCH_BASE;
6051
UINT32 aulMessage[ 5 ];
6052
6053
/* Check if the production bist has been activated. */
6054
if ( f_pApiInstance->pSharedInfo->ChipConfig.fEnableProductionBist == FALSE )
6055
return cOCT6100_ERR_PRODUCTION_BIST_DISABLED;
6056
6057
f_pProductionBist->ulCurrentAddress = cOCT6100_INVALID_VALUE;
6058
f_pProductionBist->ulCurrentLoop = cOCT6100_INVALID_VALUE;
6059
f_pProductionBist->ulCurrentTest = cOCT6100_INVALID_VALUE;
6060
f_pProductionBist->ulFailedAddress = cOCT6100_INVALID_VALUE;
6061
f_pProductionBist->ulReadValue = cOCT6100_INVALID_VALUE;
6062
f_pProductionBist->ulExpectedValue = cOCT6100_INVALID_VALUE;
6063
f_pProductionBist->ulBistStatus = cOCT6100_BIST_IN_PROGRESS;
6064
6065
/* The API knows that the firmware might be writing a status event. */
6066
/* The firmware does write a status event every 200ms (approximately). */
6067
/* So the status is read a couple of times to make sure an event was not read while */
6068
/* it was written. */
6069
while ( ulLoopCnt != 2 )
6070
{
6071
/* Read the BIST status in the external memory. */
6072
for ( i = 0; i < ulTotalElements + 1; i ++ )
6073
{
6074
ulResult = Oct6100ApiReadDword( f_pApiInstance, ulReadAddress + i * 4, &aulMessage[ i ] );
6075
if ( ulResult != cOCT6100_ERR_OK )
6076
return ulResult;
6077
}
6078
6079
/* Calculate the CRC of this message. */
6080
ulResult = Oct6100ApiProductionCrc( f_pApiInstance, aulMessage, ulTotalElements, &ulCalculatedCrc );
6081
if ( ulResult != cOCT6100_ERR_OK )
6082
return ulResult;
6083
6084
/* If the CRCs do match, break off the while. We have a valid status event. */
6085
if ( aulMessage[ i - 1 ] == ulCalculatedCrc )
6086
break;
6087
6088
ulLoopCnt++;
6089
}
6090
6091
/* Check if the CRC matches */
6092
if ( aulMessage[ i - 1 ] != ulCalculatedCrc )
6093
{
6094
/* Well, the exchange memory at the base of the external memory is corrupted. */
6095
/* Something very basic is not working correctly with this chip! */
6096
f_pProductionBist->ulBistStatus = cOCT6100_BIST_STATUS_CRC_FAILED;
6097
}
6098
else
6099
{
6100
/* Check for problems. */
6101
switch ( aulMessage[ 0 ] & 0xFFFF )
6102
{
6103
case ( 0x2 ):
6104
6105
/* The initial configuration failed. */
6106
f_pProductionBist->ulBistStatus = cOCT6100_BIST_CONFIGURATION_FAILED;
6107
break;
6108
6109
case ( 0x1 ):
6110
6111
/* A memory location failed. Return useful information to the user. */
6112
f_pProductionBist->ulBistStatus = cOCT6100_BIST_MEMORY_FAILED;
6113
6114
f_pProductionBist->ulFailedAddress = ( aulMessage[ 1 ] & ( ~0x80000000 ) ) + cOCT6100_EXTERNAL_MEM_BASE_ADDRESS;
6115
f_pProductionBist->ulReadValue = aulMessage[ 2 ];
6116
f_pProductionBist->ulExpectedValue = aulMessage[ 3 ];
6117
break;
6118
6119
case ( 0xFFFF ):
6120
6121
/* Bist is completed! */
6122
f_pProductionBist->ulBistStatus = cOCT6100_BIST_SUCCESS;
6123
break;
6124
6125
default:
6126
/* Bist is in progress. All seems to be working fine up to now. */
6127
6128
/* Return progress status. */
6129
f_pProductionBist->ulCurrentAddress = ( aulMessage[ 1 ] & ( ~0x80000000 ) ) + cOCT6100_EXTERNAL_MEM_BASE_ADDRESS;
6130
f_pProductionBist->ulCurrentTest = aulMessage[ 2 ];
6131
f_pProductionBist->ulCurrentLoop = aulMessage[ 3 ];
6132
break;
6133
}
6134
}
6135
6136
return cOCT6100_ERR_OK;
6137
}
6138
#endif
6139
6140
6141
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\
6142
6143
Function: Oct6100ApiProductionCrc
6144
6145
Description: This function calculates the crc for a production BIST
6146
message.
6147
6148
-------------------------------------------------------------------------------
6149
| Argument | Description
6150
-------------------------------------------------------------------------------
6151
f_pApiInstance Pointer to API instance. This memory is used to keep
6152
the present state of the chip and all its resources.
6153
6154
f_pulMessage Message to be exchanged with the firmware. The CRC
6155
will be calculated on this.
6156
f_ulMessageLength Length of the message to be exchanged. This value
6157
does not include the CRC value at the end
6158
f_pulCrcResult Resulting calculated CRC value.
6159
6160
\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
6161
#if !SKIP_Oct6100ApiProductionCrc
6162
UINT32 Oct6100ApiProductionCrc(
6163
IN OUT tPOCT6100_INSTANCE_API f_pApiInstance,
6164
IN PUINT32 f_pulMessage,
6165
IN UINT32 f_ulMessageLength,
6166
OUT PUINT32 f_pulCrcResult )
6167
{
6168
UINT32 ulWidth = 32;
6169
UINT32 ulKey, i, j;
6170
UINT32 ulRemainder = 0;
6171
6172
/* CRC the message. */
6173
ulRemainder = f_pulMessage[ f_ulMessageLength - 1 ];
6174
for ( j = f_ulMessageLength - 1; j != 0xFFFFFFFF ; j-- )
6175
{
6176
for ( i = 0; i < ulWidth; i++ )
6177
{
6178
if ( ( ( ulRemainder >> 0x1F ) & 0x1 ) == 0x1 )
6179
{
6180
/* Division is by something meaningful */
6181
ulKey = 0x8765DCBA;
6182
}
6183
else
6184
{
6185
/* Remainder is less than our divisor */
6186
ulKey = 0;
6187
}
6188
ulRemainder = ulRemainder ^ ulKey;
6189
6190
ulRemainder = ulRemainder << 1;
6191
if ( j != 0 )
6192
{
6193
ulRemainder = ulRemainder | ( ( f_pulMessage[ j - 1 ] ) >> ( 0x1F - i ) );
6194
}
6195
}
6196
}
6197
6198
*f_pulCrcResult = ulRemainder;
6199
6200
return cOCT6100_ERR_OK;
6201
}
6202
#endif
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