1
/* Copyright (c) 2009 Atmel Corporation
4
Redistribution and use in source and binary forms, with or without
5
modification, are permitted provided that the following conditions are met:
7
* Redistributions of source code must retain the above copyright
8
notice, this list of conditions and the following disclaimer.
10
* Redistributions in binary form must reproduce the above copyright
11
notice, this list of conditions and the following disclaimer in
12
the documentation and/or other materials provided with the
15
* Neither the name of the copyright holders nor the names of
16
contributors may be used to endorse or promote products derived
17
from this software without specific prior written permission.
19
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
POSSIBILITY OF SUCH DAMAGE. */
31
/* $Id: iom16u4.h,v 1.1.2.2 2009/02/19 21:10:54 arcanum Exp $ */
33
/* avr/iom16u4.h - definitions for ATmega16U4 */
35
/* This file should only be included from <avr/io.h>, never directly. */
38
# error "Include <avr/io.h> instead of this file."
42
# define _AVR_IOXXX_H_ "iom16u4.h"
44
# error "Attempt to include more than one <avr/ioXXX.h> file."
48
#ifndef _AVR_ATmega16U4_H_
49
#define _AVR_ATmega16U4_H_ 1
52
/* Registers and associated bit numbers. */
54
#define PINB _SFR_IO8(0x03)
64
#define DDRB _SFR_IO8(0x04)
74
#define PORTB _SFR_IO8(0x05)
84
#define PINC _SFR_IO8(0x06)
88
#define DDRC _SFR_IO8(0x07)
92
#define PORTC _SFR_IO8(0x08)
96
#define PIND _SFR_IO8(0x09)
106
#define DDRD _SFR_IO8(0x0A)
116
#define PORTD _SFR_IO8(0x0B)
126
#define PINE _SFR_IO8(0x0C)
130
#define DDRE _SFR_IO8(0x0D)
134
#define PORTE _SFR_IO8(0x0E)
138
#define PINF _SFR_IO8(0x0F)
146
#define DDRF _SFR_IO8(0x10)
154
#define PORTF _SFR_IO8(0x11)
162
#define TIFR0 _SFR_IO8(0x15)
167
#define TIFR1 _SFR_IO8(0x16)
174
#define TIFR2 _SFR_IO8(0x17)
176
#define TIFR3 _SFR_IO8(0x18)
183
#define TIFR4 _SFR_IO8(0x19)
189
#define PCIFR _SFR_IO8(0x1B)
192
#define EIFR _SFR_IO8(0x1C)
202
#define EIMSK _SFR_IO8(0x1D)
212
#define GPIOR0 _SFR_IO8(0x1E)
222
#define EECR _SFR_IO8(0x1F)
230
#define EEDR _SFR_IO8(0x20)
240
#define EEAR _SFR_IO16(0x21)
242
#define EEARL _SFR_IO8(0x21)
252
#define EEARH _SFR_IO8(0x22)
258
#define GTCCR _SFR_IO8(0x23)
262
#define TCCR0A _SFR_IO8(0x24)
270
#define TCCR0B _SFR_IO8(0x25)
278
#define TCNT0 _SFR_IO8(0x26)
288
#define OCR0A _SFR_IO8(0x27)
298
#define OCR0B _SFR_IO8(0x28)
308
#define PLLCSR _SFR_IO8(0x29)
313
#define GPIOR1 _SFR_IO8(0x2A)
323
#define GPIOR2 _SFR_IO8(0x2B)
333
#define SPCR _SFR_IO8(0x2C)
343
#define SPSR _SFR_IO8(0x2D)
348
#define SPDR _SFR_IO8(0x2E)
358
#define ACSR _SFR_IO8(0x30)
368
#define OCDR _SFR_IO8(0x31)
378
#define PLLFRQ _SFR_IO8(0x32)
388
#define SMCR _SFR_IO8(0x33)
394
#define MCUSR _SFR_IO8(0x34)
401
#define MCUCR _SFR_IO8(0x35)
407
#define SPMCSR _SFR_IO8(0x37)
417
#define RAMPZ _SFR_IO8(0x3B)
420
#define EIND _SFR_IO8(0x3C)
423
#define WDTCSR _SFR_MEM8(0x60)
433
#define CLKPR _SFR_MEM8(0x61)
440
#define PRR0 _SFR_MEM8(0x64)
449
#define PRR1 _SFR_MEM8(0x65)
454
#define OSCCAL _SFR_MEM8(0x66)
464
#define RCCTRL _SFR_MEM8(0x67)
467
#define PCICR _SFR_MEM8(0x68)
470
#define EICRA _SFR_MEM8(0x69)
480
#define EICRB _SFR_MEM8(0x6A)
490
#define PCMSK0 _SFR_MEM8(0x6B)
500
#define TIMSK0 _SFR_MEM8(0x6E)
505
#define TIMSK1 _SFR_MEM8(0x6F)
512
#define TIMSK3 _SFR_MEM8(0x71)
519
#define TIMSK4 _SFR_MEM8(0x72)
525
#ifndef __ASSEMBLER__
526
#define ADC _SFR_MEM16(0x78)
528
#define ADCW _SFR_MEM16(0x78)
530
#define ADCL _SFR_MEM8(0x78)
540
#define ADCH _SFR_MEM8(0x79)
550
#define ADCSRA _SFR_MEM8(0x7A)
560
#define ADCSRB _SFR_MEM8(0x7B)
569
#define ADMUX _SFR_MEM8(0x7C)
579
#define DIDR2 _SFR_MEM8(0x7D)
587
#define DIDR0 _SFR_MEM8(0x7E)
597
#define DIDR1 _SFR_MEM8(0x7F)
601
#define TCCR1A _SFR_MEM8(0x80)
611
#define TCCR1B _SFR_MEM8(0x81)
620
#define TCCR1C _SFR_MEM8(0x82)
625
#define TCNT1 _SFR_MEM16(0x84)
627
#define TCNT1L _SFR_MEM8(0x84)
637
#define TCNT1H _SFR_MEM8(0x85)
647
#define ICR1 _SFR_MEM16(0x86)
649
#define ICR1L _SFR_MEM8(0x86)
659
#define ICR1H _SFR_MEM8(0x87)
669
#define OCR1A _SFR_MEM16(0x88)
671
#define OCR1AL _SFR_MEM8(0x88)
681
#define OCR1AH _SFR_MEM8(0x89)
691
#define OCR1B _SFR_MEM16(0x8A)
693
#define OCR1BL _SFR_MEM8(0x8A)
703
#define OCR1BH _SFR_MEM8(0x8B)
713
#define OCR1C _SFR_MEM16(0x8C)
715
#define OCR1CL _SFR_MEM8(0x8C)
725
#define OCR1CH _SFR_MEM8(0x8D)
735
#define TCCR3A _SFR_MEM8(0x90)
745
#define TCCR3B _SFR_MEM8(0x91)
754
#define TCCR3C _SFR_MEM8(0x92)
759
#define TCNT3 _SFR_MEM16(0x94)
761
#define TCNT3L _SFR_MEM8(0x94)
771
#define TCNT3H _SFR_MEM8(0x95)
781
#define ICR3 _SFR_MEM16(0x96)
783
#define ICR3L _SFR_MEM8(0x96)
793
#define ICR3H _SFR_MEM8(0x97)
803
#define OCR3A _SFR_MEM16(0x98)
805
#define OCR3AL _SFR_MEM8(0x98)
815
#define OCR3AH _SFR_MEM8(0x99)
825
#define OCR3B _SFR_MEM16(0x9A)
827
#define OCR3BL _SFR_MEM8(0x9A)
837
#define OCR3BH _SFR_MEM8(0x9B)
847
#define OCR3C _SFR_MEM16(0x9C)
849
#define OCR3CL _SFR_MEM8(0x9C)
859
#define OCR3CH _SFR_MEM8(0x9D)
869
#define TCNT4 _SFR_MEM8(0xBE)
879
#define TC4H _SFR_MEM8(0xBF)
884
#define TCCR4A _SFR_MEM8(0xC0)
894
#define TCCR4B _SFR_MEM8(0xC1)
904
#define TCCR4C _SFR_MEM8(0xC2)
914
#define TCCR4D _SFR_MEM8(0xC3)
924
#define TCCR4E _SFR_MEM8(0xC4)
934
#define CLKSEL0 _SFR_MEM8(0xC5)
943
#define CLKSEL1 _SFR_MEM8(0xC6)
953
#define CLKSTA _SFR_MEM8(0xC7)
957
#define UCSR1A _SFR_MEM8(0xC8)
967
#define UCSR1B _SFR_MEM8(0xC9)
977
#define UCSR1C _SFR_MEM8(0xCA)
987
#define UBRR1 _SFR_MEM16(0xCC)
989
#define UBRR1L _SFR_MEM8(0xCC)
991
#define UBRR1H _SFR_MEM8(0xCD)
993
#define UDR1 _SFR_MEM8(0xCE)
1003
#define OCR4A _SFR_MEM8(0xCF)
1013
#define OCR4B _SFR_MEM8(0xD0)
1023
#define OCR4C _SFR_MEM8(0xD1)
1033
#define OCR4D _SFR_MEM8(0xD2)
1043
#define DT4 _SFR_MEM8(0xD4)
1053
#define UHWCON _SFR_MEM8(0xD7)
1056
#define USBCON _SFR_MEM8(0xD8)
1062
#define USBSTA _SFR_MEM8(0xD9)
1066
#define USBINT _SFR_MEM8(0xDA)
1069
#define UDCON _SFR_MEM8(0xE0)
1075
#define UDINT _SFR_MEM8(0xE1)
1083
#define UDIEN _SFR_MEM8(0xE2)
1091
#define UDADDR _SFR_MEM8(0xE3)
1101
#define UDFNUM _SFR_MEM16(0xE4)
1103
#define UDFNUML _SFR_MEM8(0xE4)
1113
#define UDFNUMH _SFR_MEM8(0xE5)
1118
#define UDMFN _SFR_MEM8(0xE6)
1121
#define UEINTX _SFR_MEM8(0xE8)
1131
#define UENUM _SFR_MEM8(0xE9)
1136
#define UERST _SFR_MEM8(0xEA)
1145
#define UECONX _SFR_MEM8(0xEB)
1151
#define UECFG0X _SFR_MEM8(0xEC)
1156
#define UECFG1X _SFR_MEM8(0xED)
1164
#define UESTA0X _SFR_MEM8(0xEE)
1173
#define UESTA1X _SFR_MEM8(0xEF)
1178
#define UEIENX _SFR_MEM8(0xF0)
1187
#define UEDATX _SFR_MEM8(0xF1)
1197
#define UEBCLX _SFR_MEM8(0xF2)
1207
#define UEBCHX _SFR_MEM8(0xF3)
1209
#define UEINT _SFR_MEM8(0xF4)
1219
/* Interrupt vectors */
1220
/* Vector 0 is the reset vector */
1221
#define INT0_vect_num 1
1222
#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
1223
#define INT1_vect_num 2
1224
#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
1225
#define INT2_vect_num 3
1226
#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */
1227
#define INT3_vect_num 4
1228
#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */
1229
#define INT6_vect_num 7
1230
#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */
1231
#define PCINT0_vect_num 9
1232
#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */
1233
#define USB_GEN_vect_num 10
1234
#define USB_GEN_vect _VECTOR(10) /* USB General Interrupt Request */
1235
#define USB_COM_vect_num 11
1236
#define USB_COM_vect _VECTOR(11) /* USB Endpoint/Pipe Interrupt Communication Request */
1237
#define WDT_vect_num 12
1238
#define WDT_vect _VECTOR(12) /* Watchdog Time-out Interrupt */
1239
#define TIMER1_CAPT_vect_num 16
1240
#define TIMER1_CAPT_vect _VECTOR(16) /* Timer/Counter1 Capture Event */
1241
#define TIMER1_COMPA_vect_num 17
1242
#define TIMER1_COMPA_vect _VECTOR(17) /* Timer/Counter1 Compare Match A */
1243
#define TIMER1_COMPB_vect_num 18
1244
#define TIMER1_COMPB_vect _VECTOR(18) /* Timer/Counter1 Compare Match B */
1245
#define TIMER1_COMPC_vect_num 19
1246
#define TIMER1_COMPC_vect _VECTOR(19) /* Timer/Counter1 Compare Match C */
1247
#define TIMER1_OVF_vect_num 20
1248
#define TIMER1_OVF_vect _VECTOR(20) /* Timer/Counter1 Overflow */
1249
#define TIMER0_COMPA_vect_num 21
1250
#define TIMER0_COMPA_vect _VECTOR(21) /* Timer/Counter0 Compare Match A */
1251
#define TIMER0_COMPB_vect_num 22
1252
#define TIMER0_COMPB_vect _VECTOR(22) /* Timer/Counter0 Compare Match B */
1253
#define TIMER0_OVF_vect_num 23
1254
#define TIMER0_OVF_vect _VECTOR(23) /* Timer/Counter0 Overflow */
1255
#define SPI_STC_vect_num 24
1256
#define SPI_STC_vect _VECTOR(24) /* SPI Serial Transfer Complete */
1257
#define USART1_RX_vect_num 25
1258
#define USART1_RX_vect _VECTOR(25) /* USART1, Rx Complete */
1259
#define USART1_UDRE_vect_num 26
1260
#define USART1_UDRE_vect _VECTOR(26) /* USART1 Data register Empty */
1261
#define USART1_TX_vect_num 27
1262
#define USART1_TX_vect _VECTOR(27) /* USART1, Tx Complete */
1263
#define ANALOG_COMP_vect_num 28
1264
#define ANALOG_COMP_vect _VECTOR(28) /* Analog Comparator */
1265
#define ADC_vect_num 29
1266
#define ADC_vect _VECTOR(29) /* ADC Conversion Complete */
1267
#define EE_READY_vect_num 30
1268
#define EE_READY_vect _VECTOR(30) /* EEPROM Ready */
1269
#define TIMER3_CAPT_vect_num 31
1270
#define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */
1271
#define TIMER3_COMPA_vect_num 32
1272
#define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */
1273
#define TIMER3_COMPB_vect_num 33
1274
#define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */
1275
#define TIMER3_COMPC_vect_num 34
1276
#define TIMER3_COMPC_vect _VECTOR(34) /* Timer/Counter3 Compare Match C */
1277
#define TIMER3_OVF_vect_num 35
1278
#define TIMER3_OVF_vect _VECTOR(35) /* Timer/Counter3 Overflow */
1279
#define TWI_vect_num 36
1280
#define TWI_vect _VECTOR(36) /* 2-wire Serial Interface */
1281
#define SPM_READY_vect_num 37
1282
#define SPM_READY_vect _VECTOR(37) /* Store Program Memory Read */
1283
#define TIMER4_COMPA_vect_num 38
1284
#define TIMER4_COMPA_vect _VECTOR(38) /* Timer/Counter4 Compare Match A */
1285
#define TIMER4_COMPB_vect_num 39
1286
#define TIMER4_COMPB_vect _VECTOR(39) /* Timer/Counter4 Compare Match B */
1287
#define TIMER4_COMPD_vect_num 40
1288
#define TIMER4_COMPD_vect _VECTOR(40) /* Timer/Counter4 Compare Match D */
1289
#define TIMER4_OVF_vect_num 41
1290
#define TIMER4_OVF_vect _VECTOR(41) /* Timer/Counter4 Overflow */
1291
#define TIMER4_FPF_vect_num 42
1292
#define TIMER4_FPF_vect _VECTOR(42) /* Timer/Counter4 Fault Protection Interrupt */
1294
#define _VECTOR_SIZE 4 /* Size of individual vector. */
1295
#define _VECTORS_SIZE (43 * _VECTOR_SIZE)
1299
#define SPM_PAGESIZE (128)
1300
#define RAMSTART (0x100)
1301
#define RAMSIZE (1280)
1302
#define RAMEND (RAMSTART + RAMSIZE - 1)
1303
#define XRAMSTART (NA)
1304
#define XRAMSIZE (0)
1305
#define XRAMEND (RAMEND)
1306
#define E2END (0x1FF)
1307
#define E2PAGESIZE (4)
1308
#define FLASHEND (0x3FFF)
1312
#define FUSE_MEMORY_SIZE 3
1315
#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
1316
#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
1317
#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
1318
#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
1319
#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
1320
#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
1321
#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */
1322
#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
1323
#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
1325
/* High Fuse Byte */
1326
#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
1327
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
1328
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
1329
#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
1330
#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */
1331
#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
1332
#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */
1333
#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */
1334
#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
1336
/* Extended Fuse Byte */
1337
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
1338
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
1339
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
1340
#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */
1341
#define EFUSE_DEFAULT (0xFF)
1345
#define __LOCK_BITS_EXIST
1346
#define __BOOT_LOCK_BITS_0_EXIST
1347
#define __BOOT_LOCK_BITS_1_EXIST
1351
#define SIGNATURE_0 0x1E
1352
#define SIGNATURE_1 0x94
1353
#define SIGNATURE_2 0x88
1356
#endif /* _AVR_ATmega16U4_H_ */
added
removed
include/avr/iom16u4.h
