27
26
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28
27
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29
28
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30
POSSIBILITY OF SUCH DAMAGE. */
32
/* $Id: iom88p.h,v 1.1.2.2 2007/10/25 12:24:32 aesok Exp $ */
29
POSSIBILITY OF SUCH DAMAGE.
32
/* $Id: iom88p.h,v 1.3.2.6 2008/03/19 21:25:13 arcanum Exp $ */
34
/* avr/iom88p.h - definitions for ATmega88P. */
36
/* This file should only be included from <avr/io.h>, never directly. */
39
# error "Include <avr/io.h> instead of this file."
43
# define _AVR_IOXXX_H_ "iom88p.h"
45
# error "Attempt to include more than one <avr/ioXXX.h> file."
34
49
#ifndef _AVR_IOM88P_H_
35
50
#define _AVR_IOM88P_H_ 1
37
#include <avr/iomx8p.h>
52
/* Registers and associated bit numbers */
54
#define PINB _SFR_IO8(0x03)
64
#define DDRB _SFR_IO8(0x04)
74
#define PORTB _SFR_IO8(0x05)
84
#define PINC _SFR_IO8(0x06)
93
#define DDRC _SFR_IO8(0x07)
102
#define PORTC _SFR_IO8(0x08)
111
#define PIND _SFR_IO8(0x09)
121
#define DDRD _SFR_IO8(0x0A)
131
#define PORTD _SFR_IO8(0x0B)
141
#define TIFR0 _SFR_IO8(0x15)
146
#define TIFR1 _SFR_IO8(0x16)
152
#define TIFR2 _SFR_IO8(0x17)
157
#define PCIFR _SFR_IO8(0x1B)
162
#define EIFR _SFR_IO8(0x1C)
166
#define EIMSK _SFR_IO8(0x1D)
170
#define GPIOR0 _SFR_IO8(0x1E)
180
#define EECR _SFR_IO8(0x1F)
188
#define EEDR _SFR_IO8(0x20)
198
#define EEAR _SFR_IO16(0x21)
200
#define EEARL _SFR_IO8(0x21)
210
#define EEARH _SFR_IO8(0x22)
213
#define EEPROM_REG_LOCATIONS 1F2021
215
#define GTCCR _SFR_IO8(0x23)
220
#define TCCR0A _SFR_IO8(0x24)
228
#define TCCR0B _SFR_IO8(0x25)
236
#define TCNT0 _SFR_IO8(0x26)
246
#define OCR0A _SFR_IO8(0x27)
256
#define OCR0B _SFR_IO8(0x28)
266
#define GPIOR1 _SFR_IO8(0x2A)
276
#define GPIOR2 _SFR_IO8(0x2B)
286
#define SPCR _SFR_IO8(0x2C)
296
#define SPSR _SFR_IO8(0x2D)
301
#define SPDR _SFR_IO8(0x2E)
311
#define ACSR _SFR_IO8(0x30)
321
#define SMCR _SFR_IO8(0x33)
327
#define MCUSR _SFR_IO8(0x34)
333
#define MCUCR _SFR_IO8(0x35)
340
#define SPMCSR _SFR_IO8(0x37)
349
#define WDTCSR _SFR_MEM8(0x60)
359
#define CLKPR _SFR_MEM8(0x61)
366
#define PRR _SFR_MEM8(0x64)
375
#define OSCCAL _SFR_MEM8(0x66)
385
#define PCICR _SFR_MEM8(0x68)
390
#define EICRA _SFR_MEM8(0x69)
396
#define PCMSK0 _SFR_MEM8(0x6B)
406
#define PCMSK1 _SFR_MEM8(0x6C)
415
#define PCMSK2 _SFR_MEM8(0x6D)
425
#define TIMSK0 _SFR_MEM8(0x6E)
430
#define TIMSK1 _SFR_MEM8(0x6F)
436
#define TIMSK2 _SFR_MEM8(0x70)
441
#define ADC _SFR_MEM16(0x78)
443
#define ADCL _SFR_MEM8(0x78)
453
#define ADCH _SFR_MEM8(0x79)
463
#define ADCSRA _SFR_MEM8(0x7A)
473
#define ADCSRB _SFR_MEM8(0x7B)
479
#define ADMUX _SFR_MEM8(0x7C)
488
#define DIDR0 _SFR_MEM8(0x7E)
496
#define DIDR1 _SFR_MEM8(0x7F)
500
#define TCCR1A _SFR_MEM8(0x80)
508
#define TCCR1B _SFR_MEM8(0x81)
517
#define TCCR1C _SFR_MEM8(0x82)
521
#define TCNT1 _SFR_MEM16(0x84)
523
#define TCNT1L _SFR_MEM8(0x84)
533
#define TCNT1H _SFR_MEM8(0x85)
543
#define ICR1 _SFR_MEM16(0x86)
545
#define ICR1L _SFR_MEM8(0x86)
555
#define ICR1H _SFR_MEM8(0x87)
565
#define OCR1A _SFR_MEM16(0x88)
567
#define OCR1AL _SFR_MEM8(0x88)
577
#define OCR1AH _SFR_MEM8(0x89)
587
#define OCR1B _SFR_MEM16(0x8A)
589
#define OCR1BL _SFR_MEM8(0x8A)
599
#define OCR1BH _SFR_MEM8(0x8B)
609
#define TCCR2A _SFR_MEM8(0xB0)
617
#define TCCR2B _SFR_MEM8(0xB1)
625
#define TCNT2 _SFR_MEM8(0xB2)
635
#define OCR2A _SFR_MEM8(0xB3)
645
#define OCR2B _SFR_MEM8(0xB4)
655
#define ASSR _SFR_MEM8(0xB6)
664
#define TWBR _SFR_MEM8(0xB8)
674
#define TWSR _SFR_MEM8(0xB9)
683
#define TWAR _SFR_MEM8(0xBA)
693
#define TWDR _SFR_MEM8(0xBB)
703
#define TWCR _SFR_MEM8(0xBC)
712
#define TWAMR _SFR_MEM8(0xBD)
721
#define UCSR0A _SFR_MEM8(0xC0)
731
#define UCSR0B _SFR_MEM8(0xC1)
741
#define UCSR0C _SFR_MEM8(0xC2)
753
#define UBRR0 _SFR_MEM16(0xC4)
755
#define UBRR0L _SFR_MEM8(0xC4)
765
#define UBRR0H _SFR_MEM8(0xC5)
771
#define UDR0 _SFR_MEM8(0xC6)
783
/* Interrupt Vectors */
784
/* Interrupt Vector 0 is the reset vector. */
785
#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
786
#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
787
#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */
788
#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */
789
#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */
790
#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */
791
#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */
792
#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */
793
#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */
794
#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */
795
#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */
796
#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
797
#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */
798
#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */
799
#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */
800
#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */
801
#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */
802
#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */
803
#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */
804
#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */
805
#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */
806
#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */
807
#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */
808
#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */
809
#define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */
811
#define _VECTORS_SIZE (26 * 2)
40
#define SPM_PAGESIZE 64
44
#define FLASHEND 0x1FFF
46
#endif /* _AVR_IOM88P_H_ */
816
#define SPM_PAGESIZE 32
817
#define RAMEND 0x4FF /* Last On-Chip SRAM Location */
819
#define XRAMEND (RAMEND + XRAMSIZE)
821
#define FLASHEND 0x1FFF
826
#define FUSE_MEMORY_SIZE 3
829
#define FUSE_CKSEL0 ~_BV(0) /* Select Clock Source */
830
#define FUSE_CKSEL1 ~_BV(1) /* Select Clock Source */
831
#define FUSE_CKSEL2 ~_BV(2) /* Select Clock Source */
832
#define FUSE_CKSEL3 ~_BV(3) /* Select Clock Source */
833
#define FUSE_SUT0 ~_BV(4) /* Select start-up time */
834
#define FUSE_SUT1 ~_BV(5) /* Select start-up time */
835
#define FUSE_CKOUT ~_BV(6) /* Clock output */
836
#define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */
837
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
840
#define FUSE_BODLEVEL0 ~_BV(0) /* Brown-out Detector trigger level */
841
#define FUSE_BODLEVEL1 ~_BV(1) /* Brown-out Detector trigger level */
842
#define FUSE_BODLEVEL2 ~_BV(2) /* Brown-out Detector trigger level */
843
#define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */
844
#define FUSE_WDTON ~_BV(4) /* Watchdog Timer Always On */
845
#define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */
846
#define FUSE_DWEN ~_BV(6) /* debugWIRE Enable */
847
#define FUSE_RSTDISBL ~_BV(7) /* External reset disable */
848
#define HFUSE_DEFAULT (FUSE_SPIEN)
850
/* Extended Fuse Byte */
851
#define FUSE_BOOTRST ~_BV(0)
852
#define FUSE_BOOTSZ0 ~_BV(1)
853
#define FUSE_BOOTSZ1 ~_BV(2)
854
#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
859
#define __LOCK_BITS_EXIST
860
#define __BOOT_LOCK_BITS_0_EXIST
861
#define __BOOT_LOCK_BITS_1_EXIST
864
#endif /* _AVR_IOM88P_H_ */
added
removed
include/avr/iom88p.h
