~ubuntu-branches/ubuntu/raring/avr-libc/raring-proposed : revision 8

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Redistribution and use in source and binary forms, with or without

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modification, are permitted provided that the following conditions are met:

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* Redistributions of source code must retain the above copyright

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notice, this list of conditions and the following disclaimer.

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* Redistributions in binary form must reproduce the above copyright

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notice, this list of conditions and the following disclaimer in

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the documentation and/or other materials provided with the

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distribution.

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* Neither the name of the copyright holders nor the names of

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contributors may be used to endorse or promote products derived

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from this software without specific prior written permission.

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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE

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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

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POSSIBILITY OF SUCH DAMAGE. */

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/* $Id: iox128a1.h,v 1.1.2.3 2008/03/27 01:07:47 arcanum Exp $ */

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#ifndef _AVR_ATxmega128A1_H_

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#define _AVR_ATxmega128A1_H_ 1

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/* This file should only be included from <avr/io.h>, never directly. */

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#ifndef _AVR_IO_H_

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# error "Include <avr/io.h> instead of this file."

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#endif

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#ifndef _AVR_IOXXX_H_

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# define _AVR_IOXXX_H_ "iox128a1.h"

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#else

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# error "Attempt to include more than one <avr/ioXXX.h> file."

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#endif

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/* Ungrouped common registers */

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#define GPIO0 _SFR_MEM8(0x00) // General Purpose IO Register 0

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#define GPIO1 _SFR_MEM8(0x01) // General Purpose IO Register 1

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#define GPIO2 _SFR_MEM8(0x02) // General Purpose IO Register 2

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#define GPIO3 _SFR_MEM8(0x03) // General Purpose IO Register 3

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#define GPIO4 _SFR_MEM8(0x04) // General Purpose IO Register 4

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#define GPIO5 _SFR_MEM8(0x05) // General Purpose IO Register 5

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#define GPIO6 _SFR_MEM8(0x06) // General Purpose IO Register 6

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#define GPIO7 _SFR_MEM8(0x07) // General Purpose IO Register 7

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#define GPIO8 _SFR_MEM8(0x08) // General Purpose IO Register 8

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#define GPIO9 _SFR_MEM8(0x09) // General Purpose IO Register 9

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#define GPIOA _SFR_MEM8(0x0A) // General Purpose IO Register 10

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#define GPIOB _SFR_MEM8(0x0B) // General Purpose IO Register 11

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#define GPIOC _SFR_MEM8(0x0C) // General Purpose IO Register 12

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#define GPIOD _SFR_MEM8(0x0D) // General Purpose IO Register 13

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#define GPIOE _SFR_MEM8(0x0E) // General Purpose IO Register 14

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#define GPIOF _SFR_MEM8(0x0F) // General Purpose IO Register 15

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#define CCP _SFR_MEM8(0x34) // Configuration Change Protection

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#define RAMPD _SFR_MEM8(0x38) // Ramp D

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#define RAMPX _SFR_MEM8(0x39) // Ramp X

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#define RAMPY _SFR_MEM8(0x3A) // Ramp Y

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#define RAMPZ _SFR_MEM8(0x3B) // Ramp Z

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#define EIND _SFR_MEM8(0x3C) // Extended Indirect Jump

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#define SPL _SFR_MEM8(0x3D) // Stack Pointer Low

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#define SPH _SFR_MEM8(0x3E) // Stack Pointer High

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#define SP _SFR_MEM16(0x3D) // 16-bit Stack Pointer

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#define SREG _SFR_MEM8(0x3F) // Status Register

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/* C Language Only */

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#if !defined (__ASSEMBLER__)

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#include <stdint.h>

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typedef volatile uint8_t register8_t;

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typedef volatile uint16_t register16_t;

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typedef volatile uint32_t register32_t;

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#ifdef _WORDREGISTER

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#undef _WORDREGISTER

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#endif

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#define _WORDREGISTER(regname) \

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union \

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{ \

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register16_t regname; \

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struct \

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{ \

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register8_t regname ## L; \

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register8_t regname ## H; \

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}; \

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}

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#ifdef _DWORDREGISTER

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#undef _DWORDREGISTER

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#endif

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#define _DWORDREGISTER(regname) \

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union \

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{ \

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register32_t regname; \

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struct \

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{ \

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register8_t regname ## 0; \

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register8_t regname ## 1; \

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register8_t regname ## 2; \

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register8_t regname ## 3; \

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}; \

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}

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/*

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==========================================================================

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IO Module Structures

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==========================================================================

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*/

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/*

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--------------------------------------------------------------------------

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XOCD - On-Chip Debug System

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--------------------------------------------------------------------------

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*/

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/* On-Chip Debug System */

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typedef struct OCD_struct

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{

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register8_t OCDR0; /* OCD Register 0 */

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register8_t OCDR1; /* OCD Register 1 */

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} OCD_t;

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/*

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--------------------------------------------------------------------------

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CLK - Clock System

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--------------------------------------------------------------------------

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*/

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/* Clock System */

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typedef struct CLK_struct

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{

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register8_t CTRL; /* Control Register */

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register8_t PSCTRL; /* Prescaler Control Register */

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register8_t LOCK; /* Lock register */

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register8_t RTCCTRL; /* RTC Control Register */

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} CLK_t;

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/* Power Reduction */

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typedef struct PR_struct

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{

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register8_t PR; /* General Power Reduction */

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register8_t PRPA; /* Power Reduction Port A */

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register8_t PRPB; /* Power Reduction Port B */

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register8_t PRPC; /* Power Reduction Port C */

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register8_t PRPD; /* Power Reduction Port D */

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register8_t PRPE; /* Power Reduction Port E */

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register8_t PRPF; /* Power Reduction Port F */

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} PR_t;

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/*

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--------------------------------------------------------------------------

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SLEEP - Sleep Controller

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--------------------------------------------------------------------------

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*/

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/* Sleep Controller */

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typedef struct SLEEP_struct

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{

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register8_t CTRL; /* Control Register */

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} SLEEP_t;

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/*

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--------------------------------------------------------------------------

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OSC - Oscillator

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--------------------------------------------------------------------------

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*/

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/* Oscillator */

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typedef struct OSC_struct

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{

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register8_t CTRL; /* Control Register */

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register8_t STATUS; /* Status Register */

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register8_t XOSCCTRL; /* External Oscillator Control Register */

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register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */

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register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */

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register8_t PLLCTRL; /* PLL Control REgister */

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register8_t DFLLCTRL; /* DFLL Control Register */

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} OSC_t;

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/*

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--------------------------------------------------------------------------

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DFLL - DFLL

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--------------------------------------------------------------------------

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*/

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/* DFLL */

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typedef struct DFLL_struct

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{

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register8_t OSCCNT0; /* Oscillator Counter Register 0 */

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register8_t OSCCNT1; /* Oscillator Counter Register 1 */

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register8_t OSCCNT2; /* Oscillator Counter Register 2 */

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register8_t CALA; /* Calibration Register A */

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register8_t CALB; /* Calibration Register B */

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} DFLL_t;

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/*

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--------------------------------------------------------------------------

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RST - Reset

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--------------------------------------------------------------------------

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*/

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/* Reset */

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typedef struct RST_struct

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{

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register8_t STATUS; /* Status Register */

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register8_t CTRL; /* Control Register */

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} RST_t;

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/*

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--------------------------------------------------------------------------

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WDT - Watch-Dog Timer

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--------------------------------------------------------------------------

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*/

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/* Watch-Dog Timer */

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typedef struct WDT_struct

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{

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register8_t CTRL; /* Control */

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register8_t WINCTRL; /* Windowed Mode Control */

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register8_t STATUS; /* Status */

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} WDT_t;

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/*

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--------------------------------------------------------------------------

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MCU - MCU

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--------------------------------------------------------------------------

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*/

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/* MCU */

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typedef struct MCU_struct

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{

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register8_t DEVID0; /* Device ID byte 0 */

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register8_t DEVID1; /* Device ID byte 1 */

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register8_t DEVID2; /* Device ID byte 2 */

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register8_t REVID; /* Revision ID */

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register8_t JTAGUID; /* JTAG User ID */

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register8_t reserved_0x05;

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register8_t MCUCR; /* MCU Control */

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register8_t reserved_0x07;

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register8_t EVSYSLOCK; /* Event System Lock */

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register8_t AWEXLOCK; /* AWeX Lock */

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register8_t reserved_0x0A;

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register8_t reserved_0x0B;

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} MCU_t;

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/*

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--------------------------------------------------------------------------

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PMIC - Programmable Multi-level Interrupt Controller

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--------------------------------------------------------------------------

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*/

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/* Programmable Multi-level Interrupt Controller */

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typedef struct PMIC_struct

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{

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register8_t STATUS; /* Status Register */

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register8_t INTPRI; /* Interrupt Priority */

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register8_t CTRL; /* Control Register */

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} PMIC_t;

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/*

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--------------------------------------------------------------------------

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DMA - DMA Controller

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--------------------------------------------------------------------------

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*/

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/* DMA Channel */

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typedef struct DMA_CH_struct

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{

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register8_t CTRLA; /* Channel Control */

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register8_t CTRLB; /* Channel Control */

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register8_t ADDRCTRL; /* Address Control */

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register8_t TRIGSRC; /* Channel Trigger Source */

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register8_t reserved_0x03;

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_WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */

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register8_t REPCNT; /* Channel Repeat Count */

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register8_t reserved_0x07;

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register8_t SRCADDR0; /* Channel Source Address 0 */

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register8_t SRCADDR1; /* Channel Source Address 1 */

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register8_t SRCADDR2; /* Channel Source Address 2 */

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register8_t reserved_0x0B;

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register8_t DESTADDR0; /* Channel Destination Address 0 */

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register8_t DESTADDR1; /* Channel Destination Address 1 */

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register8_t DESTADDR2; /* Channel Destination Address 2 */

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register8_t reserved_0x0F;

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} DMA_CH_t;

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/* DMA Controller */

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typedef struct DMA_struct

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{

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register8_t CTRL; /* Control */

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register8_t INTFLAGS; /* Transfer Interrupt Status */

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register8_t STATUS; /* Status */

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register8_t reserved_0x05;

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register8_t reserved_0x06;

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register8_t reserved_0x07;

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register8_t reserved_0x08;

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register8_t reserved_0x09;

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register8_t reserved_0x0A;

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register8_t reserved_0x0B;

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register8_t reserved_0x0C;

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register8_t reserved_0x0D;

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register8_t reserved_0x0E;

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register8_t reserved_0x0F;

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DMA_CH_t CH0; /* DMA Channel 0 */

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DMA_CH_t CH1; /* DMA Channel 1 */

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DMA_CH_t CH2; /* DMA Channel 2 */

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DMA_CH_t CH3; /* DMA Channel 3 */

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} DMA_t;

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/*

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--------------------------------------------------------------------------

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EVSYS - Event System

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--------------------------------------------------------------------------

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*/

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/* Event System */

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typedef struct EVSYS_struct

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{

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register8_t CH0MUX; /* Event Channel 0 Multiplexer */

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register8_t CH1MUX; /* Event Channel 1 Multiplexer */

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register8_t CH2MUX; /* Event Channel 2 Multiplexer */

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register8_t CH3MUX; /* Event Channel 3 Multiplexer */

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register8_t CH4MUX; /* Event Channel 4 Multiplexer */

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register8_t CH5MUX; /* Event Channel 5 Multiplexer */

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register8_t CH6MUX; /* Event Channel 6 Multiplexer */

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register8_t CH7MUX; /* Event Channel 7 Multiplexer */

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register8_t CH0CTRL; /* Channel 0 Control Register */

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register8_t CH1CTRL; /* Channel 1 Control Register */

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register8_t CH2CTRL; /* Channel 2 Control Register */

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register8_t CH3CTRL; /* Channel 3 Control Register */

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register8_t CH4CTRL; /* Channel 4 Control Register */

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register8_t CH5CTRL; /* Channel 5 Control Register */

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register8_t CH6CTRL; /* Channel 6 Control Register */

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register8_t CH7CTRL; /* Channel 7 Control Register */

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register8_t STROBE; /* Event Strobe */

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register8_t DATA; /* Event Data */

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} EVSYS_t;

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/*

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--------------------------------------------------------------------------

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NVM - Non Volatile Memory

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--------------------------------------------------------------------------

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*/

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/* Non-volatile Memory */

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typedef struct NVM_struct

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{

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register8_t ADDR0; /* Address Register 0 */

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register8_t ADDR1; /* Address Register 1 */

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register8_t ADDR2; /* Address Register 2 */

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register8_t reserved_0x03;

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register8_t DATA0; /* Data Register 0 */

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register8_t DATA1; /* Data Register 1 */

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register8_t DATA2; /* Data Register 2 */

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register8_t reserved_0x07;

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register8_t reserved_0x08;

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register8_t reserved_0x09;

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register8_t CMD; /* Command */

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register8_t CTRLA; /* Control Register A */

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register8_t CTRLB; /* Control Register B */

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register8_t INTCTRL; /* Interrupt Control */

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register8_t reserved_0x0E;

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register8_t STATUS; /* Status */

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register8_t LOCKBITS; /* Lock Bits */

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} NVM_t;

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/* Lock Bits */

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typedef struct NVM_LOCKBITS_struct

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{

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register8_t LOCKBITS; /* Lock Bits */

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} NVM_LOCKBITS_t;

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/* Fuses */

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typedef struct NVM_FUSES_struct

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{

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register8_t FUSEBYTE0; /* JTAG User ID */

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register8_t FUSEBYTE1; /* Watchdog Configuration */

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register8_t FUSEBYTE2; /* Reset Configuration */

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register8_t reserved_0x03;

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register8_t FUSEBYTE4; /* Start-up Configuration */

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register8_t FUSEBYTE5; /* EESAVE and BOD Level */

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} NVM_FUSES_t;

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/* Production Signatures */

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typedef struct NVM_PROD_SIGNATURES_struct

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{

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register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */

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register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */

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register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */

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register8_t LOTNUM0; /* Lot Number, Byte 0, ASCII */

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register8_t LOTNUM1; /* Lot Number, Byte 1, ASCII */

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register8_t LOTNUM2; /* Lot Number, Byte 2, ASCII */

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register8_t LOTNUM3; /* Lot Number, Byte 3, ASCII */

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register8_t LOTNUM4; /* Lot Number, Byte 4, ASCII */

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register8_t LOTNUM5; /* Lot Number, Byte 5, ASCII */

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register8_t WAFNUM; /* Wafer Number */

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_WORDREGISTER(COORDX); /* Wafer Coordinate X */

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_WORDREGISTER(COORDY); /* Wafer Coordinate Y */

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register8_t ADCACAL0; /* ADCA Calibration Byte 0 */

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register8_t ADCACAL1; /* ADCA Calibration Byte 1 */

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register8_t ADCACAL2; /* ADCA Calibration Byte 2 */

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register8_t ADCACAL3; /* ADCA Calibration Byte 3 */

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register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */

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register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */

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register8_t ADCBCAL2; /* ADCB Calibration Byte 2 */

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register8_t ADCBCAL3; /* ADCB Calibration Byte 3 */

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register8_t DACACAL0; /* DACA Calibration Byte 0 */

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register8_t DACACAL1; /* DACA Calibration Byte 1 */

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register8_t DACBCAL0; /* DACB Calibration Byte 0 */

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register8_t DACBCAL1; /* DACB Calibration Byte 1 */

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} NVM_PROD_SIGNATURES_t;

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/*

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--------------------------------------------------------------------------

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AC - Analog Comparator

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--------------------------------------------------------------------------

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*/

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/* Analog Comparator */

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typedef struct AC_struct

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{

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register8_t AC0CTRL; /* Comparator 0 Control */

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register8_t AC1CTRL; /* Comparator 1 Control */

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register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */

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register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */

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register8_t CTRLA; /* Control Register A */

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register8_t CTRLB; /* Control Register B */

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register8_t WINCTRL; /* Window Mode Control */

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register8_t STATUS; /* Status */

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} AC_t;

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/*

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--------------------------------------------------------------------------

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ADC - Analog/Digital Converter

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--------------------------------------------------------------------------

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*/

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/* ADC Channel */

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typedef struct ADC_CH_struct

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{

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register8_t CTRL; /* Control Register */

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register8_t MUXCTRL; /* MUX Control */

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register8_t INTCTRL; /* Channel Interrupt Control */

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register8_t INTFLAGS; /* Interrupt Flags */

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_WORDREGISTER(RES); /* Channel Result */

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register8_t reserved_0x6;

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register8_t reserved_0x7;

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} ADC_CH_t;

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/* Analog-to-Digital Converter */

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typedef struct ADC_struct

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{

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register8_t CTRLA; /* Control Register A */

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register8_t CTRLB; /* Control Register B */

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register8_t REFCTRL; /* Reference Control */

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register8_t EVCTRL; /* Event Control */

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register8_t PRESCALER; /* Clock Prescaler */

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register8_t CALCTRL; /* Calibration Control Register */

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register8_t INTFLAGS; /* Interrupt Flags */

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register8_t reserved_0x07;

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register8_t reserved_0x08;

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register8_t reserved_0x09;

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register8_t reserved_0x10;

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register8_t reserved_0x11;

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register8_t CALIB; /* Calibration Value */

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register8_t reserved_0x0D;

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register8_t reserved_0x0E;

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register8_t reserved_0x0F;

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_WORDREGISTER(CH0RES); /* Channel 0 Result */

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_WORDREGISTER(CH1RES); /* Channel 1 Result */

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_WORDREGISTER(CH2RES); /* Channel 2 Result */

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_WORDREGISTER(CH3RES); /* Channel 3 Result */

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_WORDREGISTER(CMP); /* Compare Value */

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register8_t reserved_0x1A;

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register8_t reserved_0x1B;

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register8_t reserved_0x1C;

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register8_t reserved_0x1D;

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register8_t reserved_0x1E;

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register8_t reserved_0x1F;

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ADC_CH_t CH0; /* ADC Channel 0 */

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ADC_CH_t CH1; /* ADC Channel 1 */

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ADC_CH_t CH2; /* ADC Channel 2 */

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ADC_CH_t CH3; /* ADC Channel 3 */

505

} ADC_t;

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507

/*

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--------------------------------------------------------------------------

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DAC - Digital/Analog Converter

510

--------------------------------------------------------------------------

511

*/

512

513

/* Digital-to-Analog Converter */

514

typedef struct DAC_struct

515

{

516

register8_t CTRLA; /* Control Register A */

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register8_t CTRLB; /* Control Register B */

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register8_t CTRLC; /* Control Register C */

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register8_t EVCTRL; /* Event Input Control */

520

register8_t TIMCTRL; /* Timing Control */

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register8_t STATUS; /* Status */

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register8_t reserved_0x06;

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register8_t reserved_0x07;

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register8_t GAINCAL; /* Gain Calibration */

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register8_t OFFSETCAL; /* Offset Calibration */

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register8_t reserved_0x0A;

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register8_t reserved_0x0B;

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register8_t reserved_0x0C;

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register8_t reserved_0x0D;

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register8_t reserved_0x0E;

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register8_t reserved_0x0F;

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register8_t reserved_0x10;

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register8_t reserved_0x11;

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register8_t reserved_0x12;

535

register8_t reserved_0x13;

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register8_t reserved_0x14;

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register8_t reserved_0x15;

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register8_t reserved_0x16;

539

register8_t reserved_0x17;

540

_WORDREGISTER(CH0DATA); /* Channel 0 Data */

541

_WORDREGISTER(CH1DATA); /* Channel 1 Data */

542

} DAC_t;

543

544

/*

545

--------------------------------------------------------------------------

546

RTC - Real-Time Clock

547

--------------------------------------------------------------------------

548

*/

549

550

/* Real-Time Clock */

551

typedef struct RTC_struct

552

{

553

register8_t CTRL; /* Control Register */

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register8_t STATUS; /* Status Register */

555

register8_t INTCTRL; /* Interrupt Control Register */

556

register8_t INTFLAGS; /* Interrupt Flags */

557

register8_t TEMP; /* Temporary register */

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register8_t reserved_0x05;

559

register8_t reserved_0x06;

560

register8_t reserved_0x07;

561

_WORDREGISTER(CNT); /* Count Register */

562

_WORDREGISTER(PER); /* Period Register */

563

_WORDREGISTER(COMP); /* Compare Register */

564

} RTC_t;

565

566

/*

567

--------------------------------------------------------------------------

568

EBI - External Bus Interface

569

--------------------------------------------------------------------------

570

*/

571

572

/* EBI Chip Select Module */

573

typedef struct EBI_CS_struct

574

{

575

register8_t CTRLA; /* Chip Select Control Register A */

576

register8_t CTRLB; /* Chip Select Control Register B */

577

_WORDREGISTER(BASEADDR); /* Chip Select Base Address */

578

} EBI_CS_t;

579

580

/* External Bus Interface */

581

typedef struct EBI_struct

582

{

583

register8_t CTRL; /* Control */

584

register8_t SDRAMCTRLA; /* SDRAM Control Register A */

585

register8_t reserved_0x02;

586

register8_t reserved_0x03;

587

_WORDREGISTER(REFRESH); /* SDRAM Refresh Period */

588

_WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */

589

register8_t SDRAMCTRLB; /* SDRAM Control Register B */

590

register8_t SDRAMCTRLC; /* SDRAM Control Register C */

591

register8_t reserved_0x0A;

592

register8_t reserved_0x0B;

593

register8_t reserved_0x0C;

594

register8_t reserved_0x0D;

595

register8_t reserved_0x0E;

596

register8_t reserved_0x0F;

597

EBI_CS_t CS0; /* Chip Select 0 */

598

EBI_CS_t CS1; /* Chip Select 1 */

599

EBI_CS_t CS2; /* Chip Select 2 */

600

EBI_CS_t CS3; /* Chip Select 3 */

601

} EBI_t;

602

603

/*

604

--------------------------------------------------------------------------

605

TWI - Two-Wire Interface

606

--------------------------------------------------------------------------

607

*/

608

609

/* */

610

typedef struct TWI_MASTER_struct

611

{

612

register8_t CTRLA; /* Control Register A */

613

register8_t CTRLB; /* Control Register B */

614

register8_t CTRLC; /* Control Register C */

615

register8_t STATUS; /* Status Register */

616

register8_t BAUD; /* Baurd Rate Control Register */

617

register8_t ADDR; /* Address Register */

618

register8_t DATA; /* Data Register */

619

} TWI_MASTER_t;

620

621

/* */

622

typedef struct TWI_SLAVE_struct

623

{

624

register8_t CTRLA; /* Control Register A */

625

register8_t CTRLB; /* Control Register B */

626

register8_t STATUS; /* Status Register */

627

register8_t ADDR; /* Address Register */

628

register8_t DATA; /* Data Register */

629

} TWI_SLAVE_t;

630

631

/* Two-Wire Interface */

632

typedef struct TWI_struct

633

{

634

register8_t CTRL; /* TWI Common Control Register */

635

TWI_MASTER_t MASTER; /* TWI master module */

636

TWI_SLAVE_t SLAVE; /* TWI slave module */

637

} TWI_t;

638

639

/*

640

--------------------------------------------------------------------------

641

PORT - Port Configuration

642

--------------------------------------------------------------------------

643

*/

644

645

/* I/O port Configuration */

646

typedef struct PORTCFG_struct

647

{

648

register8_t MPCMASK; /* Multi-pin Configuration Mask */

649

register8_t reserved_0x01;

650

register8_t VPCTRLA; /* Virtual Port Control Register A */

651

register8_t VPCTRLB; /* Virtual Port Control Register B */

652

register8_t CLKEVOUT; /* Clock and Event Out Register */

653

} PORTCFG_t;

654

655

/* Virtual Port */

656

typedef struct VPORT_struct

657

{

658

register8_t DIR; /* I/O Port Data Direction */

659

register8_t OUT; /* I/O Port Output */

660

register8_t IN; /* I/O Port Input */

661

register8_t INTFLAGS; /* Interrupt Flag Register */

662

} VPORT_t;

663

664

/* I/O Ports */

665

typedef struct PORT_struct

666

{

667

register8_t DIR; /* I/O Port Data Direction */

668

register8_t DIRSET; /* I/O Port Data Direction Set */

669

register8_t DIRCLR; /* I/O Port Data Direction Clear */

670

register8_t DIRTGL; /* I/O Port Data Direction Toggle */

671

register8_t OUT; /* I/O Port Output */

672

register8_t OUTSET; /* I/O Port Output Set */

673

register8_t OUTCLR; /* I/O Port Output Clear */

674

register8_t OUTTGL; /* I/O Port Output Toggle */

675

register8_t IN; /* I/O port Input */

676

register8_t INTCTRL; /* Interrupt Control Register */

677

register8_t INT0MASK; /* Port Interrupt 0 Mask */

678

register8_t INT1MASK; /* Port Interrupt 1 Mask */

679

register8_t INTFLAGS; /* Interrupt Flag Register */

680

register8_t reserved_0x0D;

681

register8_t reserved_0x0E;

682

register8_t reserved_0x0F;

683

register8_t PIN0CTRL; /* Pin 0 Control Register */

684

register8_t PIN1CTRL; /* Pin 1 Control Register */

685

register8_t PIN2CTRL; /* Pin 2 Control Register */

686

register8_t PIN3CTRL; /* Pin 3 Control Register */

687

register8_t PIN4CTRL; /* Pin 4 Control Register */

688

register8_t PIN5CTRL; /* Pin 5 Control Register */

689

register8_t PIN6CTRL; /* Pin 6 Control Register */

690

register8_t PIN7CTRL; /* Pin 7 Control Register */

691

} PORT_t;

692

693

/*

694

--------------------------------------------------------------------------

695

TC - 16-bit Timer/Counter With PWM

696

--------------------------------------------------------------------------

697

*/

698

699

/* 16-bit Timer/Counter 0 */

700

typedef struct TC0_struct

701

{

702

register8_t CTRLA; /* Control Register A */

703

register8_t CTRLB; /* Control Register B */

704

register8_t CTRLC; /* Control register C */

705

register8_t CTRLD; /* Control Register D */

706

register8_t CTRLE; /* Control Register E */

707

register8_t reserved_0x05;

708

register8_t INTCTRLA; /* Interrupt Control Register A */

709

register8_t INTCTRLB; /* Interrupt Control Register B */

710

register8_t CTRLFCLR; /* Control Register F Clear */

711

register8_t CTRLFSET; /* Control Register F Set */

712

register8_t CTRLGCLR; /* Control Register G Clear */

713

register8_t CTRLGSET; /* Control Register G Set */

714

register8_t INTFLAGS; /* Interrupt Flag Register */

715

register8_t reserved_0x0D;

716

register8_t reserved_0x0E;

717

register8_t TEMP; /* Temporary Register For 16-bit Access */

718

register8_t reserved_0x10;

719

register8_t reserved_0x11;

720

register8_t reserved_0x12;

721

register8_t reserved_0x13;

722

register8_t reserved_0x14;

723

register8_t reserved_0x15;

724

register8_t reserved_0x16;

725

register8_t reserved_0x17;

726

register8_t reserved_0x18;

727

register8_t reserved_0x19;

728

register8_t reserved_0x1A;

729

register8_t reserved_0x1B;

730

register8_t reserved_0x1C;

731

register8_t reserved_0x1D;

732

register8_t reserved_0x1E;

733

register8_t reserved_0x1F;

734

_WORDREGISTER(CNT); /* Count */

735

register8_t reserved_0x22;

736

register8_t reserved_0x23;

737

register8_t reserved_0x24;

738

register8_t reserved_0x25;

739

_WORDREGISTER(PER); /* Period */

740

_WORDREGISTER(CCA); /* Compare or Capture A */

741

_WORDREGISTER(CCB); /* Compare or Capture B */

742

_WORDREGISTER(CCC); /* Compare or Capture C */

743

_WORDREGISTER(CCD); /* Compare or Capture D */

744

register8_t reserved_0x30;

745

register8_t reserved_0x31;

746

register8_t reserved_0x32;

747

register8_t reserved_0x33;

748

register8_t reserved_0x34;

749

register8_t reserved_0x35;

750

_WORDREGISTER(PERBUF); /* Period Buffer */

751

_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */

752

_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */

753

_WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */

754

_WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */

755

} TC0_t;

756

757

/* 16-bit Timer/Counter 1 */

758

typedef struct TC1_struct

759

{

760

register8_t CTRLA; /* Control Register A */

761

register8_t CTRLB; /* Control Register B */

762

register8_t CTRLC; /* Control register C */

763

register8_t CTRLD; /* Control Register D */

764

register8_t CTRLE; /* Control Register E */

765

register8_t reserved_0x05;

766

register8_t INTCTRLA; /* Interrupt Control Register A */

767

register8_t INTCTRLB; /* Interrupt Control Register B */

768

register8_t CTRLFCLR; /* Control Register F Clear */

769

register8_t CTRLFSET; /* Control Register F Set */

770

register8_t CTRLGCLR; /* Control Register G Clear */

771

register8_t CTRLGSET; /* Control Register G Set */

772

register8_t INTFLAGS; /* Interrupt Flag Register */

773

register8_t reserved_0x0D;

774

register8_t reserved_0x0E;

775

register8_t TEMP; /* Temporary Register For 16-bit Access */

776

register8_t reserved_0x10;

777

register8_t reserved_0x11;

778

register8_t reserved_0x12;

779

register8_t reserved_0x13;

780

register8_t reserved_0x14;

781

register8_t reserved_0x15;

782

register8_t reserved_0x16;

783

register8_t reserved_0x17;

784

register8_t reserved_0x18;

785

register8_t reserved_0x19;

786

register8_t reserved_0x1A;

787

register8_t reserved_0x1B;

788

register8_t reserved_0x1C;

789

register8_t reserved_0x1D;

790

register8_t reserved_0x1E;

791

register8_t reserved_0x1F;

792

_WORDREGISTER(CNT); /* Count */

793

register8_t reserved_0x22;

794

register8_t reserved_0x23;

795

register8_t reserved_0x24;

796

register8_t reserved_0x25;

797

_WORDREGISTER(PER); /* Period */

798

_WORDREGISTER(CCA); /* Compare or Capture A */

799

_WORDREGISTER(CCB); /* Compare or Capture B */

800

register8_t reserved_0x2C;

801

register8_t reserved_0x2D;

802

register8_t reserved_0x2E;

803

register8_t reserved_0x2F;

804

register8_t reserved_0x30;

805

register8_t reserved_0x31;

806

register8_t reserved_0x32;

807

register8_t reserved_0x33;

808

register8_t reserved_0x34;

809

register8_t reserved_0x35;

810

_WORDREGISTER(PERBUF); /* Period Buffer */

811

_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */

812

_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */

813

} TC1_t;

814

815

/* Advanced Waveform Extension */

816

typedef struct AWEX_struct

817

{

818

register8_t CTRL; /* Control Register */

819

register8_t reserved_0x01;

820

register8_t FDEVMASK; /* Fault Detection Event Mask */

821

register8_t DFCTRL; /* Fault Detection Control Register */

822

register8_t STATUS; /* Status Register */

823

register8_t reserved_0x05;

824

register8_t DTBOTH; /* Dead Time Both Sides */

825

register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */

826

register8_t DTLS; /* Dead Time Low Side */

827

register8_t DTHS; /* Dead Time High Side */

828

register8_t DTLSBUF; /* Dead Time Low Side Buffer */

829

register8_t DTHSBUF; /* Dead Time High Side Buffer */

830

register8_t OUTOVEN; /* Output Override Enable */

831

} AWEX_t;

832

833

/* High-Resolution Extension */

834

typedef struct HIRES_struct

835

{

836

register8_t CTRL; /* Control Register */

837

} HIRES_t;

838

839

/*

840

--------------------------------------------------------------------------

841

USART - Universal Asynchronous Receiver-Transmitter

842

--------------------------------------------------------------------------

843

*/

844

845

/* Universal Synchronous/Asynchronous Receiver/Transmitter */

846

typedef struct USART_struct

847

{

848

register8_t DATA; /* Data Register */

849

register8_t STATUS; /* Status Register */

850

register8_t reserved_0x02;

851

register8_t CTRLA; /* Control Register A */

852

register8_t CTRLB; /* Control Register B */

853

register8_t CTRLC; /* Control Register C */

854

register8_t BAUDCTRLA; /* Baud Rate Control Register A */

855

register8_t BAUDCTRLB; /* Baud Rate Control Register B */

856

} USART_t;

857

858

/*

859

--------------------------------------------------------------------------

860

SPI - Serial Peripheral Interface

861

--------------------------------------------------------------------------

862

*/

863

864

/* Serial Peripheral Interface */

865

typedef struct SPI_struct

866

{

867

register8_t CTRL; /* Control Register */

868

register8_t INTCTRL; /* Interrupt Control Register */

869

register8_t STATUS; /* Status Register */

870

register8_t DATA; /* Data Register */

871

} SPI_t;

872

873

/*

874

--------------------------------------------------------------------------

875

IRCOM - IR Communication Module

876

--------------------------------------------------------------------------

877

*/

878

879

/* IR Communication Module */

880

typedef struct IRCOM_struct

881

{

882

register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */

883

register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */

884

register8_t CTRL; /* Control Register */

885

} IRCOM_t;

886

887

/*

888

--------------------------------------------------------------------------

889

AES - AES Module

890

--------------------------------------------------------------------------

891

*/

892

893

/* AES MOdule */

894

typedef struct AES_struct

895

{

896

register8_t CTRL; /* AES Control Register */

897

register8_t STATUS; /* AES Status Register */

898

register8_t STATE; /* AES State Register */

899

register8_t KEY; /* AES Key Register */

900

register8_t INTCTRL; /* AES Interrupt Control Register */

901

} AES_t;

902

903

904

905

/*

906

==========================================================================

907

IO Module Instances. Mapped to memory.

908

==========================================================================

909

*/

910

911

912

#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */

913

#define CLK (*(CLK_t *) 0x0040) /* Clock System */

914

#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */

915

#define OSC (*(OSC_t *) 0x0050) /* Oscillator */

916

#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz Clock */

917

#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz Internal RC */

918

#define PR (*(PR_t *) 0x0070) /* Power Reduction */

919

#define RST (*(RST_t *) 0x0078) /* Reset Controller */

920

#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */

921

#define MCU (*(MCU_t *) 0x0090) /* MCU Revision */

922

#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */

923

#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */

924

#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */

925

#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory */

926

#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */

927

#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */

928

#define ADCA (*(ADC_t *) 0x0200) /* Analog/Digital Converter A */

929

#define ADCB (*(ADC_t *) 0x0240) /* Analog/Digital Converter B */

930

#define DACA (*(DAC_t *) 0x0300) /* Digital/Analog Converter A */

931

#define DACB (*(DAC_t *) 0x0320) /* Digital/Analog Converter B */

932

#define RTC (*(RTC_t *) 0x0400) /* Real-Time Clock */

933

#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */

934

#define TWIC (*(TWI_t *) 0x480) /* Two-Wire Interface C */

935

#define TWID (*(TWI_t *) 0x490) /* Two-Wire Interface D */

936

#define TWIE (*(TWI_t *) 0x4A0) /* Two-Wire Interface E */

937

#define TWIF (*(TWI_t *) 0x4B0) /* Two-Wire Interface F */

938

#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */

939

#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */

940

#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */

941

#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */

942

#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */

943

#define PORTA (*(PORT_t *) 0x0600) /* Port A */

944

#define PORTB (*(PORT_t *) 0x0620) /* Port B */

945

#define PORTC (*(PORT_t *) 0x0640) /* Port C */

946

#define PORTD (*(PORT_t *) 0x0660) /* Port D */

947

#define PORTE (*(PORT_t *) 0x0680) /* Port E */

948

#define PORTF (*(PORT_t *) 0x06A0) /* Port F */

949

#define PORTH (*(PORT_t *) 0x06E0) /* Port H */

950

#define PORTJ (*(PORT_t *) 0x0700) /* Port J */

951

#define PORTK (*(PORT_t *) 0x0720) /* Port K */

952

#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */

953

#define PORTR (*(PORT_t *) 0x07E0) /* Port R */

954

#define TCC0 (*(TC0_t *) 0x800) /* 16-bit Timer/Counter With PWM C0 */

955

#define TCC1 (*(TC1_t *) 0x840) /* 16-bit Timer/Counter With PWM C1 */

956

#define AWEXC (*(AWEX_t *) 0x880) /* Advanced Waveform Extension C */

957

#define HIRESC (*(HIRES_t *) 0x890) /* High-Resolution PWM C */

958

#define USARTC0 (*(USART_t *) 0x8A0) /* Universal Asynchronous Receiver-Transmitter C0 */

959

#define USARTC1 (*(USART_t *) 0x8B0) /* Universal Asynchronous Receiver-Transmitter C1 */

960

#define SPIC (*(SPI_t *) 0x8C0) /* Serial Peripheral Interface C */

961

#define TCD0 (*(TC0_t *) 0x900) /* 16-bit Timer/Counter With PWM D0 */

962

#define TCD1 (*(TC1_t *) 0x940) /* 16-bit Timer/Counter With PWM D1 */

963

#define HIRESD (*(HIRES_t *) 0x990) /* High-Resolution PWM D */

964

#define USARTD0 (*(USART_t *) 0x9A0) /* Universal Asynchronous Receiver-Transmitter D0 */

965

#define USARTD1 (*(USART_t *) 0x9B0) /* Universal Asynchronous Receiver-Transmitter D1 */

966

#define SPID (*(SPI_t *) 0x9C0) /* Serial Peripheral Interface D */

967

#define TCE0 (*(TC0_t *) 0xA00) /* 16-bit Timer/Counter With PWM E0 */

968

#define TCE1 (*(TC1_t *) 0xA40) /* 16-bit Timer/Counter With PWM E1 */

969

#define AWEXE (*(AWEX_t *) 0xA80) /* Advanced Waveform Extension E */

970

#define HIRESE (*(HIRES_t *) 0xA90) /* High-Resolution PWM E */

971

#define USARTE0 (*(USART_t *) 0xAA0) /* Universal Asynchronous Receiver-Transmitter E0 */

972

#define USARTE1 (*(USART_t *) 0xAB0) /* Universal Asynchronous Receiver-Transmitter E1 */

973

#define SPIE (*(SPI_t *) 0xAC0) /* Serial Peripheral Interface E */

974

#define TCF0 (*(TC0_t *) 0xB00) /* 16-bit Timer/Counter With PWM F0 */

975

#define TCF1 (*(TC1_t *) 0xB40) /* 16-bit Timer/Counter With PWM F1 */

976

#define HIRESF (*(HIRES_t *) 0xB90) /* High-Resolution PWM F */

977

#define USARTF0 (*(USART_t *) 0xBA0) /* Universal Asynchronous Receiver-Transmitter F0 */

978

#define USARTF1 (*(USART_t *) 0xBB0) /* Universal Asynchronous Receiver-Transmitter F1 */

979

#define SPIF (*(SPI_t *) 0xBC0) /* Serial Peripheral Interface F */

980

#define IRCOM (*(IRCOM_t *) 0x8F0) /* IR Communication Module */

981

#define AES (*(AES_t *) 0x0C0) /* AES Crypto Module */

982

983

984

/* ========== IO register and sub-module fully qualified names ========== */

985

986

987

// OCD - On-Chip Debug System

988

#define OCD_OCDR0 OCD.OCDR0

989

#define OCD_OCDR1 OCD.OCDR1

990

991

// CLK - Clock System

992

#define CLK_CTRL CLK.CTRL

993

#define CLK_PSCTRL CLK.PSCTRL

994

#define CLK_LOCK CLK.LOCK

995

#define CLK_RTCCTRL CLK.RTCCTRL

996

997

// SLEEP - Sleep Controller

998

#define SLEEP_CTRL SLEEP.CTRL

999

1000

// OSC - Oscillator

1001

#define OSC_CTRL OSC.CTRL

1002

#define OSC_STATUS OSC.STATUS

1003

#define OSC_XOSCCTRL OSC.XOSCCTRL

1004

#define OSC_XOSCFAIL OSC.XOSCFAIL

1005

#define OSC_RC32KCAL OSC.RC32KCAL

1006

#define OSC_PLLCTRL OSC.PLLCTRL

1007

#define OSC_DFLLCTRL OSC.DFLLCTRL

1008

1009

// DFLLRC32M - DFLL for 32MHz Clock

1010

#define DFLLRC32M_OSCCNT0 DFLLRC32M.OSCCNT0

1011

#define DFLLRC32M_OSCCNT1 DFLLRC32M.OSCCNT1

1012

#define DFLLRC32M_OSCCNT2 DFLLRC32M.OSCCNT2

1013

#define DFLLRC32M_CALA DFLLRC32M.CALA

1014

#define DFLLRC32M_CALB DFLLRC32M.CALB

1015

1016

// DFLLRC2M - DFLL for 2MHz Internal RC

1017

#define DFLLRC2M_OSCCNT0 DFLLRC2M.OSCCNT0

1018

#define DFLLRC2M_OSCCNT1 DFLLRC2M.OSCCNT1

1019

#define DFLLRC2M_OSCCNT2 DFLLRC2M.OSCCNT2

1020

#define DFLLRC2M_CALA DFLLRC2M.CALA

1021

#define DFLLRC2M_CALB DFLLRC2M.CALB

1022

1023

// PR - Power Reduction

1024

#define PR_PR PR.PR

1025

#define PR_PRPA PR.PRPA

1026

#define PR_PRPB PR.PRPB

1027

#define PR_PRPC PR.PRPC

1028

#define PR_PRPD PR.PRPD

1029

#define PR_PRPE PR.PRPE

1030

#define PR_PRPF PR.PRPF

1031

1032

// RST - Reset Controller

1033

#define RST_STATUS RST.STATUS

1034

#define RST_CTRL RST.CTRL

1035

1036

// WDT - Watch-Dog Timer

1037

#define WDT_CTRL WDT.CTRL

1038

#define WDT_WINCTRL WDT.WINCTRL

1039

#define WDT_STATUS WDT.STATUS

1040

1041

// MCU - MCU Revision

1042

#define MCU_DEVID0 MCU.DEVID0

1043

#define MCU_DEVID1 MCU.DEVID1

1044

#define MCU_DEVID2 MCU.DEVID2

1045

#define MCU_REVID MCU.REVID

1046

#define MCU_JTAGUID MCU.JTAGUID

1047

#define MCU_MCUCR MCU.MCUCR

1048

#define MCU_EVSYSLOCK MCU.EVSYSLOCK

1049

#define MCU_AWEXLOCK MCU.AWEXLOCK

1050

1051

// PMIC - Programmable Interrupt Controller

1052

#define PMIC_STATUS PMIC.STATUS

1053

#define PMIC_INTPRI PMIC.INTPRI

1054

#define PMIC_CTRL PMIC.CTRL

1055

1056

// DMA - DMA Controller

1057

#define DMA_CTRL DMA.CTRL

1058

#define DMA_INTFLAGS DMA.INTFLAGS

1059

#define DMA_STATUS DMA.STATUS

1060

1061

// EVSYS - Event System

1062

#define EVSYS_CH0MUX EVSYS.CH0MUX

1063

#define EVSYS_CH1MUX EVSYS.CH1MUX

1064

#define EVSYS_CH2MUX EVSYS.CH2MUX

1065

#define EVSYS_CH3MUX EVSYS.CH3MUX

1066

#define EVSYS_CH4MUX EVSYS.CH4MUX

1067

#define EVSYS_CH5MUX EVSYS.CH5MUX

1068

#define EVSYS_CH6MUX EVSYS.CH6MUX

1069

#define EVSYS_CH7MUX EVSYS.CH7MUX

1070

#define EVSYS_CH0CTRL EVSYS.CH0CTRL

1071

#define EVSYS_CH1CTRL EVSYS.CH1CTRL

1072

#define EVSYS_CH2CTRL EVSYS.CH2CTRL

1073

#define EVSYS_CH3CTRL EVSYS.CH3CTRL

1074

#define EVSYS_CH4CTRL EVSYS.CH4CTRL

1075

#define EVSYS_CH5CTRL EVSYS.CH5CTRL

1076

#define EVSYS_CH6CTRL EVSYS.CH6CTRL

1077

#define EVSYS_CH7CTRL EVSYS.CH7CTRL

1078

#define EVSYS_STROBE EVSYS.STROBE

1079

#define EVSYS_DATA EVSYS.DATA

1080

1081

// NVM - Non Volatile Memory

1082

#define NVM_ADDR0 NVM.ADDR0

1083

#define NVM_ADDR1 NVM.ADDR1

1084

#define NVM_ADDR2 NVM.ADDR2

1085

#define NVM_DATA0 NVM.DATA0

1086

#define NVM_DATA1 NVM.DATA1

1087

#define NVM_DATA2 NVM.DATA2

1088

#define NVM_CMD NVM.CMD

1089

#define NVM_CTRLA NVM.CTRLA

1090

#define NVM_CTRLB NVM.CTRLB

1091

#define NVM_INTCTRL NVM.INTCTRL

1092

#define NVM_STATUS NVM.STATUS

1093

#define NVM_LOCKBITS NVM.LOCKBITS

1094

1095

// ACA - Analog Comparator A

1096

#define ACA_AC0CTRL ACA.AC0CTRL

1097

#define ACA_AC1CTRL ACA.AC1CTRL

1098

#define ACA_AC0MUXCTRL ACA.AC0MUXCTRL

1099

#define ACA_AC1MUXCTRL ACA.AC1MUXCTRL

1100

#define ACA_CTRLA ACA.CTRLA

1101

#define ACA_CTRLB ACA.CTRLB

1102

#define ACA_WINCTRL ACA.WINCTRL

1103

#define ACA_STATUS ACA.STATUS

1104

1105

// ACB - Analog Comparator B

1106

#define ACB_AC0CTRL ACB.AC0CTRL

1107

#define ACB_AC1CTRL ACB.AC1CTRL

1108

#define ACB_AC0MUXCTRL ACB.AC0MUXCTRL

1109

#define ACB_AC1MUXCTRL ACB.AC1MUXCTRL

1110

#define ACB_CTRLA ACB.CTRLA

1111

#define ACB_CTRLB ACB.CTRLB

1112

#define ACB_WINCTRL ACB.WINCTRL

1113

#define ACB_STATUS ACB.STATUS

1114

1115

// ADCA - Analog/Digital Converter A

1116

#define ADCA_CTRLA ADCA.CTRLA

1117

#define ADCA_CTRLB ADCA.CTRLB

1118

#define ADCA_REFCTRL ADCA.REFCTRL

1119

#define ADCA_EVCTRL ADCA.EVCTRL

1120

#define ADCA_PRESCALER ADCA.PRESCALER

1121

#define ADCA_CALCTRL ADCA.CALCTRL

1122

#define ADCA_INTFLAGS ADCA.INTFLAGS

1123

#define ADCA_CALIB ADCA.CALIB

1124

#define ADCA_CH0RES ADCA.CH0RES

1125

#define ADCA_CH1RES ADCA.CH1RES

1126

#define ADCA_CH2RES ADCA.CH2RES

1127

#define ADCA_CH3RES ADCA.CH3RES

1128

#define ADCA_CMP ADCA.CMP

1129

1130

// ADCB - Analog/Digital Converter B

1131

#define ADCB_CTRLA ADCB.CTRLA

1132

#define ADCB_CTRLB ADCB.CTRLB

1133

#define ADCB_REFCTRL ADCB.REFCTRL

1134

#define ADCB_EVCTRL ADCB.EVCTRL

1135

#define ADCB_PRESCALER ADCB.PRESCALER

1136

#define ADCB_CALCTRL ADCB.CALCTRL

1137

#define ADCB_INTFLAGS ADCB.INTFLAGS

1138

#define ADCB_CALIB ADCB.CALIB

1139

#define ADCB_CH0RES ADCB.CH0RES

1140

#define ADCB_CH1RES ADCB.CH1RES

1141

#define ADCB_CH2RES ADCB.CH2RES

1142

#define ADCB_CH3RES ADCB.CH3RES

1143

#define ADCB_CMP ADCB.CMP

1144

1145

// DACA - Digital/Analog Converter A

1146

#define DACA_CTRLA DACA.CTRLA

1147

#define DACA_CTRLB DACA.CTRLB

1148

#define DACA_CTRLC DACA.CTRLC

1149

#define DACA_EVCTRL DACA.EVCTRL

1150

#define DACA_TIMCTRL DACA.TIMCTRL

1151

#define DACA_STATUS DACA.STATUS

1152

#define DACA_GAINCAL DACA.GAINCAL

1153

#define DACA_OFFSETCAL DACA.OFFSETCAL

1154

#define DACA_CH0DATA DACA.CH0DATA

1155

#define DACA_CH1DATA DACA.CH1DATA

1156

1157

// DACB - Digital/Analog Converter B

1158

#define DACB_CTRLA DACB.CTRLA

1159

#define DACB_CTRLB DACB.CTRLB

1160

#define DACB_CTRLC DACB.CTRLC

1161

#define DACB_EVCTRL DACB.EVCTRL

1162

#define DACB_TIMCTRL DACB.TIMCTRL

1163

#define DACB_STATUS DACB.STATUS

1164

#define DACB_GAINCAL DACB.GAINCAL

1165

#define DACB_OFFSETCAL DACB.OFFSETCAL

1166

#define DACB_CH0DATA DACB.CH0DATA

1167

#define DACB_CH1DATA DACB.CH1DATA

1168

1169

// RTC - Real-Time Clock

1170

#define RTC_CTRL RTC.CTRL

1171

#define RTC_STATUS RTC.STATUS

1172

#define RTC_INTCTRL RTC.INTCTRL

1173

#define RTC_INTFLAGS RTC.INTFLAGS

1174

#define RTC_TEMP RTC.TEMP

1175

#define RTC_CNT RTC.CNT

1176

#define RTC_PER RTC.PER

1177

#define RTC_COMP RTC.COMP

1178

1179

// EBI - External Bus Interface

1180

#define EBI_CTRL EBI.CTRL

1181

#define EBI_SDRAMCTRLA EBI.SDRAMCTRLA

1182

#define EBI_REFRESH EBI.REFRESH

1183

#define EBI_INITDLY EBI.INITDLY

1184

#define EBI_SDRAMCTRLB EBI.SDRAMCTRLB

1185

#define EBI_SDRAMCTRLC EBI.SDRAMCTRLC

1186

1187

// TWIC - Two-Wire Interface C

1188

#define TWIC_CTRL TWIC.CTRL

1189

1190

// TWID - Two-Wire Interface D

1191

#define TWID_CTRL TWID.CTRL

1192

1193

// TWIE - Two-Wire Interface E

1194

#define TWIE_CTRL TWIE.CTRL

1195

1196

// TWIF - Two-Wire Interface F

1197

#define TWIF_CTRL TWIF.CTRL

1198

1199

// PORTCFG - Port Configuration

1200

#define PORTCFG_MPCMASK PORTCFG.MPCMASK

1201

#define PORTCFG_VPCTRLA PORTCFG.VPCTRLA

1202

#define PORTCFG_VPCTRLB PORTCFG.VPCTRLB

1203

#define PORTCFG_CLKEVOUT PORTCFG.CLKEVOUT

1204

1205

// VPORT0 - Virtual Port 0

1206

#define VPORT0_DIR VPORT0.DIR

1207

#define VPORT0_OUT VPORT0.OUT

1208

#define VPORT0_IN VPORT0.IN

1209

#define VPORT0_INTFLAGS VPORT0.INTFLAGS

1210

1211

// VPORT1 - Virtual Port 1

1212

#define VPORT1_DIR VPORT1.DIR

1213

#define VPORT1_OUT VPORT1.OUT

1214

#define VPORT1_IN VPORT1.IN

1215

#define VPORT1_INTFLAGS VPORT1.INTFLAGS

1216

1217

// VPORT2 - Virtual Port 2

1218

#define VPORT2_DIR VPORT2.DIR

1219

#define VPORT2_OUT VPORT2.OUT

1220

#define VPORT2_IN VPORT2.IN

1221

#define VPORT2_INTFLAGS VPORT2.INTFLAGS

1222

1223

// VPORT3 - Virtual Port 3

1224

#define VPORT3_DIR VPORT3.DIR

1225

#define VPORT3_OUT VPORT3.OUT

1226

#define VPORT3_IN VPORT3.IN

1227

#define VPORT3_INTFLAGS VPORT3.INTFLAGS

1228

1229

// PORTA - Port A

1230

#define PORTA_DIR PORTA.DIR

1231

#define PORTA_DIRSET PORTA.DIRSET

1232

#define PORTA_DIRCLR PORTA.DIRCLR

1233

#define PORTA_DIRTGL PORTA.DIRTGL

1234

#define PORTA_OUT PORTA.OUT

1235

#define PORTA_OUTSET PORTA.OUTSET

1236

#define PORTA_OUTCLR PORTA.OUTCLR

1237

#define PORTA_OUTTGL PORTA.OUTTGL

1238

#define PORTA_IN PORTA.IN

1239

#define PORTA_INTCTRL PORTA.INTCTRL

1240

#define PORTA_INT0MASK PORTA.INT0MASK

1241

#define PORTA_INT1MASK PORTA.INT1MASK

1242

#define PORTA_INTFLAGS PORTA.INTFLAGS

1243

#define PORTA_PIN0CTRL PORTA.PIN0CTRL

1244

#define PORTA_PIN1CTRL PORTA.PIN1CTRL

1245

#define PORTA_PIN2CTRL PORTA.PIN2CTRL

1246

#define PORTA_PIN3CTRL PORTA.PIN3CTRL

1247

#define PORTA_PIN4CTRL PORTA.PIN4CTRL

1248

#define PORTA_PIN5CTRL PORTA.PIN5CTRL

1249

#define PORTA_PIN6CTRL PORTA.PIN6CTRL

1250

#define PORTA_PIN7CTRL PORTA.PIN7CTRL

1251

1252

// PORTB - Port B

1253

#define PORTB_DIR PORTB.DIR

1254

#define PORTB_DIRSET PORTB.DIRSET

1255

#define PORTB_DIRCLR PORTB.DIRCLR

1256

#define PORTB_DIRTGL PORTB.DIRTGL

1257

#define PORTB_OUT PORTB.OUT

1258

#define PORTB_OUTSET PORTB.OUTSET

1259

#define PORTB_OUTCLR PORTB.OUTCLR

1260

#define PORTB_OUTTGL PORTB.OUTTGL

1261

#define PORTB_IN PORTB.IN

1262

#define PORTB_INTCTRL PORTB.INTCTRL

1263

#define PORTB_INT0MASK PORTB.INT0MASK

1264

#define PORTB_INT1MASK PORTB.INT1MASK

1265

#define PORTB_INTFLAGS PORTB.INTFLAGS

1266

#define PORTB_PIN0CTRL PORTB.PIN0CTRL

1267

#define PORTB_PIN1CTRL PORTB.PIN1CTRL

1268

#define PORTB_PIN2CTRL PORTB.PIN2CTRL

1269

#define PORTB_PIN3CTRL PORTB.PIN3CTRL

1270

#define PORTB_PIN4CTRL PORTB.PIN4CTRL

1271

#define PORTB_PIN5CTRL PORTB.PIN5CTRL

1272

#define PORTB_PIN6CTRL PORTB.PIN6CTRL

1273

#define PORTB_PIN7CTRL PORTB.PIN7CTRL

1274

1275

// PORTC - Port C

1276

#define PORTC_DIR PORTC.DIR

1277

#define PORTC_DIRSET PORTC.DIRSET

1278

#define PORTC_DIRCLR PORTC.DIRCLR

1279

#define PORTC_DIRTGL PORTC.DIRTGL

1280

#define PORTC_OUT PORTC.OUT

1281

#define PORTC_OUTSET PORTC.OUTSET

1282

#define PORTC_OUTCLR PORTC.OUTCLR

1283

#define PORTC_OUTTGL PORTC.OUTTGL

1284

#define PORTC_IN PORTC.IN

1285

#define PORTC_INTCTRL PORTC.INTCTRL

1286

#define PORTC_INT0MASK PORTC.INT0MASK

1287

#define PORTC_INT1MASK PORTC.INT1MASK

1288

#define PORTC_INTFLAGS PORTC.INTFLAGS

1289

#define PORTC_PIN0CTRL PORTC.PIN0CTRL

1290

#define PORTC_PIN1CTRL PORTC.PIN1CTRL

1291

#define PORTC_PIN2CTRL PORTC.PIN2CTRL

1292

#define PORTC_PIN3CTRL PORTC.PIN3CTRL

1293

#define PORTC_PIN4CTRL PORTC.PIN4CTRL

1294

#define PORTC_PIN5CTRL PORTC.PIN5CTRL

1295

#define PORTC_PIN6CTRL PORTC.PIN6CTRL

1296

#define PORTC_PIN7CTRL PORTC.PIN7CTRL

1297

1298

// PORTD - Port D

1299

#define PORTD_DIR PORTD.DIR

1300

#define PORTD_DIRSET PORTD.DIRSET

1301

#define PORTD_DIRCLR PORTD.DIRCLR

1302

#define PORTD_DIRTGL PORTD.DIRTGL

1303

#define PORTD_OUT PORTD.OUT

1304

#define PORTD_OUTSET PORTD.OUTSET

1305

#define PORTD_OUTCLR PORTD.OUTCLR

1306

#define PORTD_OUTTGL PORTD.OUTTGL

1307

#define PORTD_IN PORTD.IN

1308

#define PORTD_INTCTRL PORTD.INTCTRL

1309

#define PORTD_INT0MASK PORTD.INT0MASK

1310

#define PORTD_INT1MASK PORTD.INT1MASK

1311

#define PORTD_INTFLAGS PORTD.INTFLAGS

1312

#define PORTD_PIN0CTRL PORTD.PIN0CTRL

1313

#define PORTD_PIN1CTRL PORTD.PIN1CTRL

1314

#define PORTD_PIN2CTRL PORTD.PIN2CTRL

1315

#define PORTD_PIN3CTRL PORTD.PIN3CTRL

1316

#define PORTD_PIN4CTRL PORTD.PIN4CTRL

1317

#define PORTD_PIN5CTRL PORTD.PIN5CTRL

1318

#define PORTD_PIN6CTRL PORTD.PIN6CTRL

1319

#define PORTD_PIN7CTRL PORTD.PIN7CTRL

1320

1321

// PORTE - Port E

1322

#define PORTE_DIR PORTE.DIR

1323

#define PORTE_DIRSET PORTE.DIRSET

1324

#define PORTE_DIRCLR PORTE.DIRCLR

1325

#define PORTE_DIRTGL PORTE.DIRTGL

1326

#define PORTE_OUT PORTE.OUT

1327

#define PORTE_OUTSET PORTE.OUTSET

1328

#define PORTE_OUTCLR PORTE.OUTCLR

1329

#define PORTE_OUTTGL PORTE.OUTTGL

1330

#define PORTE_IN PORTE.IN

1331

#define PORTE_INTCTRL PORTE.INTCTRL

1332

#define PORTE_INT0MASK PORTE.INT0MASK

1333

#define PORTE_INT1MASK PORTE.INT1MASK

1334

#define PORTE_INTFLAGS PORTE.INTFLAGS

1335

#define PORTE_PIN0CTRL PORTE.PIN0CTRL

1336

#define PORTE_PIN1CTRL PORTE.PIN1CTRL

1337

#define PORTE_PIN2CTRL PORTE.PIN2CTRL

1338

#define PORTE_PIN3CTRL PORTE.PIN3CTRL

1339

#define PORTE_PIN4CTRL PORTE.PIN4CTRL

1340

#define PORTE_PIN5CTRL PORTE.PIN5CTRL

1341

#define PORTE_PIN6CTRL PORTE.PIN6CTRL

1342

#define PORTE_PIN7CTRL PORTE.PIN7CTRL

1343

1344

// PORTF - Port F

1345

#define PORTF_DIR PORTF.DIR

1346

#define PORTF_DIRSET PORTF.DIRSET

1347

#define PORTF_DIRCLR PORTF.DIRCLR

1348

#define PORTF_DIRTGL PORTF.DIRTGL

1349

#define PORTF_OUT PORTF.OUT

1350

#define PORTF_OUTSET PORTF.OUTSET

1351

#define PORTF_OUTCLR PORTF.OUTCLR

1352

#define PORTF_OUTTGL PORTF.OUTTGL

1353

#define PORTF_IN PORTF.IN

1354

#define PORTF_INTCTRL PORTF.INTCTRL

1355

#define PORTF_INT0MASK PORTF.INT0MASK

1356

#define PORTF_INT1MASK PORTF.INT1MASK

1357

#define PORTF_INTFLAGS PORTF.INTFLAGS

1358

#define PORTF_PIN0CTRL PORTF.PIN0CTRL

1359

#define PORTF_PIN1CTRL PORTF.PIN1CTRL

1360

#define PORTF_PIN2CTRL PORTF.PIN2CTRL

1361

#define PORTF_PIN3CTRL PORTF.PIN3CTRL

1362

#define PORTF_PIN4CTRL PORTF.PIN4CTRL

1363

#define PORTF_PIN5CTRL PORTF.PIN5CTRL

1364

#define PORTF_PIN6CTRL PORTF.PIN6CTRL

1365

#define PORTF_PIN7CTRL PORTF.PIN7CTRL

1366

1367

// PORTH - Port H

1368

#define PORTH_DIR PORTH.DIR

1369

#define PORTH_DIRSET PORTH.DIRSET

1370

#define PORTH_DIRCLR PORTH.DIRCLR

1371

#define PORTH_DIRTGL PORTH.DIRTGL

1372

#define PORTH_OUT PORTH.OUT

1373

#define PORTH_OUTSET PORTH.OUTSET

1374

#define PORTH_OUTCLR PORTH.OUTCLR

1375

#define PORTH_OUTTGL PORTH.OUTTGL

1376

#define PORTH_IN PORTH.IN

1377

#define PORTH_INTCTRL PORTH.INTCTRL

1378

#define PORTH_INT0MASK PORTH.INT0MASK

1379

#define PORTH_INT1MASK PORTH.INT1MASK

1380

#define PORTH_INTFLAGS PORTH.INTFLAGS

1381

#define PORTH_PIN0CTRL PORTH.PIN0CTRL

1382

#define PORTH_PIN1CTRL PORTH.PIN1CTRL

1383

#define PORTH_PIN2CTRL PORTH.PIN2CTRL

1384

#define PORTH_PIN3CTRL PORTH.PIN3CTRL

1385

#define PORTH_PIN4CTRL PORTH.PIN4CTRL

1386

#define PORTH_PIN5CTRL PORTH.PIN5CTRL

1387

#define PORTH_PIN6CTRL PORTH.PIN6CTRL

1388

#define PORTH_PIN7CTRL PORTH.PIN7CTRL

1389

1390

// PORTJ - Port J

1391

#define PORTJ_DIR PORTJ.DIR

1392

#define PORTJ_DIRSET PORTJ.DIRSET

1393

#define PORTJ_DIRCLR PORTJ.DIRCLR

1394

#define PORTJ_DIRTGL PORTJ.DIRTGL

1395

#define PORTJ_OUT PORTJ.OUT

1396

#define PORTJ_OUTSET PORTJ.OUTSET

1397

#define PORTJ_OUTCLR PORTJ.OUTCLR

1398

#define PORTJ_OUTTGL PORTJ.OUTTGL

1399

#define PORTJ_IN PORTJ.IN

1400

#define PORTJ_INTCTRL PORTJ.INTCTRL

1401

#define PORTJ_INT0MASK PORTJ.INT0MASK

1402

#define PORTJ_INT1MASK PORTJ.INT1MASK

1403

#define PORTJ_INTFLAGS PORTJ.INTFLAGS

1404

#define PORTJ_PIN0CTRL PORTJ.PIN0CTRL

1405

#define PORTJ_PIN1CTRL PORTJ.PIN1CTRL

1406

#define PORTJ_PIN2CTRL PORTJ.PIN2CTRL

1407

#define PORTJ_PIN3CTRL PORTJ.PIN3CTRL

1408

#define PORTJ_PIN4CTRL PORTJ.PIN4CTRL

1409

#define PORTJ_PIN5CTRL PORTJ.PIN5CTRL

1410

#define PORTJ_PIN6CTRL PORTJ.PIN6CTRL

1411

#define PORTJ_PIN7CTRL PORTJ.PIN7CTRL

1412

1413

// PORTK - Port K

1414

#define PORTK_DIR PORTK.DIR

1415

#define PORTK_DIRSET PORTK.DIRSET

1416

#define PORTK_DIRCLR PORTK.DIRCLR

1417

#define PORTK_DIRTGL PORTK.DIRTGL

1418

#define PORTK_OUT PORTK.OUT

1419

#define PORTK_OUTSET PORTK.OUTSET

1420

#define PORTK_OUTCLR PORTK.OUTCLR

1421

#define PORTK_OUTTGL PORTK.OUTTGL

1422

#define PORTK_IN PORTK.IN

1423

#define PORTK_INTCTRL PORTK.INTCTRL

1424

#define PORTK_INT0MASK PORTK.INT0MASK

1425

#define PORTK_INT1MASK PORTK.INT1MASK

1426

#define PORTK_INTFLAGS PORTK.INTFLAGS

1427

#define PORTK_PIN0CTRL PORTK.PIN0CTRL

1428

#define PORTK_PIN1CTRL PORTK.PIN1CTRL

1429

#define PORTK_PIN2CTRL PORTK.PIN2CTRL

1430

#define PORTK_PIN3CTRL PORTK.PIN3CTRL

1431

#define PORTK_PIN4CTRL PORTK.PIN4CTRL

1432

#define PORTK_PIN5CTRL PORTK.PIN5CTRL

1433

#define PORTK_PIN6CTRL PORTK.PIN6CTRL

1434

#define PORTK_PIN7CTRL PORTK.PIN7CTRL

1435

1436

// PORTQ - Port Q

1437

#define PORTQ_DIR PORTQ.DIR

1438

#define PORTQ_DIRSET PORTQ.DIRSET

1439

#define PORTQ_DIRCLR PORTQ.DIRCLR

1440

#define PORTQ_DIRTGL PORTQ.DIRTGL

1441

#define PORTQ_OUT PORTQ.OUT

1442

#define PORTQ_OUTSET PORTQ.OUTSET

1443

#define PORTQ_OUTCLR PORTQ.OUTCLR

1444

#define PORTQ_OUTTGL PORTQ.OUTTGL

1445

#define PORTQ_IN PORTQ.IN

1446

#define PORTQ_INTCTRL PORTQ.INTCTRL

1447

#define PORTQ_INT0MASK PORTQ.INT0MASK

1448

#define PORTQ_INT1MASK PORTQ.INT1MASK

1449

#define PORTQ_INTFLAGS PORTQ.INTFLAGS

1450

#define PORTQ_PIN0CTRL PORTQ.PIN0CTRL

1451

#define PORTQ_PIN1CTRL PORTQ.PIN1CTRL

1452

#define PORTQ_PIN2CTRL PORTQ.PIN2CTRL

1453

#define PORTQ_PIN3CTRL PORTQ.PIN3CTRL

1454

#define PORTQ_PIN4CTRL PORTQ.PIN4CTRL

1455

#define PORTQ_PIN5CTRL PORTQ.PIN5CTRL

1456

#define PORTQ_PIN6CTRL PORTQ.PIN6CTRL

1457

#define PORTQ_PIN7CTRL PORTQ.PIN7CTRL

1458

1459

// PORTR - Port R

1460

#define PORTR_DIR PORTR.DIR

1461

#define PORTR_DIRSET PORTR.DIRSET

1462

#define PORTR_DIRCLR PORTR.DIRCLR

1463

#define PORTR_DIRTGL PORTR.DIRTGL

1464

#define PORTR_OUT PORTR.OUT

1465

#define PORTR_OUTSET PORTR.OUTSET

1466

#define PORTR_OUTCLR PORTR.OUTCLR

1467

#define PORTR_OUTTGL PORTR.OUTTGL

1468

#define PORTR_IN PORTR.IN

1469

#define PORTR_INTCTRL PORTR.INTCTRL

1470

#define PORTR_INT0MASK PORTR.INT0MASK

1471

#define PORTR_INT1MASK PORTR.INT1MASK

1472

#define PORTR_INTFLAGS PORTR.INTFLAGS

1473

#define PORTR_PIN0CTRL PORTR.PIN0CTRL

1474

#define PORTR_PIN1CTRL PORTR.PIN1CTRL

1475

#define PORTR_PIN2CTRL PORTR.PIN2CTRL

1476

#define PORTR_PIN3CTRL PORTR.PIN3CTRL

1477

#define PORTR_PIN4CTRL PORTR.PIN4CTRL

1478

#define PORTR_PIN5CTRL PORTR.PIN5CTRL

1479

#define PORTR_PIN6CTRL PORTR.PIN6CTRL

1480

#define PORTR_PIN7CTRL PORTR.PIN7CTRL

1481

1482

// TCC0 - 16-bit Timer/Counter With PWM C0

1483

#define TCC0_CTRLA TCC0.CTRLA

1484

#define TCC0_CTRLB TCC0.CTRLB

1485

#define TCC0_CTRLC TCC0.CTRLC

1486

#define TCC0_CTRLD TCC0.CTRLD

1487

#define TCC0_CTRLE TCC0.CTRLE

1488

#define TCC0_INTCTRLA TCC0.INTCTRLA

1489

#define TCC0_INTCTRLB TCC0.INTCTRLB

1490

#define TCC0_CTRLFCLR TCC0.CTRLFCLR

1491

#define TCC0_CTRLFSET TCC0.CTRLFSET

1492

#define TCC0_CTRLGCLR TCC0.CTRLGCLR

1493

#define TCC0_CTRLGSET TCC0.CTRLGSET

1494

#define TCC0_INTFLAGS TCC0.INTFLAGS

1495

#define TCC0_TEMP TCC0.TEMP

1496

#define TCC0_CNT TCC0.CNT

1497

#define TCC0_PER TCC0.PER

1498

#define TCC0_CCA TCC0.CCA

1499

#define TCC0_CCB TCC0.CCB

1500

#define TCC0_CCC TCC0.CCC

1501

#define TCC0_CCD TCC0.CCD

1502

#define TCC0_PERBUF TCC0.PERBUF

1503

#define TCC0_CCABUF TCC0.CCABUF

1504

#define TCC0_CCBBUF TCC0.CCBBUF

1505

#define TCC0_CCCBUF TCC0.CCCBUF

1506

#define TCC0_CCDBUF TCC0.CCDBUF

1507

1508

// TCC1 - 16-bit Timer/Counter With PWM C1

1509

#define TCC1_CTRLA TCC1.CTRLA

1510

#define TCC1_CTRLB TCC1.CTRLB

1511

#define TCC1_CTRLC TCC1.CTRLC

1512

#define TCC1_CTRLD TCC1.CTRLD

1513

#define TCC1_CTRLE TCC1.CTRLE

1514

#define TCC1_INTCTRLA TCC1.INTCTRLA

1515

#define TCC1_INTCTRLB TCC1.INTCTRLB

1516

#define TCC1_CTRLFCLR TCC1.CTRLFCLR

1517

#define TCC1_CTRLFSET TCC1.CTRLFSET

1518

#define TCC1_CTRLGCLR TCC1.CTRLGCLR

1519

#define TCC1_CTRLGSET TCC1.CTRLGSET

1520

#define TCC1_INTFLAGS TCC1.INTFLAGS

1521

#define TCC1_TEMP TCC1.TEMP

1522

#define TCC1_CNT TCC1.CNT

1523

#define TCC1_PER TCC1.PER

1524

#define TCC1_CCA TCC1.CCA

1525

#define TCC1_CCB TCC1.CCB

1526

#define TCC1_PERBUF TCC1.PERBUF

1527

#define TCC1_CCABUF TCC1.CCABUF

1528

#define TCC1_CCBBUF TCC1.CCBBUF

1529

1530

// AWEXC - Advanced Waveform Extension C

1531

#define AWEXC_CTRL AWEXC.CTRL

1532

#define AWEXC_FDEVMASK AWEXC.FDEVMASK

1533

#define AWEXC_DFCTRL AWEXC.DFCTRL

1534

#define AWEXC_STATUS AWEXC.STATUS

1535

#define AWEXC_DTBOTH AWEXC.DTBOTH

1536

#define AWEXC_DTBOTHBUF AWEXC.DTBOTHBUF

1537

#define AWEXC_DTLS AWEXC.DTLS

1538

#define AWEXC_DTHS AWEXC.DTHS

1539

#define AWEXC_DTLSBUF AWEXC.DTLSBUF

1540

#define AWEXC_DTHSBUF AWEXC.DTHSBUF

1541

#define AWEXC_OUTOVEN AWEXC.OUTOVEN

1542

1543

// HIRESC - High-Resolution PWM C

1544

#define HIRESC_CTRL HIRESC.CTRL

1545

1546

// USARTC0 - Universal Asynchronous Receiver-Transmitter C0

1547

#define USARTC0_DATA USARTC0.DATA

1548

#define USARTC0_STATUS USARTC0.STATUS

1549

#define USARTC0_CTRLA USARTC0.CTRLA

1550

#define USARTC0_CTRLB USARTC0.CTRLB

1551

#define USARTC0_CTRLC USARTC0.CTRLC

1552

#define USARTC0_BAUDCTRLA USARTC0.BAUDCTRLA

1553

#define USARTC0_BAUDCTRLB USARTC0.BAUDCTRLB

1554

1555

// USARTC1 - Universal Asynchronous Receiver-Transmitter C1

1556

#define USARTC1_DATA USARTC1.DATA

1557

#define USARTC1_STATUS USARTC1.STATUS

1558

#define USARTC1_CTRLA USARTC1.CTRLA

1559

#define USARTC1_CTRLB USARTC1.CTRLB

1560

#define USARTC1_CTRLC USARTC1.CTRLC

1561

#define USARTC1_BAUDCTRLA USARTC1.BAUDCTRLA

1562

#define USARTC1_BAUDCTRLB USARTC1.BAUDCTRLB

1563

1564

// SPIC - Serial Peripheral Interface C

1565

#define SPIC_CTRL SPIC.CTRL

1566

#define SPIC_INTCTRL SPIC.INTCTRL

1567

#define SPIC_STATUS SPIC.STATUS

1568

#define SPIC_DATA SPIC.DATA

1569

1570

// TCD0 - 16-bit Timer/Counter With PWM D0

1571

#define TCD0_CTRLA TCD0.CTRLA

1572

#define TCD0_CTRLB TCD0.CTRLB

1573

#define TCD0_CTRLC TCD0.CTRLC

1574

#define TCD0_CTRLD TCD0.CTRLD

1575

#define TCD0_CTRLE TCD0.CTRLE

1576

#define TCD0_INTCTRLA TCD0.INTCTRLA

1577

#define TCD0_INTCTRLB TCD0.INTCTRLB

1578

#define TCD0_CTRLFCLR TCD0.CTRLFCLR

1579

#define TCD0_CTRLFSET TCD0.CTRLFSET

1580

#define TCD0_CTRLGCLR TCD0.CTRLGCLR

1581

#define TCD0_CTRLGSET TCD0.CTRLGSET

1582

#define TCD0_INTFLAGS TCD0.INTFLAGS

1583

#define TCD0_TEMP TCD0.TEMP

1584

#define TCD0_CNT TCD0.CNT

1585

#define TCD0_PER TCD0.PER

1586

#define TCD0_CCA TCD0.CCA

1587

#define TCD0_CCB TCD0.CCB

1588

#define TCD0_CCC TCD0.CCC

1589

#define TCD0_CCD TCD0.CCD

1590

#define TCD0_PERBUF TCD0.PERBUF

1591

#define TCD0_CCABUF TCD0.CCABUF

1592

#define TCD0_CCBBUF TCD0.CCBBUF

1593

#define TCD0_CCCBUF TCD0.CCCBUF

1594

#define TCD0_CCDBUF TCD0.CCDBUF

1595

1596

// TCD1 - 16-bit Timer/Counter With PWM D1

1597

#define TCD1_CTRLA TCD1.CTRLA

1598

#define TCD1_CTRLB TCD1.CTRLB

1599

#define TCD1_CTRLC TCD1.CTRLC

1600

#define TCD1_CTRLD TCD1.CTRLD

1601

#define TCD1_CTRLE TCD1.CTRLE

1602

#define TCD1_INTCTRLA TCD1.INTCTRLA

1603

#define TCD1_INTCTRLB TCD1.INTCTRLB

1604

#define TCD1_CTRLFCLR TCD1.CTRLFCLR

1605

#define TCD1_CTRLFSET TCD1.CTRLFSET

1606

#define TCD1_CTRLGCLR TCD1.CTRLGCLR

1607

#define TCD1_CTRLGSET TCD1.CTRLGSET

1608

#define TCD1_INTFLAGS TCD1.INTFLAGS

1609

#define TCD1_TEMP TCD1.TEMP

1610

#define TCD1_CNT TCD1.CNT

1611

#define TCD1_PER TCD1.PER

1612

#define TCD1_CCA TCD1.CCA

1613

#define TCD1_CCB TCD1.CCB

1614

#define TCD1_PERBUF TCD1.PERBUF

1615

#define TCD1_CCABUF TCD1.CCABUF

1616

#define TCD1_CCBBUF TCD1.CCBBUF

1617

1618

// HIRESD - High-Resolution PWM D

1619

#define HIRESD_CTRL HIRESD.CTRL

1620

1621

// USARTD0 - Universal Asynchronous Receiver-Transmitter D0

1622

#define USARTD0_DATA USARTD0.DATA

1623

#define USARTD0_STATUS USARTD0.STATUS

1624

#define USARTD0_CTRLA USARTD0.CTRLA

1625

#define USARTD0_CTRLB USARTD0.CTRLB

1626

#define USARTD0_CTRLC USARTD0.CTRLC

1627

#define USARTD0_BAUDCTRLA USARTD0.BAUDCTRLA

1628

#define USARTD0_BAUDCTRLB USARTD0.BAUDCTRLB

1629

1630

// USARTD1 - Universal Asynchronous Receiver-Transmitter D1

1631

#define USARTD1_DATA USARTD1.DATA

1632

#define USARTD1_STATUS USARTD1.STATUS

1633

#define USARTD1_CTRLA USARTD1.CTRLA

1634

#define USARTD1_CTRLB USARTD1.CTRLB

1635

#define USARTD1_CTRLC USARTD1.CTRLC

1636

#define USARTD1_BAUDCTRLA USARTD1.BAUDCTRLA

1637

#define USARTD1_BAUDCTRLB USARTD1.BAUDCTRLB

1638

1639

// SPID - Serial Peripheral Interface D

1640

#define SPID_CTRL SPID.CTRL

1641

#define SPID_INTCTRL SPID.INTCTRL

1642

#define SPID_STATUS SPID.STATUS

1643

#define SPID_DATA SPID.DATA

1644

1645

// TCE0 - 16-bit Timer/Counter With PWM E0

1646

#define TCE0_CTRLA TCE0.CTRLA

1647

#define TCE0_CTRLB TCE0.CTRLB

1648

#define TCE0_CTRLC TCE0.CTRLC

1649

#define TCE0_CTRLD TCE0.CTRLD

1650

#define TCE0_CTRLE TCE0.CTRLE

1651

#define TCE0_INTCTRLA TCE0.INTCTRLA

1652

#define TCE0_INTCTRLB TCE0.INTCTRLB

1653

#define TCE0_CTRLFCLR TCE0.CTRLFCLR

1654

#define TCE0_CTRLFSET TCE0.CTRLFSET

1655

#define TCE0_CTRLGCLR TCE0.CTRLGCLR

1656

#define TCE0_CTRLGSET TCE0.CTRLGSET

1657

#define TCE0_INTFLAGS TCE0.INTFLAGS

1658

#define TCE0_TEMP TCE0.TEMP

1659

#define TCE0_CNT TCE0.CNT

1660

#define TCE0_PER TCE0.PER

1661

#define TCE0_CCA TCE0.CCA

1662

#define TCE0_CCB TCE0.CCB

1663

#define TCE0_CCC TCE0.CCC

1664

#define TCE0_CCD TCE0.CCD

1665

#define TCE0_PERBUF TCE0.PERBUF

1666

#define TCE0_CCABUF TCE0.CCABUF

1667

#define TCE0_CCBBUF TCE0.CCBBUF

1668

#define TCE0_CCCBUF TCE0.CCCBUF

1669

#define TCE0_CCDBUF TCE0.CCDBUF

1670

1671

// TCE1 - 16-bit Timer/Counter With PWM E1

1672

#define TCE1_CTRLA TCE1.CTRLA

1673

#define TCE1_CTRLB TCE1.CTRLB

1674

#define TCE1_CTRLC TCE1.CTRLC

1675

#define TCE1_CTRLD TCE1.CTRLD

1676

#define TCE1_CTRLE TCE1.CTRLE

1677

#define TCE1_INTCTRLA TCE1.INTCTRLA

1678

#define TCE1_INTCTRLB TCE1.INTCTRLB

1679

#define TCE1_CTRLFCLR TCE1.CTRLFCLR

1680

#define TCE1_CTRLFSET TCE1.CTRLFSET

1681

#define TCE1_CTRLGCLR TCE1.CTRLGCLR

1682

#define TCE1_CTRLGSET TCE1.CTRLGSET

1683

#define TCE1_INTFLAGS TCE1.INTFLAGS

1684

#define TCE1_TEMP TCE1.TEMP

1685

#define TCE1_CNT TCE1.CNT

1686

#define TCE1_PER TCE1.PER

1687

#define TCE1_CCA TCE1.CCA

1688

#define TCE1_CCB TCE1.CCB

1689

#define TCE1_PERBUF TCE1.PERBUF

1690

#define TCE1_CCABUF TCE1.CCABUF

1691

#define TCE1_CCBBUF TCE1.CCBBUF

1692

1693

// AWEXE - Advanced Waveform Extension E

1694

#define AWEXE_CTRL AWEXE.CTRL

1695

#define AWEXE_FDEVMASK AWEXE.FDEVMASK

1696

#define AWEXE_DFCTRL AWEXE.DFCTRL

1697

#define AWEXE_STATUS AWEXE.STATUS

1698

#define AWEXE_DTBOTH AWEXE.DTBOTH

1699

#define AWEXE_DTBOTHBUF AWEXE.DTBOTHBUF

1700

#define AWEXE_DTLS AWEXE.DTLS

1701

#define AWEXE_DTHS AWEXE.DTHS

1702

#define AWEXE_DTLSBUF AWEXE.DTLSBUF

1703

#define AWEXE_DTHSBUF AWEXE.DTHSBUF

1704

#define AWEXE_OUTOVEN AWEXE.OUTOVEN

1705

1706

// HIRESE - High-Resolution PWM E

1707

#define HIRESE_CTRL HIRESE.CTRL

1708

1709

// USARTE0 - Universal Asynchronous Receiver-Transmitter E0

1710

#define USARTE0_DATA USARTE0.DATA

1711

#define USARTE0_STATUS USARTE0.STATUS

1712

#define USARTE0_CTRLA USARTE0.CTRLA

1713

#define USARTE0_CTRLB USARTE0.CTRLB

1714

#define USARTE0_CTRLC USARTE0.CTRLC

1715

#define USARTE0_BAUDCTRLA USARTE0.BAUDCTRLA

1716

#define USARTE0_BAUDCTRLB USARTE0.BAUDCTRLB

1717

1718

// USARTE1 - Universal Asynchronous Receiver-Transmitter E1

1719

#define USARTE1_DATA USARTE1.DATA

1720

#define USARTE1_STATUS USARTE1.STATUS

1721

#define USARTE1_CTRLA USARTE1.CTRLA

1722

#define USARTE1_CTRLB USARTE1.CTRLB

1723

#define USARTE1_CTRLC USARTE1.CTRLC

1724

#define USARTE1_BAUDCTRLA USARTE1.BAUDCTRLA

1725

#define USARTE1_BAUDCTRLB USARTE1.BAUDCTRLB

1726

1727

// SPIE - Serial Peripheral Interface E

1728

#define SPIE_CTRL SPIE.CTRL

1729

#define SPIE_INTCTRL SPIE.INTCTRL

1730

#define SPIE_STATUS SPIE.STATUS

1731

#define SPIE_DATA SPIE.DATA

1732

1733

// TCF0 - 16-bit Timer/Counter With PWM F0

1734

#define TCF0_CTRLA TCF0.CTRLA

1735

#define TCF0_CTRLB TCF0.CTRLB

1736

#define TCF0_CTRLC TCF0.CTRLC

1737

#define TCF0_CTRLD TCF0.CTRLD

1738

#define TCF0_CTRLE TCF0.CTRLE

1739

#define TCF0_INTCTRLA TCF0.INTCTRLA

1740

#define TCF0_INTCTRLB TCF0.INTCTRLB

1741

#define TCF0_CTRLFCLR TCF0.CTRLFCLR

1742

#define TCF0_CTRLFSET TCF0.CTRLFSET

1743

#define TCF0_CTRLGCLR TCF0.CTRLGCLR

1744

#define TCF0_CTRLGSET TCF0.CTRLGSET

1745

#define TCF0_INTFLAGS TCF0.INTFLAGS

1746

#define TCF0_TEMP TCF0.TEMP

1747

#define TCF0_CNT TCF0.CNT

1748

#define TCF0_PER TCF0.PER

1749

#define TCF0_CCA TCF0.CCA

1750

#define TCF0_CCB TCF0.CCB

1751

#define TCF0_CCC TCF0.CCC

1752

#define TCF0_CCD TCF0.CCD

1753

#define TCF0_PERBUF TCF0.PERBUF

1754

#define TCF0_CCABUF TCF0.CCABUF

1755

#define TCF0_CCBBUF TCF0.CCBBUF

1756

#define TCF0_CCCBUF TCF0.CCCBUF

1757

#define TCF0_CCDBUF TCF0.CCDBUF

1758

1759

// TCF1 - 16-bit Timer/Counter With PWM F1

1760

#define TCF1_CTRLA TCF1.CTRLA

1761

#define TCF1_CTRLB TCF1.CTRLB

1762

#define TCF1_CTRLC TCF1.CTRLC

1763

#define TCF1_CTRLD TCF1.CTRLD

1764

#define TCF1_CTRLE TCF1.CTRLE

1765

#define TCF1_INTCTRLA TCF1.INTCTRLA

1766

#define TCF1_INTCTRLB TCF1.INTCTRLB

1767

#define TCF1_CTRLFCLR TCF1.CTRLFCLR

1768

#define TCF1_CTRLFSET TCF1.CTRLFSET

1769

#define TCF1_CTRLGCLR TCF1.CTRLGCLR

1770

#define TCF1_CTRLGSET TCF1.CTRLGSET

1771

#define TCF1_INTFLAGS TCF1.INTFLAGS

1772

#define TCF1_TEMP TCF1.TEMP

1773

#define TCF1_CNT TCF1.CNT

1774

#define TCF1_PER TCF1.PER

1775

#define TCF1_CCA TCF1.CCA

1776

#define TCF1_CCB TCF1.CCB

1777

#define TCF1_PERBUF TCF1.PERBUF

1778

#define TCF1_CCABUF TCF1.CCABUF

1779

#define TCF1_CCBBUF TCF1.CCBBUF

1780

1781

// HIRESF - High-Resolution PWM F

1782

#define HIRESF_CTRL HIRESF.CTRL

1783

1784

// USARTF0 - Universal Asynchronous Receiver-Transmitter F0

1785

#define USARTF0_DATA USARTF0.DATA

1786

#define USARTF0_STATUS USARTF0.STATUS

1787

#define USARTF0_CTRLA USARTF0.CTRLA

1788

#define USARTF0_CTRLB USARTF0.CTRLB

1789

#define USARTF0_CTRLC USARTF0.CTRLC

1790

#define USARTF0_BAUDCTRLA USARTF0.BAUDCTRLA

1791

#define USARTF0_BAUDCTRLB USARTF0.BAUDCTRLB

1792

1793

// USARTF1 - Universal Asynchronous Receiver-Transmitter F1

1794

#define USARTF1_DATA USARTF1.DATA

1795

#define USARTF1_STATUS USARTF1.STATUS

1796

#define USARTF1_CTRLA USARTF1.CTRLA

1797

#define USARTF1_CTRLB USARTF1.CTRLB

1798

#define USARTF1_CTRLC USARTF1.CTRLC

1799

#define USARTF1_BAUDCTRLA USARTF1.BAUDCTRLA

1800

#define USARTF1_BAUDCTRLB USARTF1.BAUDCTRLB

1801

1802

// SPIF - Serial Peripheral Interface F

1803

#define SPIF_CTRL SPIF.CTRL

1804

#define SPIF_INTCTRL SPIF.INTCTRL

1805

#define SPIF_STATUS SPIF.STATUS

1806

#define SPIF_DATA SPIF.DATA

1807

1808

// IRCOM - IR Communication Module

1809

#define IRCOM_TXPLCTRL IRCOM.TXPLCTRL

1810

#define IRCOM_RXPLCTRL IRCOM.RXPLCTRL

1811

#define IRCOM_CTRL IRCOM.CTRL

1812

1813

// AES - AES Crypto Module

1814

#define AES_CTRL AES.CTRL

1815

#define AES_STATUS AES.STATUS

1816

#define AES_STATE AES.STATE

1817

#define AES_KEY AES.KEY

1818

#define AES_INTCTRL AES.INTCTRL

1819

1820

#endif /* !defined (__ASSEMBLER__) */

1821

1822

1823

/* ========== Flattened fully qualified IO register names ========== */

1824

1825

/* GPIO - General Purpose IO Registers */

1826

#define GPIO_GPIO0 _SFR_MEM8(0)

1827

#define GPIO_GPIO1 _SFR_MEM8(1)

1828

#define GPIO_GPIO2 _SFR_MEM8(2)

1829

#define GPIO_GPIO3 _SFR_MEM8(3)

1830

#define GPIO_GPIO4 _SFR_MEM8(4)

1831

#define GPIO_GPIO5 _SFR_MEM8(5)

1832

#define GPIO_GPIO6 _SFR_MEM8(6)

1833

#define GPIO_GPIO7 _SFR_MEM8(7)

1834

#define GPIO_GPIO8 _SFR_MEM8(8)

1835

#define GPIO_GPIO9 _SFR_MEM8(9)

1836

#define GPIO_GPIOA _SFR_MEM8(10)

1837

#define GPIO_GPIOB _SFR_MEM8(11)

1838

#define GPIO_GPIOC _SFR_MEM8(12)

1839

#define GPIO_GPIOD _SFR_MEM8(13)

1840

#define GPIO_GPIOE _SFR_MEM8(14)

1841

#define GPIO_GPIOF _SFR_MEM8(15)

1842

1843

/* OCD - On-Chip Debug System */

1844

#define OCD_OCDR0 _SFR_MEM8(46)

1845

#define OCD_OCDR1 _SFR_MEM8(47)

1846

1847

/* CPU - CPU Registers */

1848

#define CPU_CCP _SFR_MEM8(52)

1849

#define CPU_RAMPD _SFR_MEM8(56)

1850

#define CPU_RAMPX _SFR_MEM8(57)

1851

#define CPU_RAMPY _SFR_MEM8(58)

1852

#define CPU_RAMPZ _SFR_MEM8(59)

1853

#define CPU_EIND _SFR_MEM8(60)

1854

#define CPU_SPL _SFR_MEM8(61)

1855

#define CPU_SPH _SFR_MEM8(62)

1856

#define CPU_SREG _SFR_MEM8(63)

1857

1858

/* CLK - Clock System */

1859

#define CLK_CTRL _SFR_MEM8(64)

1860

#define CLK_PSCTRL _SFR_MEM8(65)

1861

#define CLK_LOCK _SFR_MEM8(66)

1862

#define CLK_RTCCTRL _SFR_MEM8(67)

1863

1864

/* SLEEP - Sleep Controller */

1865

#define SLEEP_CTRL _SFR_MEM8(72)

1866

1867

/* OSC - Oscillator */

1868

#define OSC_CTRL _SFR_MEM8(80)

1869

#define OSC_STATUS _SFR_MEM8(81)

1870

#define OSC_XOSCCTRL _SFR_MEM8(82)

1871

#define OSC_XOSCFAIL _SFR_MEM8(83)

1872

#define OSC_RC32KCAL _SFR_MEM8(84)

1873

#define OSC_PLLCTRL _SFR_MEM8(85)

1874

#define OSC_DFLLCTRL _SFR_MEM8(86)

1875

1876

/* DFLLRC32M - DFLL for 32MHz Clock */

1877

#define DFLLRC32M_OSCCNT0 _SFR_MEM8(96)

1878

#define DFLLRC32M_OSCCNT1 _SFR_MEM8(97)

1879

#define DFLLRC32M_OSCCNT2 _SFR_MEM8(98)

1880

#define DFLLRC32M_CALA _SFR_MEM8(99)

1881

#define DFLLRC32M_CALB _SFR_MEM8(100)

1882

1883

/* DFLLRC2M - DFLL for 2MHz Internal RC */

1884

#define DFLLRC2M_OSCCNT0 _SFR_MEM8(104)

1885

#define DFLLRC2M_OSCCNT1 _SFR_MEM8(105)

1886

#define DFLLRC2M_OSCCNT2 _SFR_MEM8(106)

1887

#define DFLLRC2M_CALA _SFR_MEM8(107)

1888

#define DFLLRC2M_CALB _SFR_MEM8(108)

1889

1890

/* PR - Power Reduction */

1891

#define PR_PR _SFR_MEM8(112)

1892

#define PR_PRPA _SFR_MEM8(113)

1893

#define PR_PRPB _SFR_MEM8(114)

1894

#define PR_PRPC _SFR_MEM8(115)

1895

#define PR_PRPD _SFR_MEM8(116)

1896

#define PR_PRPE _SFR_MEM8(117)

1897

#define PR_PRPF _SFR_MEM8(118)

1898

1899

/* RST - Reset Controller */

1900

#define RST_STATUS _SFR_MEM8(120)

1901

#define RST_CTRL _SFR_MEM8(121)

1902

1903

/* WDT - Watch-Dog Timer */

1904

#define WDT_CTRL _SFR_MEM8(128)

1905

#define WDT_WINCTRL _SFR_MEM8(129)

1906

#define WDT_STATUS _SFR_MEM8(130)

1907

1908

/* MCU - MCU Revision */

1909

#define MCU_DEVID0 _SFR_MEM8(144)

1910

#define MCU_DEVID1 _SFR_MEM8(145)

1911

#define MCU_DEVID2 _SFR_MEM8(146)

1912

#define MCU_REVID _SFR_MEM8(147)

1913

#define MCU_JTAGUID _SFR_MEM8(148)

1914

#define MCU_MCUCR _SFR_MEM8(150)

1915

#define MCU_EVSYSLOCK _SFR_MEM8(152)

1916

#define MCU_AWEXLOCK _SFR_MEM8(153)

1917

1918

/* PMIC - Programmable Interrupt Controller */

1919

#define PMIC_STATUS _SFR_MEM8(160)

1920

#define PMIC_INTPRI _SFR_MEM8(161)

1921

#define PMIC_CTRL _SFR_MEM8(162)

1922

1923

/* DMA - DMA Controller */

1924

#define DMA_CTRL _SFR_MEM8(256)

1925

#define DMA_INTFLAGS _SFR_MEM8(259)

1926

#define DMA_STATUS _SFR_MEM8(260)

1927

1928

/* EVSYS - Event System */

1929

#define EVSYS_CH0MUX _SFR_MEM8(384)

1930

#define EVSYS_CH1MUX _SFR_MEM8(385)

1931

#define EVSYS_CH2MUX _SFR_MEM8(386)

1932

#define EVSYS_CH3MUX _SFR_MEM8(387)

1933

#define EVSYS_CH4MUX _SFR_MEM8(388)

1934

#define EVSYS_CH5MUX _SFR_MEM8(389)

1935

#define EVSYS_CH6MUX _SFR_MEM8(390)

1936

#define EVSYS_CH7MUX _SFR_MEM8(391)

1937

#define EVSYS_CH0CTRL _SFR_MEM8(392)

1938

#define EVSYS_CH1CTRL _SFR_MEM8(393)

1939

#define EVSYS_CH2CTRL _SFR_MEM8(394)

1940

#define EVSYS_CH3CTRL _SFR_MEM8(395)

1941

#define EVSYS_CH4CTRL _SFR_MEM8(396)

1942

#define EVSYS_CH5CTRL _SFR_MEM8(397)

1943

#define EVSYS_CH6CTRL _SFR_MEM8(398)

1944

#define EVSYS_CH7CTRL _SFR_MEM8(399)

1945

#define EVSYS_STROBE _SFR_MEM8(400)

1946

#define EVSYS_DATA _SFR_MEM8(401)

1947

1948

/* NVM - Non Volatile Memory */

1949

#define NVM_ADDR0 _SFR_MEM8(448)

1950

#define NVM_ADDR1 _SFR_MEM8(449)

1951

#define NVM_ADDR2 _SFR_MEM8(450)

1952

#define NVM_DATA0 _SFR_MEM8(452)

1953

#define NVM_DATA1 _SFR_MEM8(453)

1954

#define NVM_DATA2 _SFR_MEM8(454)

1955

#define NVM_CMD _SFR_MEM8(458)

1956

#define NVM_CTRLA _SFR_MEM8(459)

1957

#define NVM_CTRLB _SFR_MEM8(460)

1958

#define NVM_INTCTRL _SFR_MEM8(461)

1959

#define NVM_STATUS _SFR_MEM8(463)

1960

#define NVM_LOCKBITS _SFR_MEM8(464)

1961

1962

/* ACA - Analog Comparator A */

1963

#define ACA_AC0CTRL _SFR_MEM8(896)

1964

#define ACA_AC1CTRL _SFR_MEM8(897)

1965

#define ACA_AC0MUXCTRL _SFR_MEM8(898)

1966

#define ACA_AC1MUXCTRL _SFR_MEM8(899)

1967

#define ACA_CTRLA _SFR_MEM8(900)

1968

#define ACA_CTRLB _SFR_MEM8(901)

1969

#define ACA_WINCTRL _SFR_MEM8(902)

1970

#define ACA_STATUS _SFR_MEM8(903)

1971

1972

/* ACB - Analog Comparator B */

1973

#define ACB_AC0CTRL _SFR_MEM8(912)

1974

#define ACB_AC1CTRL _SFR_MEM8(913)

1975

#define ACB_AC0MUXCTRL _SFR_MEM8(914)

1976

#define ACB_AC1MUXCTRL _SFR_MEM8(915)

1977

#define ACB_CTRLA _SFR_MEM8(916)

1978

#define ACB_CTRLB _SFR_MEM8(917)

1979

#define ACB_WINCTRL _SFR_MEM8(918)

1980

#define ACB_STATUS _SFR_MEM8(919)

1981

1982

/* ADCA - Analog/Digital Converter A */

1983

#define ADCA_CTRLA _SFR_MEM8(512)

1984

#define ADCA_CTRLB _SFR_MEM8(513)

1985

#define ADCA_REFCTRL _SFR_MEM8(514)

1986

#define ADCA_EVCTRL _SFR_MEM8(515)

1987

#define ADCA_PRESCALER _SFR_MEM8(516)

1988

#define ADCA_CALCTRL _SFR_MEM8(517)

1989

#define ADCA_INTFLAGS _SFR_MEM8(518)

1990

#define ADCA_CALIB _SFR_MEM8(524)

1991

#define ADCA_CH0RES _SFR_MEM16(528)

1992

#define ADCA_CH1RES _SFR_MEM16(530)

1993

#define ADCA_CH2RES _SFR_MEM16(532)

1994

#define ADCA_CH3RES _SFR_MEM16(534)

1995

#define ADCA_CMP _SFR_MEM16(536)

1996

1997

/* ADCB - Analog/Digital Converter B */

1998

#define ADCB_CTRLA _SFR_MEM8(576)

1999

#define ADCB_CTRLB _SFR_MEM8(577)

2000

#define ADCB_REFCTRL _SFR_MEM8(578)

2001

#define ADCB_EVCTRL _SFR_MEM8(579)

2002

#define ADCB_PRESCALER _SFR_MEM8(580)

2003

#define ADCB_CALCTRL _SFR_MEM8(581)

2004

#define ADCB_INTFLAGS _SFR_MEM8(582)

2005

#define ADCB_CALIB _SFR_MEM8(588)

2006

#define ADCB_CH0RES _SFR_MEM16(592)

2007

#define ADCB_CH1RES _SFR_MEM16(594)

2008

#define ADCB_CH2RES _SFR_MEM16(596)

2009

#define ADCB_CH3RES _SFR_MEM16(598)

2010

#define ADCB_CMP _SFR_MEM16(600)

2011

2012

/* DACA - Digital/Analog Converter A */

2013

#define DACA_CTRLA _SFR_MEM8(768)

2014

#define DACA_CTRLB _SFR_MEM8(769)

2015

#define DACA_CTRLC _SFR_MEM8(770)

2016

#define DACA_EVCTRL _SFR_MEM8(771)

2017

#define DACA_TIMCTRL _SFR_MEM8(772)

2018

#define DACA_STATUS _SFR_MEM8(773)

2019

#define DACA_GAINCAL _SFR_MEM8(776)

2020

#define DACA_OFFSETCAL _SFR_MEM8(777)

2021

#define DACA_CH0DATA _SFR_MEM16(792)

2022

#define DACA_CH1DATA _SFR_MEM16(794)

2023

2024

/* DACB - Digital/Analog Converter B */

2025

#define DACB_CTRLA _SFR_MEM8(800)

2026

#define DACB_CTRLB _SFR_MEM8(801)

2027

#define DACB_CTRLC _SFR_MEM8(802)

2028

#define DACB_EVCTRL _SFR_MEM8(803)

2029

#define DACB_TIMCTRL _SFR_MEM8(804)

2030

#define DACB_STATUS _SFR_MEM8(805)

2031

#define DACB_GAINCAL _SFR_MEM8(808)

2032

#define DACB_OFFSETCAL _SFR_MEM8(809)

2033

#define DACB_CH0DATA _SFR_MEM16(824)

2034

#define DACB_CH1DATA _SFR_MEM16(826)

2035

2036

/* RTC - Real-Time Clock */

2037

#define RTC_CTRL _SFR_MEM8(1024)

2038

#define RTC_STATUS _SFR_MEM8(1025)

2039

#define RTC_INTCTRL _SFR_MEM8(1026)

2040

#define RTC_INTFLAGS _SFR_MEM8(1027)

2041

#define RTC_TEMP _SFR_MEM8(1028)

2042

#define RTC_CNT _SFR_MEM16(1032)

2043

#define RTC_PER _SFR_MEM16(1034)

2044

#define RTC_COMP _SFR_MEM16(1036)

2045

2046

/* EBI - External Bus Interface */

2047

#define EBI_CTRL _SFR_MEM8(1088)

2048

#define EBI_SDRAMCTRLA _SFR_MEM8(1089)

2049

#define EBI_REFRESH _SFR_MEM16(1092)

2050

#define EBI_INITDLY _SFR_MEM16(1094)

2051

#define EBI_SDRAMCTRLB _SFR_MEM8(1096)

2052

#define EBI_SDRAMCTRLC _SFR_MEM8(1097)

2053

2054

/* TWIC - Two-Wire Interface C */

2055

#define TWIC_CTRL _SFR_MEM8(1152)

2056

2057

/* TWID - Two-Wire Interface D */

2058

#define TWID_CTRL _SFR_MEM8(1168)

2059

2060

/* TWIE - Two-Wire Interface E */

2061

#define TWIE_CTRL _SFR_MEM8(1184)

2062

2063

/* TWIF - Two-Wire Interface F */

2064

#define TWIF_CTRL _SFR_MEM8(1200)

2065

2066

/* PORTCFG - Port Configuration */

2067

#define PORTCFG_MPCMASK _SFR_MEM8(176)

2068

#define PORTCFG_VPCTRLA _SFR_MEM8(178)

2069

#define PORTCFG_VPCTRLB _SFR_MEM8(179)

2070

#define PORTCFG_CLKEVOUT _SFR_MEM8(180)

2071

2072

/* VPORT0 - Virtual Port 0 */

2073

#define VPORT0_DIR _SFR_MEM8(16)

2074

#define VPORT0_OUT _SFR_MEM8(17)

2075

#define VPORT0_IN _SFR_MEM8(18)

2076

#define VPORT0_INTFLAGS _SFR_MEM8(19)

2077

2078

/* VPORT1 - Virtual Port 1 */

2079

#define VPORT1_DIR _SFR_MEM8(20)

2080

#define VPORT1_OUT _SFR_MEM8(21)

2081

#define VPORT1_IN _SFR_MEM8(22)

2082

#define VPORT1_INTFLAGS _SFR_MEM8(23)

2083

2084

/* VPORT2 - Virtual Port 2 */

2085

#define VPORT2_DIR _SFR_MEM8(24)

2086

#define VPORT2_OUT _SFR_MEM8(25)

2087

#define VPORT2_IN _SFR_MEM8(26)

2088

#define VPORT2_INTFLAGS _SFR_MEM8(27)

2089

2090

/* VPORT3 - Virtual Port 3 */

2091

#define VPORT3_DIR _SFR_MEM8(28)

2092

#define VPORT3_OUT _SFR_MEM8(29)

2093

#define VPORT3_IN _SFR_MEM8(30)

2094

#define VPORT3_INTFLAGS _SFR_MEM8(31)

2095

2096

/* PORTA - Port A */

2097

#define PORTA_DIR _SFR_MEM8(1536)

2098

#define PORTA_DIRSET _SFR_MEM8(1537)

2099

#define PORTA_DIRCLR _SFR_MEM8(1538)

2100

#define PORTA_DIRTGL _SFR_MEM8(1539)

2101

#define PORTA_OUT _SFR_MEM8(1540)

2102

#define PORTA_OUTSET _SFR_MEM8(1541)

2103

#define PORTA_OUTCLR _SFR_MEM8(1542)

2104

#define PORTA_OUTTGL _SFR_MEM8(1543)

2105

#define PORTA_IN _SFR_MEM8(1544)

2106

#define PORTA_INTCTRL _SFR_MEM8(1545)

2107

#define PORTA_INT0MASK _SFR_MEM8(1546)

2108

#define PORTA_INT1MASK _SFR_MEM8(1547)

2109

#define PORTA_INTFLAGS _SFR_MEM8(1548)

2110

#define PORTA_PIN0CTRL _SFR_MEM8(1552)

2111

#define PORTA_PIN1CTRL _SFR_MEM8(1553)

2112

#define PORTA_PIN2CTRL _SFR_MEM8(1554)

2113

#define PORTA_PIN3CTRL _SFR_MEM8(1555)

2114

#define PORTA_PIN4CTRL _SFR_MEM8(1556)

2115

#define PORTA_PIN5CTRL _SFR_MEM8(1557)

2116

#define PORTA_PIN6CTRL _SFR_MEM8(1558)

2117

#define PORTA_PIN7CTRL _SFR_MEM8(1559)

2118

2119

/* PORTB - Port B */

2120

#define PORTB_DIR _SFR_MEM8(1568)

2121

#define PORTB_DIRSET _SFR_MEM8(1569)

2122

#define PORTB_DIRCLR _SFR_MEM8(1570)

2123

#define PORTB_DIRTGL _SFR_MEM8(1571)

2124

#define PORTB_OUT _SFR_MEM8(1572)

2125

#define PORTB_OUTSET _SFR_MEM8(1573)

2126

#define PORTB_OUTCLR _SFR_MEM8(1574)

2127

#define PORTB_OUTTGL _SFR_MEM8(1575)

2128

#define PORTB_IN _SFR_MEM8(1576)

2129

#define PORTB_INTCTRL _SFR_MEM8(1577)

2130

#define PORTB_INT0MASK _SFR_MEM8(1578)

2131

#define PORTB_INT1MASK _SFR_MEM8(1579)

2132

#define PORTB_INTFLAGS _SFR_MEM8(1580)

2133

#define PORTB_PIN0CTRL _SFR_MEM8(1584)

2134

#define PORTB_PIN1CTRL _SFR_MEM8(1585)

2135

#define PORTB_PIN2CTRL _SFR_MEM8(1586)

2136

#define PORTB_PIN3CTRL _SFR_MEM8(1587)

2137

#define PORTB_PIN4CTRL _SFR_MEM8(1588)

2138

#define PORTB_PIN5CTRL _SFR_MEM8(1589)

2139

#define PORTB_PIN6CTRL _SFR_MEM8(1590)

2140

#define PORTB_PIN7CTRL _SFR_MEM8(1591)

2141

2142

/* PORTC - Port C */

2143

#define PORTC_DIR _SFR_MEM8(1600)

2144

#define PORTC_DIRSET _SFR_MEM8(1601)

2145

#define PORTC_DIRCLR _SFR_MEM8(1602)

2146

#define PORTC_DIRTGL _SFR_MEM8(1603)

2147

#define PORTC_OUT _SFR_MEM8(1604)

2148

#define PORTC_OUTSET _SFR_MEM8(1605)

2149

#define PORTC_OUTCLR _SFR_MEM8(1606)

2150

#define PORTC_OUTTGL _SFR_MEM8(1607)

2151

#define PORTC_IN _SFR_MEM8(1608)

2152

#define PORTC_INTCTRL _SFR_MEM8(1609)

2153

#define PORTC_INT0MASK _SFR_MEM8(1610)

2154

#define PORTC_INT1MASK _SFR_MEM8(1611)

2155

#define PORTC_INTFLAGS _SFR_MEM8(1612)

2156

#define PORTC_PIN0CTRL _SFR_MEM8(1616)

2157

#define PORTC_PIN1CTRL _SFR_MEM8(1617)

2158

#define PORTC_PIN2CTRL _SFR_MEM8(1618)

2159

#define PORTC_PIN3CTRL _SFR_MEM8(1619)

2160

#define PORTC_PIN4CTRL _SFR_MEM8(1620)

2161

#define PORTC_PIN5CTRL _SFR_MEM8(1621)

2162

#define PORTC_PIN6CTRL _SFR_MEM8(1622)

2163

#define PORTC_PIN7CTRL _SFR_MEM8(1623)

2164

2165

/* PORTD - Port D */

2166

#define PORTD_DIR _SFR_MEM8(1632)

2167

#define PORTD_DIRSET _SFR_MEM8(1633)

2168

#define PORTD_DIRCLR _SFR_MEM8(1634)

2169

#define PORTD_DIRTGL _SFR_MEM8(1635)

2170

#define PORTD_OUT _SFR_MEM8(1636)

2171

#define PORTD_OUTSET _SFR_MEM8(1637)

2172

#define PORTD_OUTCLR _SFR_MEM8(1638)

2173

#define PORTD_OUTTGL _SFR_MEM8(1639)

2174

#define PORTD_IN _SFR_MEM8(1640)

2175

#define PORTD_INTCTRL _SFR_MEM8(1641)

2176

#define PORTD_INT0MASK _SFR_MEM8(1642)

2177

#define PORTD_INT1MASK _SFR_MEM8(1643)

2178

#define PORTD_INTFLAGS _SFR_MEM8(1644)

2179

#define PORTD_PIN0CTRL _SFR_MEM8(1648)

2180

#define PORTD_PIN1CTRL _SFR_MEM8(1649)

2181

#define PORTD_PIN2CTRL _SFR_MEM8(1650)

2182

#define PORTD_PIN3CTRL _SFR_MEM8(1651)

2183

#define PORTD_PIN4CTRL _SFR_MEM8(1652)

2184

#define PORTD_PIN5CTRL _SFR_MEM8(1653)

2185

#define PORTD_PIN6CTRL _SFR_MEM8(1654)

2186

#define PORTD_PIN7CTRL _SFR_MEM8(1655)

2187

2188

/* PORTE - Port E */

2189

#define PORTE_DIR _SFR_MEM8(1664)

2190

#define PORTE_DIRSET _SFR_MEM8(1665)

2191

#define PORTE_DIRCLR _SFR_MEM8(1666)

2192

#define PORTE_DIRTGL _SFR_MEM8(1667)

2193

#define PORTE_OUT _SFR_MEM8(1668)

2194

#define PORTE_OUTSET _SFR_MEM8(1669)

2195

#define PORTE_OUTCLR _SFR_MEM8(1670)

2196

#define PORTE_OUTTGL _SFR_MEM8(1671)

2197

#define PORTE_IN _SFR_MEM8(1672)

2198

#define PORTE_INTCTRL _SFR_MEM8(1673)

2199

#define PORTE_INT0MASK _SFR_MEM8(1674)

2200

#define PORTE_INT1MASK _SFR_MEM8(1675)

2201

#define PORTE_INTFLAGS _SFR_MEM8(1676)

2202

#define PORTE_PIN0CTRL _SFR_MEM8(1680)

2203

#define PORTE_PIN1CTRL _SFR_MEM8(1681)

2204

#define PORTE_PIN2CTRL _SFR_MEM8(1682)

2205

#define PORTE_PIN3CTRL _SFR_MEM8(1683)

2206

#define PORTE_PIN4CTRL _SFR_MEM8(1684)

2207

#define PORTE_PIN5CTRL _SFR_MEM8(1685)

2208

#define PORTE_PIN6CTRL _SFR_MEM8(1686)

2209

#define PORTE_PIN7CTRL _SFR_MEM8(1687)

2210

2211

/* PORTF - Port F */

2212

#define PORTF_DIR _SFR_MEM8(1696)

2213

#define PORTF_DIRSET _SFR_MEM8(1697)

2214

#define PORTF_DIRCLR _SFR_MEM8(1698)

2215

#define PORTF_DIRTGL _SFR_MEM8(1699)

2216

#define PORTF_OUT _SFR_MEM8(1700)

2217

#define PORTF_OUTSET _SFR_MEM8(1701)

2218

#define PORTF_OUTCLR _SFR_MEM8(1702)

2219

#define PORTF_OUTTGL _SFR_MEM8(1703)

2220

#define PORTF_IN _SFR_MEM8(1704)

2221

#define PORTF_INTCTRL _SFR_MEM8(1705)

2222

#define PORTF_INT0MASK _SFR_MEM8(1706)

2223

#define PORTF_INT1MASK _SFR_MEM8(1707)

2224

#define PORTF_INTFLAGS _SFR_MEM8(1708)

2225

#define PORTF_PIN0CTRL _SFR_MEM8(1712)

2226

#define PORTF_PIN1CTRL _SFR_MEM8(1713)

2227

#define PORTF_PIN2CTRL _SFR_MEM8(1714)

2228

#define PORTF_PIN3CTRL _SFR_MEM8(1715)

2229

#define PORTF_PIN4CTRL _SFR_MEM8(1716)

2230

#define PORTF_PIN5CTRL _SFR_MEM8(1717)

2231

#define PORTF_PIN6CTRL _SFR_MEM8(1718)

2232

#define PORTF_PIN7CTRL _SFR_MEM8(1719)

2233

2234

/* PORTH - Port H */

2235

#define PORTH_DIR _SFR_MEM8(1760)

2236

#define PORTH_DIRSET _SFR_MEM8(1761)

2237

#define PORTH_DIRCLR _SFR_MEM8(1762)

2238

#define PORTH_DIRTGL _SFR_MEM8(1763)

2239

#define PORTH_OUT _SFR_MEM8(1764)

2240

#define PORTH_OUTSET _SFR_MEM8(1765)

2241

#define PORTH_OUTCLR _SFR_MEM8(1766)

2242

#define PORTH_OUTTGL _SFR_MEM8(1767)

2243

#define PORTH_IN _SFR_MEM8(1768)

2244

#define PORTH_INTCTRL _SFR_MEM8(1769)

2245

#define PORTH_INT0MASK _SFR_MEM8(1770)

2246

#define PORTH_INT1MASK _SFR_MEM8(1771)

2247

#define PORTH_INTFLAGS _SFR_MEM8(1772)

2248

#define PORTH_PIN0CTRL _SFR_MEM8(1776)

2249

#define PORTH_PIN1CTRL _SFR_MEM8(1777)

2250

#define PORTH_PIN2CTRL _SFR_MEM8(1778)

2251

#define PORTH_PIN3CTRL _SFR_MEM8(1779)

2252

#define PORTH_PIN4CTRL _SFR_MEM8(1780)

2253

#define PORTH_PIN5CTRL _SFR_MEM8(1781)

2254

#define PORTH_PIN6CTRL _SFR_MEM8(1782)

2255

#define PORTH_PIN7CTRL _SFR_MEM8(1783)

2256

2257

/* PORTJ - Port J */

2258

#define PORTJ_DIR _SFR_MEM8(1792)

2259

#define PORTJ_DIRSET _SFR_MEM8(1793)

2260

#define PORTJ_DIRCLR _SFR_MEM8(1794)

2261

#define PORTJ_DIRTGL _SFR_MEM8(1795)

2262

#define PORTJ_OUT _SFR_MEM8(1796)

2263

#define PORTJ_OUTSET _SFR_MEM8(1797)

2264

#define PORTJ_OUTCLR _SFR_MEM8(1798)

2265

#define PORTJ_OUTTGL _SFR_MEM8(1799)

2266

#define PORTJ_IN _SFR_MEM8(1800)

2267

#define PORTJ_INTCTRL _SFR_MEM8(1801)

2268

#define PORTJ_INT0MASK _SFR_MEM8(1802)

2269

#define PORTJ_INT1MASK _SFR_MEM8(1803)

2270

#define PORTJ_INTFLAGS _SFR_MEM8(1804)

2271

#define PORTJ_PIN0CTRL _SFR_MEM8(1808)

2272

#define PORTJ_PIN1CTRL _SFR_MEM8(1809)

2273

#define PORTJ_PIN2CTRL _SFR_MEM8(1810)

2274

#define PORTJ_PIN3CTRL _SFR_MEM8(1811)

2275

#define PORTJ_PIN4CTRL _SFR_MEM8(1812)

2276

#define PORTJ_PIN5CTRL _SFR_MEM8(1813)

2277

#define PORTJ_PIN6CTRL _SFR_MEM8(1814)

2278

#define PORTJ_PIN7CTRL _SFR_MEM8(1815)

2279

2280

/* PORTK - Port K */

2281

#define PORTK_DIR _SFR_MEM8(1824)

2282

#define PORTK_DIRSET _SFR_MEM8(1825)

2283

#define PORTK_DIRCLR _SFR_MEM8(1826)

2284

#define PORTK_DIRTGL _SFR_MEM8(1827)

2285

#define PORTK_OUT _SFR_MEM8(1828)

2286

#define PORTK_OUTSET _SFR_MEM8(1829)

2287

#define PORTK_OUTCLR _SFR_MEM8(1830)

2288

#define PORTK_OUTTGL _SFR_MEM8(1831)

2289

#define PORTK_IN _SFR_MEM8(1832)

2290

#define PORTK_INTCTRL _SFR_MEM8(1833)

2291

#define PORTK_INT0MASK _SFR_MEM8(1834)

2292

#define PORTK_INT1MASK _SFR_MEM8(1835)

2293

#define PORTK_INTFLAGS _SFR_MEM8(1836)

2294

#define PORTK_PIN0CTRL _SFR_MEM8(1840)

2295

#define PORTK_PIN1CTRL _SFR_MEM8(1841)

2296

#define PORTK_PIN2CTRL _SFR_MEM8(1842)

2297

#define PORTK_PIN3CTRL _SFR_MEM8(1843)

2298

#define PORTK_PIN4CTRL _SFR_MEM8(1844)

2299

#define PORTK_PIN5CTRL _SFR_MEM8(1845)

2300

#define PORTK_PIN6CTRL _SFR_MEM8(1846)

2301

#define PORTK_PIN7CTRL _SFR_MEM8(1847)

2302

2303

/* PORTQ - Port Q */

2304

#define PORTQ_DIR _SFR_MEM8(1984)

2305

#define PORTQ_DIRSET _SFR_MEM8(1985)

2306

#define PORTQ_DIRCLR _SFR_MEM8(1986)

2307

#define PORTQ_DIRTGL _SFR_MEM8(1987)

2308

#define PORTQ_OUT _SFR_MEM8(1988)

2309

#define PORTQ_OUTSET _SFR_MEM8(1989)

2310

#define PORTQ_OUTCLR _SFR_MEM8(1990)

2311

#define PORTQ_OUTTGL _SFR_MEM8(1991)

2312

#define PORTQ_IN _SFR_MEM8(1992)

2313

#define PORTQ_INTCTRL _SFR_MEM8(1993)

2314

#define PORTQ_INT0MASK _SFR_MEM8(1994)

2315

#define PORTQ_INT1MASK _SFR_MEM8(1995)

2316

#define PORTQ_INTFLAGS _SFR_MEM8(1996)

2317

#define PORTQ_PIN0CTRL _SFR_MEM8(2000)

2318

#define PORTQ_PIN1CTRL _SFR_MEM8(2001)

2319

#define PORTQ_PIN2CTRL _SFR_MEM8(2002)

2320

#define PORTQ_PIN3CTRL _SFR_MEM8(2003)

2321

#define PORTQ_PIN4CTRL _SFR_MEM8(2004)

2322

#define PORTQ_PIN5CTRL _SFR_MEM8(2005)

2323

#define PORTQ_PIN6CTRL _SFR_MEM8(2006)

2324

#define PORTQ_PIN7CTRL _SFR_MEM8(2007)

2325

2326

/* PORTR - Port R */

2327

#define PORTR_DIR _SFR_MEM8(2016)

2328

#define PORTR_DIRSET _SFR_MEM8(2017)

2329

#define PORTR_DIRCLR _SFR_MEM8(2018)

2330

#define PORTR_DIRTGL _SFR_MEM8(2019)

2331

#define PORTR_OUT _SFR_MEM8(2020)

2332

#define PORTR_OUTSET _SFR_MEM8(2021)

2333

#define PORTR_OUTCLR _SFR_MEM8(2022)

2334

#define PORTR_OUTTGL _SFR_MEM8(2023)

2335

#define PORTR_IN _SFR_MEM8(2024)

2336

#define PORTR_INTCTRL _SFR_MEM8(2025)

2337

#define PORTR_INT0MASK _SFR_MEM8(2026)

2338

#define PORTR_INT1MASK _SFR_MEM8(2027)

2339

#define PORTR_INTFLAGS _SFR_MEM8(2028)

2340

#define PORTR_PIN0CTRL _SFR_MEM8(2032)

2341

#define PORTR_PIN1CTRL _SFR_MEM8(2033)

2342

#define PORTR_PIN2CTRL _SFR_MEM8(2034)

2343

#define PORTR_PIN3CTRL _SFR_MEM8(2035)

2344

#define PORTR_PIN4CTRL _SFR_MEM8(2036)

2345

#define PORTR_PIN5CTRL _SFR_MEM8(2037)

2346

#define PORTR_PIN6CTRL _SFR_MEM8(2038)

2347

#define PORTR_PIN7CTRL _SFR_MEM8(2039)

2348

2349

/* TCC0 - 16-bit Timer/Counter With PWM C0 */

2350

#define TCC0_CTRLA _SFR_MEM8(2048)

2351

#define TCC0_CTRLB _SFR_MEM8(2049)

2352

#define TCC0_CTRLC _SFR_MEM8(2050)

2353

#define TCC0_CTRLD _SFR_MEM8(2051)

2354

#define TCC0_CTRLE _SFR_MEM8(2052)

2355

#define TCC0_INTCTRLA _SFR_MEM8(2054)

2356

#define TCC0_INTCTRLB _SFR_MEM8(2055)

2357

#define TCC0_CTRLFCLR _SFR_MEM8(2056)

2358

#define TCC0_CTRLFSET _SFR_MEM8(2057)

2359

#define TCC0_CTRLGCLR _SFR_MEM8(2058)

2360

#define TCC0_CTRLGSET _SFR_MEM8(2059)

2361

#define TCC0_INTFLAGS _SFR_MEM8(2060)

2362

#define TCC0_TEMP _SFR_MEM8(2063)

2363

#define TCC0_CNT _SFR_MEM16(2080)

2364

#define TCC0_PER _SFR_MEM16(2086)

2365

#define TCC0_CCA _SFR_MEM16(2088)

2366

#define TCC0_CCB _SFR_MEM16(2090)

2367

#define TCC0_CCC _SFR_MEM16(2092)

2368

#define TCC0_CCD _SFR_MEM16(2094)

2369

#define TCC0_PERBUF _SFR_MEM16(2102)

2370

#define TCC0_CCABUF _SFR_MEM16(2104)

2371

#define TCC0_CCBBUF _SFR_MEM16(2106)

2372

#define TCC0_CCCBUF _SFR_MEM16(2108)

2373

#define TCC0_CCDBUF _SFR_MEM16(2110)

2374

2375

/* TCC1 - 16-bit Timer/Counter With PWM C1 */

2376

#define TCC1_CTRLA _SFR_MEM8(2112)

2377

#define TCC1_CTRLB _SFR_MEM8(2113)

2378

#define TCC1_CTRLC _SFR_MEM8(2114)

2379

#define TCC1_CTRLD _SFR_MEM8(2115)

2380

#define TCC1_CTRLE _SFR_MEM8(2116)

2381

#define TCC1_INTCTRLA _SFR_MEM8(2118)

2382

#define TCC1_INTCTRLB _SFR_MEM8(2119)

2383

#define TCC1_CTRLFCLR _SFR_MEM8(2120)

2384

#define TCC1_CTRLFSET _SFR_MEM8(2121)

2385

#define TCC1_CTRLGCLR _SFR_MEM8(2122)

2386

#define TCC1_CTRLGSET _SFR_MEM8(2123)

2387

#define TCC1_INTFLAGS _SFR_MEM8(2124)

2388

#define TCC1_TEMP _SFR_MEM8(2127)

2389

#define TCC1_CNT _SFR_MEM16(2144)

2390

#define TCC1_PER _SFR_MEM16(2150)

2391

#define TCC1_CCA _SFR_MEM16(2152)

2392

#define TCC1_CCB _SFR_MEM16(2154)

2393

#define TCC1_PERBUF _SFR_MEM16(2166)

2394

#define TCC1_CCABUF _SFR_MEM16(2168)

2395

#define TCC1_CCBBUF _SFR_MEM16(2170)

2396

2397

/* AWEXC - Advanced Waveform Extension C */

2398

#define AWEXC_CTRL _SFR_MEM8(2176)

2399

#define AWEXC_FDEVMASK _SFR_MEM8(2178)

2400

#define AWEXC_DFCTRL _SFR_MEM8(2179)

2401

#define AWEXC_STATUS _SFR_MEM8(2180)

2402

#define AWEXC_DTBOTH _SFR_MEM8(2182)

2403

#define AWEXC_DTBOTHBUF _SFR_MEM8(2183)

2404

#define AWEXC_DTLS _SFR_MEM8(2184)

2405

#define AWEXC_DTHS _SFR_MEM8(2185)

2406

#define AWEXC_DTLSBUF _SFR_MEM8(2186)

2407

#define AWEXC_DTHSBUF _SFR_MEM8(2187)

2408

#define AWEXC_OUTOVEN _SFR_MEM8(2188)

2409

2410

/* HIRESC - High-Resolution PWM C */

2411

#define HIRESC_CTRL _SFR_MEM8(2192)

2412

2413

/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */

2414

#define USARTC0_DATA _SFR_MEM8(2208)

2415

#define USARTC0_STATUS _SFR_MEM8(2209)

2416

#define USARTC0_CTRLA _SFR_MEM8(2211)

2417

#define USARTC0_CTRLB _SFR_MEM8(2212)

2418

#define USARTC0_CTRLC _SFR_MEM8(2213)

2419

#define USARTC0_BAUDCTRLA _SFR_MEM8(2214)

2420

#define USARTC0_BAUDCTRLB _SFR_MEM8(2215)

2421

2422

/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */

2423

#define USARTC1_DATA _SFR_MEM8(2224)

2424

#define USARTC1_STATUS _SFR_MEM8(2225)

2425

#define USARTC1_CTRLA _SFR_MEM8(2227)

2426

#define USARTC1_CTRLB _SFR_MEM8(2228)

2427

#define USARTC1_CTRLC _SFR_MEM8(2229)

2428

#define USARTC1_BAUDCTRLA _SFR_MEM8(2230)

2429

#define USARTC1_BAUDCTRLB _SFR_MEM8(2231)

2430

2431

/* SPIC - Serial Peripheral Interface C */

2432

#define SPIC_CTRL _SFR_MEM8(2240)

2433

#define SPIC_INTCTRL _SFR_MEM8(2241)

2434

#define SPIC_STATUS _SFR_MEM8(2242)

2435

#define SPIC_DATA _SFR_MEM8(2243)

2436

2437

/* TCD0 - 16-bit Timer/Counter With PWM D0 */

2438

#define TCD0_CTRLA _SFR_MEM8(2304)

2439

#define TCD0_CTRLB _SFR_MEM8(2305)

2440

#define TCD0_CTRLC _SFR_MEM8(2306)

2441

#define TCD0_CTRLD _SFR_MEM8(2307)

2442

#define TCD0_CTRLE _SFR_MEM8(2308)

2443

#define TCD0_INTCTRLA _SFR_MEM8(2310)

2444

#define TCD0_INTCTRLB _SFR_MEM8(2311)

2445

#define TCD0_CTRLFCLR _SFR_MEM8(2312)

2446

#define TCD0_CTRLFSET _SFR_MEM8(2313)

2447

#define TCD0_CTRLGCLR _SFR_MEM8(2314)

2448

#define TCD0_CTRLGSET _SFR_MEM8(2315)

2449

#define TCD0_INTFLAGS _SFR_MEM8(2316)

2450

#define TCD0_TEMP _SFR_MEM8(2319)

2451

#define TCD0_CNT _SFR_MEM8(2336)

2452

#define TCD0_PER _SFR_MEM8(2342)

2453

#define TCD0_CCA _SFR_MEM8(2344)

2454

#define TCD0_CCB _SFR_MEM8(2346)

2455

#define TCD0_CCC _SFR_MEM8(2348)

2456

#define TCD0_CCD _SFR_MEM8(2350)

2457

#define TCD0_PERBUF _SFR_MEM8(2358)

2458

#define TCD0_CCABUF _SFR_MEM8(2360)

2459

#define TCD0_CCBBUF _SFR_MEM8(2362)

2460

#define TCD0_CCCBUF _SFR_MEM8(2364)

2461

#define TCD0_CCDBUF _SFR_MEM8(2366)

2462

2463

/* TCD1 - 16-bit Timer/Counter With PWM D1 */

2464

#define TCD1_CTRLA _SFR_MEM8(2368)

2465

#define TCD1_CTRLB _SFR_MEM8(2369)

2466

#define TCD1_CTRLC _SFR_MEM8(2370)

2467

#define TCD1_CTRLD _SFR_MEM8(2371)

2468

#define TCD1_CTRLE _SFR_MEM8(2372)

2469

#define TCD1_INTCTRLA _SFR_MEM8(2374)

2470

#define TCD1_INTCTRLB _SFR_MEM8(2375)

2471

#define TCD1_CTRLFCLR _SFR_MEM8(2376)

2472

#define TCD1_CTRLFSET _SFR_MEM8(2377)

2473

#define TCD1_CTRLGCLR _SFR_MEM8(2378)

2474

#define TCD1_CTRLGSET _SFR_MEM8(2379)

2475

#define TCD1_INTFLAGS _SFR_MEM8(2380)

2476

#define TCD1_TEMP _SFR_MEM8(2383)

2477

#define TCD1_CNT _SFR_MEM8(2400)

2478

#define TCD1_PER _SFR_MEM8(2406)

2479

#define TCD1_CCA _SFR_MEM8(2408)

2480

#define TCD1_CCB _SFR_MEM8(2410)

2481

#define TCD1_PERBUF _SFR_MEM8(2422)

2482

#define TCD1_CCABUF _SFR_MEM8(2424)

2483

#define TCD1_CCBBUF _SFR_MEM8(2426)

2484

2485

/* HIRESD - High-Resolution PWM D */

2486

#define HIRESD_CTRL _SFR_MEM8(2448)

2487

2488

/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */

2489

#define USARTD0_DATA _SFR_MEM8(2464)

2490

#define USARTD0_STATUS _SFR_MEM8(2465)

2491

#define USARTD0_CTRLA _SFR_MEM8(2467)

2492

#define USARTD0_CTRLB _SFR_MEM8(2468)

2493

#define USARTD0_CTRLC _SFR_MEM8(2469)

2494

#define USARTD0_BAUDCTRLA _SFR_MEM8(2470)

2495

#define USARTD0_BAUDCTRLB _SFR_MEM8(2471)

2496

2497

/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */

2498

#define USARTD1_DATA _SFR_MEM8(2480)

2499

#define USARTD1_STATUS _SFR_MEM8(2481)

2500

#define USARTD1_CTRLA _SFR_MEM8(2483)

2501

#define USARTD1_CTRLB _SFR_MEM8(2484)

2502

#define USARTD1_CTRLC _SFR_MEM8(2485)

2503

#define USARTD1_BAUDCTRLA _SFR_MEM8(2486)

2504

#define USARTD1_BAUDCTRLB _SFR_MEM8(2487)

2505

2506

/* SPID - Serial Peripheral Interface D */

2507

#define SPID_CTRL _SFR_MEM8(2496)

2508

#define SPID_INTCTRL _SFR_MEM8(2497)

2509

#define SPID_STATUS _SFR_MEM8(2498)

2510

#define SPID_DATA _SFR_MEM8(2499)

2511

2512

/* TCE0 - 16-bit Timer/Counter With PWM E0 */

2513

#define TCE0_CTRLA _SFR_MEM8(2560)

2514

#define TCE0_CTRLB _SFR_MEM8(2561)

2515

#define TCE0_CTRLC _SFR_MEM8(2562)

2516

#define TCE0_CTRLD _SFR_MEM8(2563)

2517

#define TCE0_CTRLE _SFR_MEM8(2564)

2518

#define TCE0_INTCTRLA _SFR_MEM8(2566)

2519

#define TCE0_INTCTRLB _SFR_MEM8(2567)

2520

#define TCE0_CTRLFCLR _SFR_MEM8(2568)

2521

#define TCE0_CTRLFSET _SFR_MEM8(2569)

2522

#define TCE0_CTRLGCLR _SFR_MEM8(2570)

2523

#define TCE0_CTRLGSET _SFR_MEM8(2571)

2524

#define TCE0_INTFLAGS _SFR_MEM8(2572)

2525

#define TCE0_TEMP _SFR_MEM8(2575)

2526

#define TCE0_CNT _SFR_MEM8(2592)

2527

#define TCE0_PER _SFR_MEM8(2598)

2528

#define TCE0_CCA _SFR_MEM8(2600)

2529

#define TCE0_CCB _SFR_MEM8(2602)

2530

#define TCE0_CCC _SFR_MEM8(2604)

2531

#define TCE0_CCD _SFR_MEM8(2606)

2532

#define TCE0_PERBUF _SFR_MEM8(2614)

2533

#define TCE0_CCABUF _SFR_MEM8(2616)

2534

#define TCE0_CCBBUF _SFR_MEM8(2618)

2535

#define TCE0_CCCBUF _SFR_MEM8(2620)

2536

#define TCE0_CCDBUF _SFR_MEM8(2622)

2537

2538

/* TCE1 - 16-bit Timer/Counter With PWM E1 */

2539

#define TCE1_CTRLA _SFR_MEM8(2624)

2540

#define TCE1_CTRLB _SFR_MEM8(2625)

2541

#define TCE1_CTRLC _SFR_MEM8(2626)

2542

#define TCE1_CTRLD _SFR_MEM8(2627)

2543

#define TCE1_CTRLE _SFR_MEM8(2628)

2544

#define TCE1_INTCTRLA _SFR_MEM8(2630)

2545

#define TCE1_INTCTRLB _SFR_MEM8(2631)

2546

#define TCE1_CTRLFCLR _SFR_MEM8(2632)

2547

#define TCE1_CTRLFSET _SFR_MEM8(2633)

2548

#define TCE1_CTRLGCLR _SFR_MEM8(2634)

2549

#define TCE1_CTRLGSET _SFR_MEM8(2635)

2550

#define TCE1_INTFLAGS _SFR_MEM8(2636)

2551

#define TCE1_TEMP _SFR_MEM8(2639)

2552

#define TCE1_CNT _SFR_MEM8(2656)

2553

#define TCE1_PER _SFR_MEM8(2662)

2554

#define TCE1_CCA _SFR_MEM8(2664)

2555

#define TCE1_CCB _SFR_MEM8(2666)

2556

#define TCE1_PERBUF _SFR_MEM8(2678)

2557

#define TCE1_CCABUF _SFR_MEM8(2680)

2558

#define TCE1_CCBBUF _SFR_MEM8(2682)

2559

2560

/* AWEXE - Advanced Waveform Extension E */

2561

#define AWEXE_CTRL _SFR_MEM8(2688)

2562

#define AWEXE_FDEVMASK _SFR_MEM8(2690)

2563

#define AWEXE_DFCTRL _SFR_MEM8(2691)

2564

#define AWEXE_STATUS _SFR_MEM8(2692)

2565

#define AWEXE_DTBOTH _SFR_MEM8(2694)

2566

#define AWEXE_DTBOTHBUF _SFR_MEM8(2695)

2567

#define AWEXE_DTLS _SFR_MEM8(2696)

2568

#define AWEXE_DTHS _SFR_MEM8(2697)

2569

#define AWEXE_DTLSBUF _SFR_MEM8(2698)

2570

#define AWEXE_DTHSBUF _SFR_MEM8(2699)

2571

#define AWEXE_OUTOVEN _SFR_MEM8(2700)

2572

2573

/* HIRESE - High-Resolution PWM E */

2574

#define HIRESE_CTRL _SFR_MEM8(2704)

2575

2576

/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */

2577

#define USARTE0_DATA _SFR_MEM8(2720)

2578

#define USARTE0_STATUS _SFR_MEM8(2721)

2579

#define USARTE0_CTRLA _SFR_MEM8(2723)

2580

#define USARTE0_CTRLB _SFR_MEM8(2724)

2581

#define USARTE0_CTRLC _SFR_MEM8(2725)

2582

#define USARTE0_BAUDCTRLA _SFR_MEM8(2726)

2583

#define USARTE0_BAUDCTRLB _SFR_MEM8(2727)

2584

2585

/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */

2586

#define USARTE1_DATA _SFR_MEM8(2736)

2587

#define USARTE1_STATUS _SFR_MEM8(2737)

2588

#define USARTE1_CTRLA _SFR_MEM8(2739)

2589

#define USARTE1_CTRLB _SFR_MEM8(2740)

2590

#define USARTE1_CTRLC _SFR_MEM8(2741)

2591

#define USARTE1_BAUDCTRLA _SFR_MEM8(2742)

2592

#define USARTE1_BAUDCTRLB _SFR_MEM8(2743)

2593

2594

/* SPIE - Serial Peripheral Interface E */

2595

#define SPIE_CTRL _SFR_MEM8(2752)

2596

#define SPIE_INTCTRL _SFR_MEM8(2753)

2597

#define SPIE_STATUS _SFR_MEM8(2754)

2598

#define SPIE_DATA _SFR_MEM8(2755)

2599

2600

/* TCF0 - 16-bit Timer/Counter With PWM F0 */

2601

#define TCF0_CTRLA _SFR_MEM8(2816)

2602

#define TCF0_CTRLB _SFR_MEM8(2817)

2603

#define TCF0_CTRLC _SFR_MEM8(2818)

2604

#define TCF0_CTRLD _SFR_MEM8(2819)

2605

#define TCF0_CTRLE _SFR_MEM8(2820)

2606

#define TCF0_INTCTRLA _SFR_MEM8(2822)

2607

#define TCF0_INTCTRLB _SFR_MEM8(2823)

2608

#define TCF0_CTRLFCLR _SFR_MEM8(2824)

2609

#define TCF0_CTRLFSET _SFR_MEM8(2825)

2610

#define TCF0_CTRLGCLR _SFR_MEM8(2826)

2611

#define TCF0_CTRLGSET _SFR_MEM8(2827)

2612

#define TCF0_INTFLAGS _SFR_MEM8(2828)

2613

#define TCF0_TEMP _SFR_MEM8(2831)

2614

#define TCF0_CNT _SFR_MEM8(2848)

2615

#define TCF0_PER _SFR_MEM8(2854)

2616

#define TCF0_CCA _SFR_MEM8(2856)

2617

#define TCF0_CCB _SFR_MEM8(2858)

2618

#define TCF0_CCC _SFR_MEM8(2860)

2619

#define TCF0_CCD _SFR_MEM8(2862)

2620

#define TCF0_PERBUF _SFR_MEM8(2870)

2621

#define TCF0_CCABUF _SFR_MEM8(2872)

2622

#define TCF0_CCBBUF _SFR_MEM8(2874)

2623

#define TCF0_CCCBUF _SFR_MEM8(2876)

2624

#define TCF0_CCDBUF _SFR_MEM8(2878)

2625

2626

/* TCF1 - 16-bit Timer/Counter With PWM F1 */

2627

#define TCF1_CTRLA _SFR_MEM8(2880)

2628

#define TCF1_CTRLB _SFR_MEM8(2881)

2629

#define TCF1_CTRLC _SFR_MEM8(2882)

2630

#define TCF1_CTRLD _SFR_MEM8(2883)

2631

#define TCF1_CTRLE _SFR_MEM8(2884)

2632

#define TCF1_INTCTRLA _SFR_MEM8(2886)

2633

#define TCF1_INTCTRLB _SFR_MEM8(2887)

2634

#define TCF1_CTRLFCLR _SFR_MEM8(2888)

2635

#define TCF1_CTRLFSET _SFR_MEM8(2889)

2636

#define TCF1_CTRLGCLR _SFR_MEM8(2890)

2637

#define TCF1_CTRLGSET _SFR_MEM8(2891)

2638

#define TCF1_INTFLAGS _SFR_MEM8(2892)

2639

#define TCF1_TEMP _SFR_MEM8(2895)

2640

#define TCF1_CNT _SFR_MEM8(2912)

2641

#define TCF1_PER _SFR_MEM8(2918)

2642

#define TCF1_CCA _SFR_MEM8(2920)

2643

#define TCF1_CCB _SFR_MEM8(2922)

2644

#define TCF1_PERBUF _SFR_MEM8(2934)

2645

#define TCF1_CCABUF _SFR_MEM8(2936)

2646

#define TCF1_CCBBUF _SFR_MEM8(2938)

2647

2648

/* HIRESF - High-Resolution PWM F */

2649

#define HIRESF_CTRL _SFR_MEM8(2960)

2650

2651

/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */

2652

#define USARTF0_DATA _SFR_MEM8(2976)

2653

#define USARTF0_STATUS _SFR_MEM8(2977)

2654

#define USARTF0_CTRLA _SFR_MEM8(2979)

2655

#define USARTF0_CTRLB _SFR_MEM8(2980)

2656

#define USARTF0_CTRLC _SFR_MEM8(2981)

2657

#define USARTF0_BAUDCTRLA _SFR_MEM8(2982)

2658

#define USARTF0_BAUDCTRLB _SFR_MEM8(2983)

2659

2660

/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */

2661

#define USARTF1_DATA _SFR_MEM8(2992)

2662

#define USARTF1_STATUS _SFR_MEM8(2993)

2663

#define USARTF1_CTRLA _SFR_MEM8(2995)

2664

#define USARTF1_CTRLB _SFR_MEM8(2996)

2665

#define USARTF1_CTRLC _SFR_MEM8(2997)

2666

#define USARTF1_BAUDCTRLA _SFR_MEM8(2998)

2667

#define USARTF1_BAUDCTRLB _SFR_MEM8(2999)

2668

2669

/* SPIF - Serial Peripheral Interface F */

2670

#define SPIF_CTRL _SFR_MEM8(3008)

2671

#define SPIF_INTCTRL _SFR_MEM8(3009)

2672

#define SPIF_STATUS _SFR_MEM8(3010)

2673

#define SPIF_DATA _SFR_MEM8(3011)

2674

2675

/* IRCOM - IR Communication Module */

2676

#define IRCOM_TXPLCTRL _SFR_MEM8(2288)

2677

#define IRCOM_RXPLCTRL _SFR_MEM8(2289)

2678

#define IRCOM_CTRL _SFR_MEM8(2290)

2679

2680

/* AES - AES Crypto Module */

2681

#define AES_CTRL _SFR_MEM8(192)

2682

#define AES_STATUS _SFR_MEM8(193)

2683

#define AES_STATE _SFR_MEM8(194)

2684

#define AES_KEY _SFR_MEM8(195)

2685

#define AES_INTCTRL _SFR_MEM8(196)

2686

2687

2688

/*================== Bitfield Definitions ================== */

2689

2690

// CCP bit masks and bit positions

2691

#define IO_bm 0x01 // TODO: Find documentation on this bit mask

2692

#define IO_bp 0 // TODO: Find documentation on this bit position

2693

#define PM_bm 0x02 // TODO: Find documentation on this bit mask

2694

#define PM_bp 1 // TODO: Find documentation on this bit position

2695

2696

// SREG bit masks and bit positions

2697

#define I_bm 0x80 // Global Interrupt Enable Flag bit mask

2698

#define I_bp 7 // Global Interrupt Enable Flag bit position

2699

#define T_bm 0x40 // Transfer Bit bit mask

2700

#define T_bp 6 // Transfer Bit bit position

2701

#define H_bm 0x20 // Half Carry Flag bit mask

2702

#define H_bp 5 // Half Carry Flag bit position

2703

#define S_bm 0x10 // N Exclusive Or V Flag bit mask

2704

#define S_bp 4 // N Exclusive Or V Flag bit position

2705

#define V_bm 0x08 // Two's Complement Overflow Flag bit mask

2706

#define V_bp 3 // Two's Complement Overflow Flag bit position

2707

#define N_bm 0x04 // Negative Flag bit mask

2708

#define N_bp 2 // Negative Flag bit position

2709

#define Z_bm 0x02 // Zero Flag bit mask

2710

#define Z_bp 1 // Zero Flag bit position

2711

#define C_bm 0x01 // Carry Flag bit mask

2712

#define C_bp 0 // Carry Flag bit position

2713

2714

2715

2716

2717

/*

2718

--------------------------------------------------------------------------

2719

XOCD - On-Chip Debug System

2720

--------------------------------------------------------------------------

2721

*/

2722

2723

/* OCD.OCDR1 bit masks and bit positions */

2724

2725

2726

#define OCD_OCDRD_bm 0x01 // OCDR Dirty bit mask

2727

#define OCD_OCDRD_bp 0 // OCDR Dirty bit position

2728

2729

2730

#if !defined (__ASSEMBLER__)

2731

/* CCP signatures */

2732

typedef enum CCP_enum

2733

{

2734

CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */

2735

CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */

2736

} CCP_t;

2737

#endif /* !defined (__ASSEMBLER__) */

2738

2739

2740

/*

2741

--------------------------------------------------------------------------

2742

CLK - Clock System

2743

--------------------------------------------------------------------------

2744

*/

2745

2746

/* CLK.CTRL bit masks and bit positions */

2747

2748

2749

#define CLK_SCLKSEL_gm 0x07 // System Clock Selection group mask

2750

#define CLK_SCLKSEL_bp 0 // System Clock Selection group position

2751

2752

#define CLK_SCLKSEL0_bm (1<<0) // System Clock Selection bit 0 mask

2753

#define CLK_SCLKSEL0_bp 0 // System Clock Selection bit 0 position

2754

#define CLK_SCLKSEL1_bm (1<<1) // System Clock Selection bit 1 mask

2755

#define CLK_SCLKSEL1_bp 1 // System Clock Selection bit 1 position

2756

#define CLK_SCLKSEL2_bm (1<<2) // System Clock Selection bit 2 mask

2757

#define CLK_SCLKSEL2_bp 2 // System Clock Selection bit 2 position

2758

2759

/* CLK.PSCTRL bit masks and bit positions */

2760

2761

2762

#define CLK_PSADIV_gm 0x7C // Prescaler A Division Factor group mask

2763

#define CLK_PSADIV_bp 2 // Prescaler A Division Factor group position

2764

2765

#define CLK_PSADIV0_bm (1<<2) // Prescaler A Division Factor bit 0 mask

2766

#define CLK_PSADIV0_bp 2 // Prescaler A Division Factor bit 0 position

2767

#define CLK_PSADIV1_bm (1<<3) // Prescaler A Division Factor bit 1 mask

2768

#define CLK_PSADIV1_bp 3 // Prescaler A Division Factor bit 1 position

2769

#define CLK_PSADIV2_bm (1<<4) // Prescaler A Division Factor bit 2 mask

2770

#define CLK_PSADIV2_bp 4 // Prescaler A Division Factor bit 2 position

2771

#define CLK_PSADIV3_bm (1<<5) // Prescaler A Division Factor bit 3 mask

2772

#define CLK_PSADIV3_bp 5 // Prescaler A Division Factor bit 3 position

2773

#define CLK_PSADIV4_bm (1<<6) // Prescaler A Division Factor bit 4 mask

2774

#define CLK_PSADIV4_bp 6 // Prescaler A Division Factor bit 4 position

2775

#define CLK_PSBCDIV_gm 0x03 // Prescaler B and D Division factor group mask

2776

#define CLK_PSBCDIV_bp 0 // Prescaler B and D Division factor group position

2777

2778

#define CLK_PSBCDIV0_bm (1<<0) // Prescaler B and D Division factor bit 0 mask

2779

#define CLK_PSBCDIV0_bp 0 // Prescaler B and D Division factor bit 0 position

2780

#define CLK_PSBCDIV1_bm (1<<1) // Prescaler B and D Division factor bit 1 mask

2781

#define CLK_PSBCDIV1_bp 1 // Prescaler B and D Division factor bit 1 position

2782

2783

/* CLK.LOCK bit masks and bit positions */

2784

2785

2786

#define CLK_LOCK_bm 0x01 // Clock System Lock bit mask

2787

#define CLK_LOCK_bp 0 // Clock System Lock bit position

2788

2789

/* CLK.RTCCTRL bit masks and bit positions */

2790

2791

2792

#define CLK_RTCSRC_gm 0x0E // Clock Source group mask

2793

#define CLK_RTCSRC_bp 1 // Clock Source group position

2794

2795

#define CLK_RTCSRC0_bm (1<<1) // Clock Source bit 0 mask

2796

#define CLK_RTCSRC0_bp 1 // Clock Source bit 0 position

2797

#define CLK_RTCSRC1_bm (1<<2) // Clock Source bit 1 mask

2798

#define CLK_RTCSRC1_bp 2 // Clock Source bit 1 position

2799

#define CLK_RTCSRC2_bm (1<<3) // Clock Source bit 2 mask

2800

#define CLK_RTCSRC2_bp 3 // Clock Source bit 2 position

2801

#define CLK_RTCEN_bm 0x01 // RTC Clock Source Enable bit mask

2802

#define CLK_RTCEN_bp 0 // RTC Clock Source Enable bit position

2803

2804

/* PR.PR bit masks and bit positions */

2805

2806

2807

#define PR_EBI_bm 0x08 // External Bus Interface bit mask

2808

#define PR_EBI_bp 3 // External Bus Interface bit position

2809

#define PR_RTC_bm 0x04 // Real-time Counter bit mask

2810

#define PR_RTC_bp 2 // Real-time Counter bit position

2811

#define PR_EVSYS_bm 0x02 // Event System bit mask

2812

#define PR_EVSYS_bp 1 // Event System bit position

2813

#define PR_DMA_bm 0x01 // DMA-Controller bit mask

2814

#define PR_DMA_bp 0 // DMA-Controller bit position

2815

2816

/* PR.PRPA bit masks and bit positions */

2817

2818

2819

#define PR_DAC_bm 0x04 // Port A DAC bit mask

2820

#define PR_DAC_bp 2 // Port A DAC bit position

2821

#define PR_ADC_bm 0x02 // Port A ADC bit mask

2822

#define PR_ADC_bp 1 // Port A ADC bit position

2823

#define PR_AC_bm 0x01 // Port A Analog Comparator bit mask

2824

#define PR_AC_bp 0 // Port A Analog Comparator bit position

2825

2826

/* PR.PRPB bit masks and bit positions */

2827

2828

2829

/* Masks for DAC aready defined */

2830

2831

/* Masks for ADC aready defined */

2832

2833

/* Masks for AC aready defined */

2834

2835

2836

/* PR.PRPC bit masks and bit positions */

2837

2838

2839

#define PR_TWI_bm 0x40 // Port C Two-wire Interface bit mask

2840

#define PR_TWI_bp 6 // Port C Two-wire Interface bit position

2841

#define PR_USART1_bm 0x20 // Port C USART1 bit mask

2842

#define PR_USART1_bp 5 // Port C USART1 bit position

2843

#define PR_USART0_bm 0x10 // Port C USART0 bit mask

2844

#define PR_USART0_bp 4 // Port C USART0 bit position

2845

#define PR_SPI_bm 0x08 // Port C SPI bit mask

2846

#define PR_SPI_bp 3 // Port C SPI bit position

2847

#define PR_HIRES_bm 0x04 // Port C AWEX bit mask

2848

#define PR_HIRES_bp 2 // Port C AWEX bit position

2849

#define PR_TC1_bm 0x02 // Port C Timer/Counter1 bit mask

2850

#define PR_TC1_bp 1 // Port C Timer/Counter1 bit position

2851

#define PR_TC0_bm 0x01 // Port C Timer/Counter0 bit mask

2852

#define PR_TC0_bp 0 // Port C Timer/Counter0 bit position

2853

2854

/* PR.PRPD bit masks and bit positions */

2855

2856

2857

/* Masks for TWI aready defined */

2858

2859

/* Masks for USART1 aready defined */

2860

2861

/* Masks for USART0 aready defined */

2862

2863

/* Masks for SPI aready defined */

2864

2865

/* Masks for HIRES aready defined */

2866

2867

/* Masks for TC1 aready defined */

2868

2869

/* Masks for TC0 aready defined */

2870

2871

2872

/* PR.PRPE bit masks and bit positions */

2873

2874

2875

/* Masks for TWI aready defined */

2876

2877

/* Masks for USART1 aready defined */

2878

2879

/* Masks for USART0 aready defined */

2880

2881

/* Masks for SPI aready defined */

2882

2883

/* Masks for HIRES aready defined */

2884

2885

/* Masks for TC1 aready defined */

2886

2887

/* Masks for TC0 aready defined */

2888

2889

2890

/* PR.PRPF bit masks and bit positions */

2891

2892

2893

/* Masks for TWI aready defined */

2894

2895

/* Masks for USART1 aready defined */

2896

2897

/* Masks for USART0 aready defined */

2898

2899

/* Masks for SPI aready defined */

2900

2901

/* Masks for HIRES aready defined */

2902

2903

/* Masks for TC1 aready defined */

2904

2905

/* Masks for TC0 aready defined */

2906

2907

2908

#if !defined (__ASSEMBLER__)

2909

/* System Clock Selection */

2910

typedef enum CLK_SCLKSEL_enum

2911

{

2912

CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */

2913

CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */

2914

CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */

2915

CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */

2916

CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */

2917

} CLK_SCLKSEL_t;

2918

#endif /* !defined (__ASSEMBLER__) */

2919

2920

#if !defined (__ASSEMBLER__)

2921

/* Prescaler A Division Factor */

2922

typedef enum CLK_PSADIV_enum

2923

{

2924

CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */

2925

CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */

2926

CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */

2927

CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */

2928

CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */

2929

CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */

2930

CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */

2931

CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */

2932

CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */

2933

CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */

2934

} CLK_PSADIV_t;

2935

#endif /* !defined (__ASSEMBLER__) */

2936

2937

#if !defined (__ASSEMBLER__)

2938

/* Prescaler B and C Division Factor */

2939

typedef enum CLK_PSBCDIV_enum

2940

{

2941

CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */

2942

CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */

2943

CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */

2944

CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */

2945

} CLK_PSBCDIV_t;

2946

#endif /* !defined (__ASSEMBLER__) */

2947

2948

#if !defined (__ASSEMBLER__)

2949

/* RTC Clock Source */

2950

typedef enum CLK_RTCSRC_enum

2951

{

2952

CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */

2953

CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */

2954

CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */

2955

CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */

2956

} CLK_RTCSRC_t;

2957

#endif /* !defined (__ASSEMBLER__) */

2958

2959

2960

/*

2961

--------------------------------------------------------------------------

2962

SLEEP - Sleep Controller

2963

--------------------------------------------------------------------------

2964

*/

2965

2966

/* SLEEP.CTRL bit masks and bit positions */

2967

2968

2969

#define SLEEP_SMODE_gm 0x0E // Sleep Mode group mask

2970

#define SLEEP_SMODE_bp 1 // Sleep Mode group position

2971

2972

#define SLEEP_SMODE0_bm (1<<1) // Sleep Mode bit 0 mask

2973

#define SLEEP_SMODE0_bp 1 // Sleep Mode bit 0 position

2974

#define SLEEP_SMODE1_bm (1<<2) // Sleep Mode bit 1 mask

2975

#define SLEEP_SMODE1_bp 2 // Sleep Mode bit 1 position

2976

#define SLEEP_SMODE2_bm (1<<3) // Sleep Mode bit 2 mask

2977

#define SLEEP_SMODE2_bp 3 // Sleep Mode bit 2 position

2978

#define SLEEP_SEN_bm 0x01 // Sleep Enable bit mask

2979

#define SLEEP_SEN_bp 0 // Sleep Enable bit position

2980

2981

#if !defined (__ASSEMBLER__)

2982

/* Sleep Mode */

2983

typedef enum SLEEP_SMODE_enum

2984

{

2985

SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */

2986

SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */

2987

SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */

2988

SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */

2989

SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */

2990

} SLEEP_SMODE_t;

2991

#endif /* !defined (__ASSEMBLER__) */

2992

2993

2994

/*

2995

--------------------------------------------------------------------------

2996

OSC - Oscillator

2997

--------------------------------------------------------------------------

2998

*/

2999

3000

/* OSC.CTRL bit masks and bit positions */

3001

3002

3003

#define OSC_PLLEN_bm 0x10 // PLL Enable bit mask

3004

#define OSC_PLLEN_bp 4 // PLL Enable bit position

3005

#define OSC_XOSCEN_bm 0x08 // External Oscillator Enable bit mask

3006

#define OSC_XOSCEN_bp 3 // External Oscillator Enable bit position

3007

#define OSC_RC32KEN_bm 0x04 // Internal 32kHz RC Oscillator Enable bit mask

3008

#define OSC_RC32KEN_bp 2 // Internal 32kHz RC Oscillator Enable bit position

3009

#define OSC_RC32MEN_bm 0x02 // Internal 32MHz RC Oscillator Enable bit mask

3010

#define OSC_RC32MEN_bp 1 // Internal 32MHz RC Oscillator Enable bit position

3011

#define OSC_RC2MEN_bm 0x01 // Internal 2MHz RC Oscillator Enable bit mask

3012

#define OSC_RC2MEN_bp 0 // Internal 2MHz RC Oscillator Enable bit position

3013

3014

/* OSC.STATUS bit masks and bit positions */

3015

3016

3017

#define OSC_PLLRDY_bm 0x10 // PLL Ready bit mask

3018

#define OSC_PLLRDY_bp 4 // PLL Ready bit position

3019

#define OSC_XOSCRDY_bm 0x08 // External Oscillator Ready bit mask

3020

#define OSC_XOSCRDY_bp 3 // External Oscillator Ready bit position

3021

#define OSC_RC32KRDY_bm 0x04 // Internal 32kHz RC Oscillator Ready bit mask

3022

#define OSC_RC32KRDY_bp 2 // Internal 32kHz RC Oscillator Ready bit position

3023

#define OSC_RC32MRDY_bm 0x02 // Internal 32MHz RC Oscillator Ready bit mask

3024

#define OSC_RC32MRDY_bp 1 // Internal 32MHz RC Oscillator Ready bit position

3025

#define OSC_RC2MRDY_bm 0x01 // Internal 2MHz RC Oscillator Ready bit mask

3026

#define OSC_RC2MRDY_bp 0 // Internal 2MHz RC Oscillator Ready bit position

3027

3028

/* OSC.XOSCCTRL bit masks and bit positions */

3029

3030

3031

#define OSC_FRQRANGE_gm 0xC0 // Frequency Range group mask

3032

#define OSC_FRQRANGE_bp 6 // Frequency Range group position

3033

3034

#define OSC_FRQRANGE0_bm (1<<6) // Frequency Range bit 0 mask

3035

#define OSC_FRQRANGE0_bp 6 // Frequency Range bit 0 position

3036

#define OSC_FRQRANGE1_bm (1<<7) // Frequency Range bit 1 mask

3037

#define OSC_FRQRANGE1_bp 7 // Frequency Range bit 1 position

3038

#define OSC_X32KLPM_bm 0x20 // 32kHz XTAL OSC Low-power Mode bit mask

3039

#define OSC_X32KLPM_bp 5 // 32kHz XTAL OSC Low-power Mode bit position

3040

#define OSC_XOSCSEL_gm 0x0F // External Oscillator Selection and Startup Time group mask

3041

#define OSC_XOSCSEL_bp 0 // External Oscillator Selection and Startup Time group position

3042

3043

#define OSC_XOSCSEL0_bm (1<<0) // External Oscillator Selection and Startup Time bit 0 mask

3044

#define OSC_XOSCSEL0_bp 0 // External Oscillator Selection and Startup Time bit 0 position

3045

#define OSC_XOSCSEL1_bm (1<<1) // External Oscillator Selection and Startup Time bit 1 mask

3046

#define OSC_XOSCSEL1_bp 1 // External Oscillator Selection and Startup Time bit 1 position

3047

#define OSC_XOSCSEL2_bm (1<<2) // External Oscillator Selection and Startup Time bit 2 mask

3048

#define OSC_XOSCSEL2_bp 2 // External Oscillator Selection and Startup Time bit 2 position

3049

#define OSC_XOSCSEL3_bm (1<<3) // External Oscillator Selection and Startup Time bit 3 mask

3050

#define OSC_XOSCSEL3_bp 3 // External Oscillator Selection and Startup Time bit 3 position

3051

3052

/* OSC.XOSCFAIL bit masks and bit positions */

3053

3054

3055

#define OSC_XOSCFDIF_bm 0x02 // Failure Detection Interrupt Flag bit mask

3056

#define OSC_XOSCFDIF_bp 1 // Failure Detection Interrupt Flag bit position

3057

#define OSC_XOSCFDEN_bm 0x01 // Failure Detection Enable bit mask

3058

#define OSC_XOSCFDEN_bp 0 // Failure Detection Enable bit position

3059

3060

/* OSC.PLLCTRL bit masks and bit positions */

3061

3062

3063

#define OSC_PLLSRC_gm 0xC0 // Clock Source group mask

3064

#define OSC_PLLSRC_bp 6 // Clock Source group position

3065

3066

#define OSC_PLLSRC0_bm (1<<6) // Clock Source bit 0 mask

3067

#define OSC_PLLSRC0_bp 6 // Clock Source bit 0 position

3068

#define OSC_PLLSRC1_bm (1<<7) // Clock Source bit 1 mask

3069

#define OSC_PLLSRC1_bp 7 // Clock Source bit 1 position

3070

#define OSC_PLLFAC_gm 0x1F // Multiplication Factor group mask

3071

#define OSC_PLLFAC_bp 0 // Multiplication Factor group position

3072

3073

#define OSC_PLLFAC0_bm (1<<0) // Multiplication Factor bit 0 mask

3074

#define OSC_PLLFAC0_bp 0 // Multiplication Factor bit 0 position

3075

#define OSC_PLLFAC1_bm (1<<1) // Multiplication Factor bit 1 mask

3076

#define OSC_PLLFAC1_bp 1 // Multiplication Factor bit 1 position

3077

#define OSC_PLLFAC2_bm (1<<2) // Multiplication Factor bit 2 mask

3078

#define OSC_PLLFAC2_bp 2 // Multiplication Factor bit 2 position

3079

#define OSC_PLLFAC3_bm (1<<3) // Multiplication Factor bit 3 mask

3080

#define OSC_PLLFAC3_bp 3 // Multiplication Factor bit 3 position

3081

#define OSC_PLLFAC4_bm (1<<4) // Multiplication Factor bit 4 mask

3082

#define OSC_PLLFAC4_bp 4 // Multiplication Factor bit 4 position

3083

3084

/* OSC.DFLLCTRL bit masks and bit positions */

3085

3086

3087

#define OSC_RC32MCREF_bm 0x02 // 32MHz Calibration Reference bit mask

3088

#define OSC_RC32MCREF_bp 1 // 32MHz Calibration Reference bit position

3089

#define OSC_RC2MCREF_bm 0x01 // 2MHz Calibration Reference bit mask

3090

#define OSC_RC2MCREF_bp 0 // 2MHz Calibration Reference bit position

3091

3092

#if !defined (__ASSEMBLER__)

3093

/* Frequency Range */

3094

typedef enum OSC_FRQRANGE_enum

3095

{

3096

OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */

3097

OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */

3098

OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */

3099

OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */

3100

} OSC_FRQRANGE_t;

3101

#endif /* !defined (__ASSEMBLER__) */

3102

3103

#if !defined (__ASSEMBLER__)

3104

/* External Oscillator Selection and Startup Time */

3105

typedef enum OSC_XOSCSEL_enum

3106

{

3107

OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */

3108

OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */

3109

OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */

3110

OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */

3111

OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */

3112

} OSC_XOSCSEL_t;

3113

#endif /* !defined (__ASSEMBLER__) */

3114

3115

#if !defined (__ASSEMBLER__)

3116

/* PLL Clock Source */

3117

typedef enum OSC_PLLSRC_enum

3118

{

3119

OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */

3120

OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */

3121

OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */

3122

} OSC_PLLSRC_t;

3123

#endif /* !defined (__ASSEMBLER__) */

3124

3125

3126

/*

3127

--------------------------------------------------------------------------

3128

DFLL - DFLL

3129

--------------------------------------------------------------------------

3130

*/

3131

3132

/* DFLL.CALA bit masks and bit positions */

3133

3134

3135

#define DFLL_CALL_gm 0xFE // DFLL Calibration bits [6:0] group mask

3136

#define DFLL_CALL_bp 1 // DFLL Calibration bits [6:0] group position

3137

3138

#define DFLL_CALL0_bm (1<<1) // DFLL Calibration bits [6:0] bit 0 mask

3139

#define DFLL_CALL0_bp 1 // DFLL Calibration bits [6:0] bit 0 position

3140

#define DFLL_CALL1_bm (1<<2) // DFLL Calibration bits [6:0] bit 1 mask

3141

#define DFLL_CALL1_bp 2 // DFLL Calibration bits [6:0] bit 1 position

3142

#define DFLL_CALL2_bm (1<<3) // DFLL Calibration bits [6:0] bit 2 mask

3143

#define DFLL_CALL2_bp 3 // DFLL Calibration bits [6:0] bit 2 position

3144

#define DFLL_CALL3_bm (1<<4) // DFLL Calibration bits [6:0] bit 3 mask

3145

#define DFLL_CALL3_bp 4 // DFLL Calibration bits [6:0] bit 3 position

3146

#define DFLL_CALL4_bm (1<<5) // DFLL Calibration bits [6:0] bit 4 mask

3147

#define DFLL_CALL4_bp 5 // DFLL Calibration bits [6:0] bit 4 position

3148

#define DFLL_CALL5_bm (1<<6) // DFLL Calibration bits [6:0] bit 5 mask

3149

#define DFLL_CALL5_bp 6 // DFLL Calibration bits [6:0] bit 5 position

3150

#define DFLL_CALL6_bm (1<<7) // DFLL Calibration bits [6:0] bit 6 mask

3151

#define DFLL_CALL6_bp 7 // DFLL Calibration bits [6:0] bit 6 position

3152

#define DFLL_ENABLE_bm 0x01 // DFLL Enable bit mask

3153

#define DFLL_ENABLE_bp 0 // DFLL Enable bit position

3154

3155

/* DFLL.CALB bit masks and bit positions */

3156

3157

3158

#define DFLL_CALH_gm 0x1F // DFLL Calibration bits [11:7] group mask

3159

#define DFLL_CALH_bp 0 // DFLL Calibration bits [11:7] group position

3160

3161

#define DFLL_CALH0_bm (1<<0) // DFLL Calibration bits [11:7] bit 0 mask

3162

#define DFLL_CALH0_bp 0 // DFLL Calibration bits [11:7] bit 0 position

3163

#define DFLL_CALH1_bm (1<<1) // DFLL Calibration bits [11:7] bit 1 mask

3164

#define DFLL_CALH1_bp 1 // DFLL Calibration bits [11:7] bit 1 position

3165

#define DFLL_CALH2_bm (1<<2) // DFLL Calibration bits [11:7] bit 2 mask

3166

#define DFLL_CALH2_bp 2 // DFLL Calibration bits [11:7] bit 2 position

3167

#define DFLL_CALH3_bm (1<<3) // DFLL Calibration bits [11:7] bit 3 mask

3168

#define DFLL_CALH3_bp 3 // DFLL Calibration bits [11:7] bit 3 position

3169

#define DFLL_CALH4_bm (1<<4) // DFLL Calibration bits [11:7] bit 4 mask

3170

#define DFLL_CALH4_bp 4 // DFLL Calibration bits [11:7] bit 4 position

3171

3172

3173

/*

3174

--------------------------------------------------------------------------

3175

RST - Reset

3176

--------------------------------------------------------------------------

3177

*/

3178

3179

/* RST.STATUS bit masks and bit positions */

3180

3181

3182

#define RST_SDRF_bm 0x40 // Spike Detection Reset Flag bit mask

3183

#define RST_SDRF_bp 6 // Spike Detection Reset Flag bit position

3184

#define RST_SRF_bm 0x20 // Software Reset Flag bit mask

3185

#define RST_SRF_bp 5 // Software Reset Flag bit position

3186

#define RST_PDIRF_bm 0x10 // Programming and Debug Interface Interface Reset Flag bit mask

3187

#define RST_PDIRF_bp 4 // Programming and Debug Interface Interface Reset Flag bit position

3188

#define RST_WDRF_bm 0x08 // Watchdog Reset Flag bit mask

3189

#define RST_WDRF_bp 3 // Watchdog Reset Flag bit position

3190

#define RST_BORF_bm 0x04 // Brown-out Reset Flag bit mask

3191

#define RST_BORF_bp 2 // Brown-out Reset Flag bit position

3192

#define RST_EXTRF_bm 0x02 // External Reset Flag bit mask

3193

#define RST_EXTRF_bp 1 // External Reset Flag bit position

3194

#define RST_PORF_bm 0x01 // Power-on Reset Flag bit mask

3195

#define RST_PORF_bp 0 // Power-on Reset Flag bit position

3196

3197

/* RST.CTRL bit masks and bit positions */

3198

3199

3200

#define RST_SWRST_bm 0x01 // Software Reset bit mask

3201

#define RST_SWRST_bp 0 // Software Reset bit position

3202

3203

3204

/*

3205

--------------------------------------------------------------------------

3206

WDT - Watch-Dog Timer

3207

--------------------------------------------------------------------------

3208

*/

3209

3210

/* WDT.CTRL bit masks and bit positions */

3211

3212

3213

#define WDT_PER_gm 0x3C // Period group mask

3214

#define WDT_PER_bp 2 // Period group position

3215

3216

#define WDT_PER0_bm (1<<2) // Period bit 0 mask

3217

#define WDT_PER0_bp 2 // Period bit 0 position

3218

#define WDT_PER1_bm (1<<3) // Period bit 1 mask

3219

#define WDT_PER1_bp 3 // Period bit 1 position

3220

#define WDT_PER2_bm (1<<4) // Period bit 2 mask

3221

#define WDT_PER2_bp 4 // Period bit 2 position

3222

#define WDT_PER3_bm (1<<5) // Period bit 3 mask

3223

#define WDT_PER3_bp 5 // Period bit 3 position

3224

#define WDT_ENABLE_bm 0x02 // Enable bit mask

3225

#define WDT_ENABLE_bp 1 // Enable bit position

3226

#define WDT_CEN_bm 0x01 // Change Enable bit mask

3227

#define WDT_CEN_bp 0 // Change Enable bit position

3228

3229

/* WDT.WINCTRL bit masks and bit positions */

3230

3231

3232

#define WDT_WPER_gm 0x3C // Windowed Mode Period group mask

3233

#define WDT_WPER_bp 2 // Windowed Mode Period group position

3234

3235

#define WDT_WPER0_bm (1<<2) // Windowed Mode Period bit 0 mask

3236

#define WDT_WPER0_bp 2 // Windowed Mode Period bit 0 position

3237

#define WDT_WPER1_bm (1<<3) // Windowed Mode Period bit 1 mask

3238

#define WDT_WPER1_bp 3 // Windowed Mode Period bit 1 position

3239

#define WDT_WPER2_bm (1<<4) // Windowed Mode Period bit 2 mask

3240

#define WDT_WPER2_bp 4 // Windowed Mode Period bit 2 position

3241

#define WDT_WPER3_bm (1<<5) // Windowed Mode Period bit 3 mask

3242

#define WDT_WPER3_bp 5 // Windowed Mode Period bit 3 position

3243

#define WDT_WEN_bm 0x02 // Windowed Mode Enable bit mask

3244

#define WDT_WEN_bp 1 // Windowed Mode Enable bit position

3245

#define WDT_WCEN_bm 0x01 // Windowed Mode Change Enable bit mask

3246

#define WDT_WCEN_bp 0 // Windowed Mode Change Enable bit position

3247

3248

/* WDT.STATUS bit masks and bit positions */

3249

3250

3251

#define WDT_SYNCBUSY_bm 0x01 // Syncronization busy bit mask

3252

#define WDT_SYNCBUSY_bp 0 // Syncronization busy bit position

3253

3254

#if !defined (__ASSEMBLER__)

3255

/* */

3256

typedef enum WDT_PER_enum

3257

{

3258

WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */

3259

WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */

3260

WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */

3261

WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */

3262

WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */

3263

WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */

3264

WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */

3265

WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */

3266

WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */

3267

WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */

3268

WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */

3269

} WDT_PER_t;

3270

#endif /* !defined (__ASSEMBLER__) */

3271

3272

#if !defined (__ASSEMBLER__)

3273

/* */

3274

typedef enum WDT_WPER_enum

3275

{

3276

WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */

3277

WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */

3278

WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */

3279

WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */

3280

WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */

3281

WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */

3282

WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */

3283

WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */

3284

WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */

3285

WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */

3286

WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */

3287

} WDT_WPER_t;

3288

#endif /* !defined (__ASSEMBLER__) */

3289

3290

3291

/*

3292

--------------------------------------------------------------------------

3293

MCU - MCU

3294

--------------------------------------------------------------------------

3295

*/

3296

3297

/* MCU.MCUCR bit masks and bit positions */

3298

3299

3300

#define MCU_JTAGD_bm 0x01 // JTAG Disable bit mask

3301

#define MCU_JTAGD_bp 0 // JTAG Disable bit position

3302

3303

/* MCU.EVSYSLOCK bit masks and bit positions */

3304

3305

3306

#define MCU_EVSYS1LOCK_bm 0x10 // Event Channel 4-7 Lock bit mask

3307

#define MCU_EVSYS1LOCK_bp 4 // Event Channel 4-7 Lock bit position

3308

#define MCU_EVSYS0LOCK_bm 0x01 // Event Channel 0-3 Lock bit mask

3309

#define MCU_EVSYS0LOCK_bp 0 // Event Channel 0-3 Lock bit position

3310

3311

/* MCU.AWEXLOCK bit masks and bit positions */

3312

3313

3314

#define MCU_AWEXELOCK_bm 0x04 // AWeX on T/C E0 Lock bit mask

3315

#define MCU_AWEXELOCK_bp 2 // AWeX on T/C E0 Lock bit position

3316

#define MCU_AWEXCLOCK_bm 0x01 // AWeX on T/C C0 Lock bit mask

3317

#define MCU_AWEXCLOCK_bp 0 // AWeX on T/C C0 Lock bit position

3318

3319

3320

/*

3321

--------------------------------------------------------------------------

3322

PMIC - Programmable Multi-level Interrupt Controller

3323

--------------------------------------------------------------------------

3324

*/

3325

3326

/* PMIC.STATUS bit masks and bit positions */

3327

3328

3329

#define PMIC_NMIEX_bm 0x80 // Non-maskable Interrupt Executing bit mask

3330

#define PMIC_NMIEX_bp 7 // Non-maskable Interrupt Executing bit position

3331

#define PMIC_HILVLEX_bm 0x04 // High Level Interrupt Executing bit mask

3332

#define PMIC_HILVLEX_bp 2 // High Level Interrupt Executing bit position

3333

#define PMIC_MEDLVLEX_bm 0x02 // Medium Level Interrupt Executing bit mask

3334

#define PMIC_MEDLVLEX_bp 1 // Medium Level Interrupt Executing bit position

3335

#define PMIC_LOLVLEX_bm 0x01 // Low Level Interrupt Executing bit mask

3336

#define PMIC_LOLVLEX_bp 0 // Low Level Interrupt Executing bit position

3337

3338

/* PMIC.CTRL bit masks and bit positions */

3339

3340

3341

#define PMIC_RREN_bm 0x80 // Round-Robin Priority Enable bit mask

3342

#define PMIC_RREN_bp 7 // Round-Robin Priority Enable bit position

3343

#define PMIC_IVSEL_bm 0x40 // Interrupt Vector Select bit mask

3344

#define PMIC_IVSEL_bp 6 // Interrupt Vector Select bit position

3345

#define PMIC_HILVLEN_bm 0x04 // High Level Enable bit mask

3346

#define PMIC_HILVLEN_bp 2 // High Level Enable bit position

3347

#define PMIC_MEDLVLEN_bm 0x02 // Medium Level Enable bit mask

3348

#define PMIC_MEDLVLEN_bp 1 // Medium Level Enable bit position

3349

#define PMIC_LOLVLEN_bm 0x01 // Low Level Enable bit mask

3350

#define PMIC_LOLVLEN_bp 0 // Low Level Enable bit position

3351

3352

3353

/*

3354

--------------------------------------------------------------------------

3355

DMA - DMA Controller

3356

--------------------------------------------------------------------------

3357

*/

3358

3359

/* DMA_CH.CTRLA bit masks and bit positions */

3360

3361

3362

#define DMA_CH_ENABLE_bm 0x80 // Channel Enable bit mask

3363

#define DMA_CH_ENABLE_bp 7 // Channel Enable bit position

3364

#define DMA_CH_RESET_bm 0x40 // Channel Software Reset bit mask

3365

#define DMA_CH_RESET_bp 6 // Channel Software Reset bit position

3366

#define DMA_CH_REPEAT_bm 0x20 // Channel Repeat Mode bit mask

3367

#define DMA_CH_REPEAT_bp 5 // Channel Repeat Mode bit position

3368

#define DMA_CH_TRFREQ_bm 0x10 // Channel Transfer Request bit mask

3369

#define DMA_CH_TRFREQ_bp 4 // Channel Transfer Request bit position

3370

#define DMA_CH_SINGLE_bm 0x04 // Channel Single Shot Data Transfer bit mask

3371

#define DMA_CH_SINGLE_bp 2 // Channel Single Shot Data Transfer bit position

3372

#define DMA_CH_BURSTLEN_gm 0x03 // Channel Transfer Mode group mask

3373

#define DMA_CH_BURSTLEN_bp 0 // Channel Transfer Mode group position

3374

3375

#define DMA_CH_BURSTLEN0_bm (1<<0) // Channel Transfer Mode bit 0 mask

3376

#define DMA_CH_BURSTLEN0_bp 0 // Channel Transfer Mode bit 0 position

3377

#define DMA_CH_BURSTLEN1_bm (1<<1) // Channel Transfer Mode bit 1 mask

3378

#define DMA_CH_BURSTLEN1_bp 1 // Channel Transfer Mode bit 1 position

3379

3380

/* DMA_CH.CTRLB bit masks and bit positions */

3381

3382

3383

#define DMA_CH_CHBUSY_bm 0x80 // Block Transfer Busy bit mask

3384

#define DMA_CH_CHBUSY_bp 7 // Block Transfer Busy bit position

3385

#define DMA_CH_CHPEND_bm 0x40 // Block Transfer Pending bit mask

3386

#define DMA_CH_CHPEND_bp 6 // Block Transfer Pending bit position

3387

#define DMA_CH_ERRIF_bm 0x20 // Block Transfer Error Interrupt Flag bit mask

3388

#define DMA_CH_ERRIF_bp 5 // Block Transfer Error Interrupt Flag bit position

3389

#define DMA_CH_TRNIF_bm 0x10 // Transaction Complete Interrup Flag bit mask

3390

#define DMA_CH_TRNIF_bp 4 // Transaction Complete Interrup Flag bit position

3391

#define DMA_CH_ERRINTLVL_gm 0x0C // Transfer Error Interrupt Level group mask

3392

#define DMA_CH_ERRINTLVL_bp 2 // Transfer Error Interrupt Level group position

3393

3394

#define DMA_CH_ERRINTLVL0_bm (1<<2) // Transfer Error Interrupt Level bit 0 mask

3395

#define DMA_CH_ERRINTLVL0_bp 2 // Transfer Error Interrupt Level bit 0 position

3396

#define DMA_CH_ERRINTLVL1_bm (1<<3) // Transfer Error Interrupt Level bit 1 mask

3397

#define DMA_CH_ERRINTLVL1_bp 3 // Transfer Error Interrupt Level bit 1 position

3398

#define DMA_CH_TRNINTLVL_gm 0x03 // Transaction Complete Interrupt Level group mask

3399

#define DMA_CH_TRNINTLVL_bp 0 // Transaction Complete Interrupt Level group position

3400

3401

#define DMA_CH_TRNINTLVL0_bm (1<<0) // Transaction Complete Interrupt Level bit 0 mask

3402

#define DMA_CH_TRNINTLVL0_bp 0 // Transaction Complete Interrupt Level bit 0 position

3403

#define DMA_CH_TRNINTLVL1_bm (1<<1) // Transaction Complete Interrupt Level bit 1 mask

3404

#define DMA_CH_TRNINTLVL1_bp 1 // Transaction Complete Interrupt Level bit 1 position

3405

3406

/* DMA_CH.ADDRCTRL bit masks and bit positions */

3407

3408

3409

#define DMA_CH_SRCRELOAD_gm 0xC0 // Channel Source Address Reload group mask

3410

#define DMA_CH_SRCRELOAD_bp 6 // Channel Source Address Reload group position

3411

3412

#define DMA_CH_SRCRELOAD0_bm (1<<6) // Channel Source Address Reload bit 0 mask

3413

#define DMA_CH_SRCRELOAD0_bp 6 // Channel Source Address Reload bit 0 position

3414

#define DMA_CH_SRCRELOAD1_bm (1<<7) // Channel Source Address Reload bit 1 mask

3415

#define DMA_CH_SRCRELOAD1_bp 7 // Channel Source Address Reload bit 1 position

3416

#define DMA_CH_SRCDIR_gm 0x30 // Channel Source Address Mode group mask

3417

#define DMA_CH_SRCDIR_bp 4 // Channel Source Address Mode group position

3418

3419

#define DMA_CH_SRCDIR0_bm (1<<4) // Channel Source Address Mode bit 0 mask

3420

#define DMA_CH_SRCDIR0_bp 4 // Channel Source Address Mode bit 0 position

3421

#define DMA_CH_SRCDIR1_bm (1<<5) // Channel Source Address Mode bit 1 mask

3422

#define DMA_CH_SRCDIR1_bp 5 // Channel Source Address Mode bit 1 position

3423

#define DMA_CH_DESTRELOAD_gm 0x0C // Channel Destination Address Reload group mask

3424

#define DMA_CH_DESTRELOAD_bp 2 // Channel Destination Address Reload group position

3425

3426

#define DMA_CH_DESTRELOAD0_bm (1<<2) // Channel Destination Address Reload bit 0 mask

3427

#define DMA_CH_DESTRELOAD0_bp 2 // Channel Destination Address Reload bit 0 position

3428

#define DMA_CH_DESTRELOAD1_bm (1<<3) // Channel Destination Address Reload bit 1 mask

3429

#define DMA_CH_DESTRELOAD1_bp 3 // Channel Destination Address Reload bit 1 position

3430

#define DMA_CH_DESTDIR_gm 0x03 // Channel Destination Address Mode group mask

3431

#define DMA_CH_DESTDIR_bp 0 // Channel Destination Address Mode group position

3432

3433

#define DMA_CH_DESTDIR0_bm (1<<0) // Channel Destination Address Mode bit 0 mask

3434

#define DMA_CH_DESTDIR0_bp 0 // Channel Destination Address Mode bit 0 position

3435

#define DMA_CH_DESTDIR1_bm (1<<1) // Channel Destination Address Mode bit 1 mask

3436

#define DMA_CH_DESTDIR1_bp 1 // Channel Destination Address Mode bit 1 position

3437

3438

/* DMA.CTRL bit masks and bit positions */

3439

3440

3441

#define DMA_ENABLE_bm 0x80 // Enable bit mask

3442

#define DMA_ENABLE_bp 7 // Enable bit position

3443

#define DMA_RESET_bm 0x40 // Software Reset bit mask

3444

#define DMA_RESET_bp 6 // Software Reset bit position

3445

#define DMA_DBUFMODE_gm 0x0C // Double Buffering Mode group mask

3446

#define DMA_DBUFMODE_bp 2 // Double Buffering Mode group position

3447

3448

#define DMA_DBUFMODE0_bm (1<<2) // Double Buffering Mode bit 0 mask

3449

#define DMA_DBUFMODE0_bp 2 // Double Buffering Mode bit 0 position

3450

#define DMA_DBUFMODE1_bm (1<<3) // Double Buffering Mode bit 1 mask

3451

#define DMA_DBUFMODE1_bp 3 // Double Buffering Mode bit 1 position

3452

#define DMA_PRIMODE_gm 0x03 // Channel Priority Mode group mask

3453

#define DMA_PRIMODE_bp 0 // Channel Priority Mode group position

3454

3455

#define DMA_PRIMODE0_bm (1<<0) // Channel Priority Mode bit 0 mask

3456

#define DMA_PRIMODE0_bp 0 // Channel Priority Mode bit 0 position

3457

#define DMA_PRIMODE1_bm (1<<1) // Channel Priority Mode bit 1 mask

3458

#define DMA_PRIMODE1_bp 1 // Channel Priority Mode bit 1 position

3459

3460

/* DMA.INTFLAGS bit masks and bit positions */

3461

3462

3463

#define DMA_CH3ERRIF_bm 0x80 // Channel 3 Block Transfer Error Interrupt Flag bit mask

3464

#define DMA_CH3ERRIF_bp 7 // Channel 3 Block Transfer Error Interrupt Flag bit position

3465

#define DMA_CH2ERRIF_bm 0x40 // Channel 2 Block Transfer Error Interrupt Flag bit mask

3466

#define DMA_CH2ERRIF_bp 6 // Channel 2 Block Transfer Error Interrupt Flag bit position

3467

#define DMA_CH1ERRIF_bm 0x20 // Channel 1 Block Transfer Error Interrupt Flag bit mask

3468

#define DMA_CH1ERRIF_bp 5 // Channel 1 Block Transfer Error Interrupt Flag bit position

3469

#define DMA_CH0ERRIF_bm 0x10 // Channel 0 Block Transfer Error Interrupt Flag bit mask

3470

#define DMA_CH0ERRIF_bp 4 // Channel 0 Block Transfer Error Interrupt Flag bit position

3471

#define DMA_CH3TRNIF_bm 0x08 // Channel 3 Transaction Complete Interrupt Flag bit mask

3472

#define DMA_CH3TRNIF_bp 3 // Channel 3 Transaction Complete Interrupt Flag bit position

3473

#define DMA_CH2TRNIF_bm 0x04 // Channel 2 Transaction Complete Interrupt Flag bit mask

3474

#define DMA_CH2TRNIF_bp 2 // Channel 2 Transaction Complete Interrupt Flag bit position

3475

#define DMA_CH1TRNIF_bm 0x02 // Channel 1 Transaction Complete Interrupt Flag bit mask

3476

#define DMA_CH1TRNIF_bp 1 // Channel 1 Transaction Complete Interrupt Flag bit position

3477

#define DMA_CH0TRNIF_bm 0x01 // Channel 0 Transaction Complete Interrupt Flag bit mask

3478

#define DMA_CH0TRNIF_bp 0 // Channel 0 Transaction Complete Interrupt Flag bit position

3479

3480

/* DMA.STATUS bit masks and bit positions */

3481

3482

3483

#define DMA_CH3BUSY_bm 0x80 // Channel 3 Block Transfer Busy bit mask

3484

#define DMA_CH3BUSY_bp 7 // Channel 3 Block Transfer Busy bit position

3485

#define DMA_CH2BUSY_bm 0x40 // Channel 2 Block Transfer Busy bit mask

3486

#define DMA_CH2BUSY_bp 6 // Channel 2 Block Transfer Busy bit position

3487

#define DMA_CH1BUSY_bm 0x20 // Channel 1 Block Transfer Busy bit mask

3488

#define DMA_CH1BUSY_bp 5 // Channel 1 Block Transfer Busy bit position

3489

#define DMA_CH0BUSY_bm 0x10 // Channel 0 Block Transfer Busy bit mask

3490

#define DMA_CH0BUSY_bp 4 // Channel 0 Block Transfer Busy bit position

3491

#define DMA_CH3PEND_bm 0x08 // Channel 3 Block Transfer Pending bit mask

3492

#define DMA_CH3PEND_bp 3 // Channel 3 Block Transfer Pending bit position

3493

#define DMA_CH2PEND_bm 0x04 // Channel 2 Block Transfer Pending bit mask

3494

#define DMA_CH2PEND_bp 2 // Channel 2 Block Transfer Pending bit position

3495

#define DMA_CH1PEND_bm 0x02 // Channel 1 Block Transfer Pending bit mask

3496

#define DMA_CH1PEND_bp 1 // Channel 1 Block Transfer Pending bit position

3497

#define DMA_CH0PEND_bm 0x01 // Channel 0 Block Transfer Pending bit mask

3498

#define DMA_CH0PEND_bp 0 // Channel 0 Block Transfer Pending bit position

3499

3500

#if !defined (__ASSEMBLER__)

3501

/* */

3502

typedef enum DMA_CH_BURSTLEN_enum

3503

{

3504

DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */

3505

DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */

3506

DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */

3507

DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */

3508

} DMA_CH_BURSTLEN_t;

3509

#endif /* !defined (__ASSEMBLER__) */

3510

3511

#if !defined (__ASSEMBLER__)

3512

/* */

3513

typedef enum DMA_CH_SRCRELOAD_enum

3514

{

3515

DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */

3516

DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */

3517

DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */

3518

DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */

3519

} DMA_CH_SRCRELOAD_t;

3520

#endif /* !defined (__ASSEMBLER__) */

3521

3522

#if !defined (__ASSEMBLER__)

3523

/* */

3524

typedef enum DMA_CH_SRCDIR_enum

3525

{

3526

DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */

3527

DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */

3528

DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */

3529

} DMA_CH_SRCDIR_t;

3530

#endif /* !defined (__ASSEMBLER__) */

3531

3532

#if !defined (__ASSEMBLER__)

3533

/* */

3534

typedef enum DMA_CH_DESTRELOAD_enum

3535

{

3536

DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */

3537

DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */

3538

DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */

3539

DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */

3540

} DMA_CH_DESTRELOAD_t;

3541

#endif /* !defined (__ASSEMBLER__) */

3542

3543

#if !defined (__ASSEMBLER__)

3544

/* */

3545

typedef enum DMA_CH_DESTDIR_enum

3546

{

3547

DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */

3548

DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */

3549

DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */

3550

} DMA_CH_DESTDIR_t;

3551

#endif /* !defined (__ASSEMBLER__) */

3552

3553

#if !defined (__ASSEMBLER__)

3554

/* */

3555

typedef enum DMA_CH_TRIGSRC_enum

3556

{

3557

DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */

3558

DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */

3559

DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */

3560

DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */

3561

DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */

3562

DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */

3563

DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */

3564

DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */

3565

DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */

3566

DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */

3567

DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */

3568

DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */

3569

DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */

3570

DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */

3571

DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */

3572

DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 4 */

3573

DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */

3574

DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */

3575

DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */

3576

DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */

3577

DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */

3578

DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */

3579

DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */

3580

DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */

3581

DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */

3582

DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */

3583

DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */

3584

DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */

3585

DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */

3586

DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */

3587

DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */

3588

DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */

3589

DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */

3590

DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */

3591

DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */

3592

DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */

3593

DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */

3594

DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */

3595

DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */

3596

DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */

3597

DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */

3598

DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */

3599

DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */

3600

DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */

3601

DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */

3602

DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */

3603

DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */

3604

DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */

3605

DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */

3606

DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */

3607

DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */

3608

DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */

3609

DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */

3610

DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */

3611

DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */

3612

DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */

3613

DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */

3614

DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */

3615

DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */

3616

DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */

3617

DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */

3618

DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */

3619

DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */

3620

DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */

3621

DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */

3622

DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */

3623

DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */

3624

DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */

3625

DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */

3626

DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */

3627

DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */

3628

DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */

3629

DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */

3630

DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */

3631

DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */

3632

DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */

3633

DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */

3634

DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */

3635

} DMA_CH_TRIGSRC_t;

3636

#endif /* !defined (__ASSEMBLER__) */

3637

3638

#if !defined (__ASSEMBLER__)

3639

/* */

3640

typedef enum DMA_DBUFMODE_enum

3641

{

3642

DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */

3643

DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */

3644

DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */

3645

DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */

3646

} DMA_DBUFMODE_t;

3647

#endif /* !defined (__ASSEMBLER__) */

3648

3649

#if !defined (__ASSEMBLER__)

3650

/* */

3651

typedef enum DMA_PRIMODE_enum

3652

{

3653

DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */

3654

DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */

3655

DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */

3656

DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */

3657

} DMA_PRIMODE_t;

3658

#endif /* !defined (__ASSEMBLER__) */

3659

3660

#if !defined (__ASSEMBLER__)

3661

/* */

3662

typedef enum DMA_CH_INTLVL_enum

3663

{

3664

DMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */

3665

DMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */

3666

DMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */

3667

DMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */

3668

} DMA_CH_INTLVL_t;

3669

#endif /* !defined (__ASSEMBLER__) */

3670

3671

3672

/*

3673

--------------------------------------------------------------------------

3674

EVSYS - Event System

3675

--------------------------------------------------------------------------

3676

*/

3677

3678

/* EVSYS.CH0MUX bit masks and bit positions */

3679

3680

3681

#define EVSYS_CHMUX_gm 0xFF // Event Channel 0 Multiplexer group mask

3682

#define EVSYS_CHMUX_bp 0 // Event Channel 0 Multiplexer group position

3683

3684

#define EVSYS_CHMUX0_bm (1<<0) // Event Channel 0 Multiplexer bit 0 mask

3685

#define EVSYS_CHMUX0_bp 0 // Event Channel 0 Multiplexer bit 0 position

3686

#define EVSYS_CHMUX1_bm (1<<1) // Event Channel 0 Multiplexer bit 1 mask

3687

#define EVSYS_CHMUX1_bp 1 // Event Channel 0 Multiplexer bit 1 position

3688

#define EVSYS_CHMUX2_bm (1<<2) // Event Channel 0 Multiplexer bit 2 mask

3689

#define EVSYS_CHMUX2_bp 2 // Event Channel 0 Multiplexer bit 2 position

3690

#define EVSYS_CHMUX3_bm (1<<3) // Event Channel 0 Multiplexer bit 3 mask

3691

#define EVSYS_CHMUX3_bp 3 // Event Channel 0 Multiplexer bit 3 position

3692

#define EVSYS_CHMUX4_bm (1<<4) // Event Channel 0 Multiplexer bit 4 mask

3693

#define EVSYS_CHMUX4_bp 4 // Event Channel 0 Multiplexer bit 4 position

3694

#define EVSYS_CHMUX5_bm (1<<5) // Event Channel 0 Multiplexer bit 5 mask

3695

#define EVSYS_CHMUX5_bp 5 // Event Channel 0 Multiplexer bit 5 position

3696

#define EVSYS_CHMUX6_bm (1<<6) // Event Channel 0 Multiplexer bit 6 mask

3697

#define EVSYS_CHMUX6_bp 6 // Event Channel 0 Multiplexer bit 6 position

3698

#define EVSYS_CHMUX7_bm (1<<7) // Event Channel 0 Multiplexer bit 7 mask

3699

#define EVSYS_CHMUX7_bp 7 // Event Channel 0 Multiplexer bit 7 position

3700

3701

/* EVSYS.CH1MUX bit masks and bit positions */

3702

3703

3704

/* Masks for CHMUX aready defined */

3705

3706

3707

/* EVSYS.CH2MUX bit masks and bit positions */

3708

3709

3710

/* Masks for CHMUX aready defined */

3711

3712

3713

/* EVSYS.CH3MUX bit masks and bit positions */

3714

3715

3716

/* Masks for CHMUX aready defined */

3717

3718

3719

/* EVSYS.CH4MUX bit masks and bit positions */

3720

3721

3722

/* Masks for CHMUX aready defined */

3723

3724

3725

/* EVSYS.CH5MUX bit masks and bit positions */

3726

3727

3728

/* Masks for CHMUX aready defined */

3729

3730

3731

/* EVSYS.CH6MUX bit masks and bit positions */

3732

3733

3734

/* Masks for CHMUX aready defined */

3735

3736

3737

/* EVSYS.CH7MUX bit masks and bit positions */

3738

3739

3740

/* Masks for CHMUX aready defined */

3741

3742

3743

/* EVSYS.CH0CTRL bit masks and bit positions */

3744

3745

3746

#define EVSYS_QDIRM_gm 0x60 // Quadrature Decoder Index Recognition Mode group mask

3747

#define EVSYS_QDIRM_bp 5 // Quadrature Decoder Index Recognition Mode group position

3748

3749

#define EVSYS_QDIRM0_bm (1<<5) // Quadrature Decoder Index Recognition Mode bit 0 mask

3750

#define EVSYS_QDIRM0_bp 5 // Quadrature Decoder Index Recognition Mode bit 0 position

3751

#define EVSYS_QDIRM1_bm (1<<6) // Quadrature Decoder Index Recognition Mode bit 1 mask

3752

#define EVSYS_QDIRM1_bp 6 // Quadrature Decoder Index Recognition Mode bit 1 position

3753

#define EVSYS_QDIEN_bm 0x10 // Quadrature Decoder Index Enable bit mask

3754

#define EVSYS_QDIEN_bp 4 // Quadrature Decoder Index Enable bit position

3755

#define EVSYS_QDEN_bm 0x08 // Quadrature Decoder Enable bit mask

3756

#define EVSYS_QDEN_bp 3 // Quadrature Decoder Enable bit position

3757

#define EVSYS_DIGFILT_gm 0x07 // Digital Filter group mask

3758

#define EVSYS_DIGFILT_bp 0 // Digital Filter group position

3759

3760

#define EVSYS_DIGFILT0_bm (1<<0) // Digital Filter bit 0 mask

3761

#define EVSYS_DIGFILT0_bp 0 // Digital Filter bit 0 position

3762

#define EVSYS_DIGFILT1_bm (1<<1) // Digital Filter bit 1 mask

3763

#define EVSYS_DIGFILT1_bp 1 // Digital Filter bit 1 position

3764

#define EVSYS_DIGFILT2_bm (1<<2) // Digital Filter bit 2 mask

3765

#define EVSYS_DIGFILT2_bp 2 // Digital Filter bit 2 position

3766

3767

/* EVSYS.CH1CTRL bit masks and bit positions */

3768

3769

3770

/* Masks for DIGFILT aready defined */

3771

3772

3773

/* EVSYS.CH2CTRL bit masks and bit positions */

3774

3775

3776

/* Masks for QDIRM aready defined */

3777

3778

/* Masks for QDIEN aready defined */

3779

3780

/* Masks for QDEN aready defined */

3781

3782

/* Masks for DIGFILT aready defined */

3783

3784

3785

/* EVSYS.CH3CTRL bit masks and bit positions */

3786

3787

3788

/* Masks for DIGFILT aready defined */

3789

3790

3791

/* EVSYS.CH4CTRL bit masks and bit positions */

3792

3793

3794

/* Masks for QDIRM aready defined */

3795

3796

/* Masks for QDIEN aready defined */

3797

3798

/* Masks for QDEN aready defined */

3799

3800

/* Masks for DIGFILT aready defined */

3801

3802

3803

/* EVSYS.CH5CTRL bit masks and bit positions */

3804

3805

3806

/* Masks for DIGFILT aready defined */

3807

3808

3809

/* EVSYS.CH6CTRL bit masks and bit positions */

3810

3811

3812

/* Masks for DIGFILT aready defined */

3813

3814

3815

/* EVSYS.CH7CTRL bit masks and bit positions */

3816

3817

3818

/* Masks for DIGFILT aready defined */

3819

3820

3821

#if !defined (__ASSEMBLER__)

3822

/* */

3823

typedef enum EVSYS_QDIRM_enum

3824

{

3825

EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */

3826

EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */

3827

EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */

3828

EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */

3829

} EVSYS_QDIRM_t;

3830

#endif /* !defined (__ASSEMBLER__) */

3831

3832

#if !defined (__ASSEMBLER__)

3833

/* */

3834

typedef enum EVSYS_DIGFILT_enum

3835

{

3836

EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */

3837

EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */

3838

EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */

3839

EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */

3840

EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */

3841

EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */

3842

EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */

3843

EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */

3844

} EVSYS_DIGFILT_t;

3845

#endif /* !defined (__ASSEMBLER__) */

3846

3847

#if !defined (__ASSEMBLER__)

3848

/* */

3849

typedef enum EVSYS_CHMUX_enum

3850

{

3851

EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */

3852

EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */

3853

EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */

3854

EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */

3855

EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */

3856

EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */

3857

EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */

3858

EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */

3859

EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */

3860

EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */

3861

EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */

3862

EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */

3863

EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */

3864

EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */

3865

EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */

3866

EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */

3867

EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */

3868

EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */

3869

EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */

3870

EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */

3871

EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */

3872

EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */

3873

EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */

3874

EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */

3875

EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */

3876

EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */

3877

EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */

3878

EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */

3879

EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */

3880

EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */

3881

EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */

3882

EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */

3883

EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */

3884

EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */

3885

EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */

3886

EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */

3887

EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */

3888

EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */

3889

EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */

3890

EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */

3891

EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */

3892

EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */

3893

EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */

3894

EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */

3895

EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */

3896

EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */

3897

EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */

3898

EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */

3899

EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */

3900

EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */

3901

EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */

3902

EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */

3903

EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */

3904

EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */

3905

EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */

3906

EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */

3907

EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */

3908

EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */

3909

EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */

3910

EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */

3911

EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */

3912

EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */

3913

EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */

3914

EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */

3915

EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */

3916

EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */

3917

EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */

3918

EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */

3919

EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */

3920

EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */

3921

EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */

3922

EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */

3923

EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */

3924

EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */

3925

EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */

3926

EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */

3927

EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */

3928

EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */

3929

EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */

3930

EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */

3931

EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */

3932

EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */

3933

EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */

3934

EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */

3935

EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */

3936

EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */

3937

EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */

3938

EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */

3939

EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */

3940

EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */

3941

EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */

3942

EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */

3943

EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */

3944

EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */

3945

EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */

3946

EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */

3947

EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */

3948

EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */

3949

EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */

3950

EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */

3951

EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */

3952

EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */

3953

EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */

3954

EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */

3955

EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */

3956

EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */

3957

EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */

3958

EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */

3959

EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */

3960

EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */

3961

EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */

3962

EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */

3963

EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */

3964

EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */

3965

EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */

3966

EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */

3967

EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */

3968

EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */

3969

EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */

3970

EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */

3971

EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */

3972

} EVSYS_CHMUX_t;

3973

#endif /* !defined (__ASSEMBLER__) */

3974

3975

3976

/*

3977

--------------------------------------------------------------------------

3978

NVM - Non Volatile Memory

3979

--------------------------------------------------------------------------

3980

*/

3981

3982

/* NVM.CMD bit masks and bit positions */

3983

3984

3985

#define NVM_CMD_gm 0xFF // Command group mask

3986

#define NVM_CMD_bp 0 // Command group position

3987

3988

#define NVM_CMD0_bm (1<<0) // Command bit 0 mask

3989

#define NVM_CMD0_bp 0 // Command bit 0 position

3990

#define NVM_CMD1_bm (1<<1) // Command bit 1 mask

3991

#define NVM_CMD1_bp 1 // Command bit 1 position

3992

#define NVM_CMD2_bm (1<<2) // Command bit 2 mask

3993

#define NVM_CMD2_bp 2 // Command bit 2 position

3994

#define NVM_CMD3_bm (1<<3) // Command bit 3 mask

3995

#define NVM_CMD3_bp 3 // Command bit 3 position

3996

#define NVM_CMD4_bm (1<<4) // Command bit 4 mask

3997

#define NVM_CMD4_bp 4 // Command bit 4 position

3998

#define NVM_CMD5_bm (1<<5) // Command bit 5 mask

3999

#define NVM_CMD5_bp 5 // Command bit 5 position

4000

#define NVM_CMD6_bm (1<<6) // Command bit 6 mask

4001

#define NVM_CMD6_bp 6 // Command bit 6 position

4002

#define NVM_CMD7_bm (1<<7) // Command bit 7 mask

4003

#define NVM_CMD7_bp 7 // Command bit 7 position

4004

4005

/* NVM.CTRLA bit masks and bit positions */

4006

4007

4008

#define NVM_CMDEX_bm 0x01 // Command Execute bit mask

4009

#define NVM_CMDEX_bp 0 // Command Execute bit position

4010

4011

/* NVM.CTRLB bit masks and bit positions */

4012

4013

4014

#define NVM_EEMAPEN_bm 0x08 // EEPROM Mapping Enable bit mask

4015

#define NVM_EEMAPEN_bp 3 // EEPROM Mapping Enable bit position

4016

#define NVM_FPRM_bm 0x04 // Flash Power Reduction Enable bit mask

4017

#define NVM_FPRM_bp 2 // Flash Power Reduction Enable bit position

4018

#define NVM_EPRM_bm 0x02 // EEPROM Power Reduction Enable bit mask

4019

#define NVM_EPRM_bp 1 // EEPROM Power Reduction Enable bit position

4020

#define NVM_SPMLOCK_bm 0x01 // SPM Lock bit mask

4021

#define NVM_SPMLOCK_bp 0 // SPM Lock bit position

4022

4023

/* NVM.INTCTRL bit masks and bit positions */

4024

4025

4026

#define NVM_SPMLVL_gm 0x0C // SPM Interrupt Level group mask

4027

#define NVM_SPMLVL_bp 2 // SPM Interrupt Level group position

4028

4029

#define NVM_SPMLVL0_bm (1<<2) // SPM Interrupt Level bit 0 mask

4030

#define NVM_SPMLVL0_bp 2 // SPM Interrupt Level bit 0 position

4031

#define NVM_SPMLVL1_bm (1<<3) // SPM Interrupt Level bit 1 mask

4032

#define NVM_SPMLVL1_bp 3 // SPM Interrupt Level bit 1 position

4033

#define NVM_EELVL_gm 0x03 // EEPROM Interrupt Level group mask

4034

#define NVM_EELVL_bp 0 // EEPROM Interrupt Level group position

4035

4036

#define NVM_EELVL0_bm (1<<0) // EEPROM Interrupt Level bit 0 mask

4037

#define NVM_EELVL0_bp 0 // EEPROM Interrupt Level bit 0 position

4038

#define NVM_EELVL1_bm (1<<1) // EEPROM Interrupt Level bit 1 mask

4039

#define NVM_EELVL1_bp 1 // EEPROM Interrupt Level bit 1 position

4040

4041

/* NVM.STATUS bit masks and bit positions */

4042

4043

4044

#define NVM_NVMBUSY_bm 0x80 // Non-volatile Memory Busy bit mask

4045

#define NVM_NVMBUSY_bp 7 // Non-volatile Memory Busy bit position

4046

#define NVM_FBUSY_bm 0x40 // Flash Memory Busy bit mask

4047

#define NVM_FBUSY_bp 6 // Flash Memory Busy bit position

4048

#define NVM_EELOAD_bm 0x02 // EEPROM Page Buffer Active Loading bit mask

4049

#define NVM_EELOAD_bp 1 // EEPROM Page Buffer Active Loading bit position

4050

#define NVM_FLOAD_bm 0x01 // Flash Page Buffer Active Loading bit mask

4051

#define NVM_FLOAD_bp 0 // Flash Page Buffer Active Loading bit position

4052

4053

/* NVM.LOCKBITS bit masks and bit positions */

4054

4055

4056

#define NVM_BLBB_gm 0xC0 // Boot Lock Bits - Boot Section group mask

4057

#define NVM_BLBB_bp 6 // Boot Lock Bits - Boot Section group position

4058

4059

#define NVM_BLBB0_bm (1<<6) // Boot Lock Bits - Boot Section bit 0 mask

4060

#define NVM_BLBB0_bp 6 // Boot Lock Bits - Boot Section bit 0 position

4061

#define NVM_BLBB1_bm (1<<7) // Boot Lock Bits - Boot Section bit 1 mask

4062

#define NVM_BLBB1_bp 7 // Boot Lock Bits - Boot Section bit 1 position

4063

#define NVM_BLBA_gm 0x30 // Boot Lock Bits - Application Section group mask

4064

#define NVM_BLBA_bp 4 // Boot Lock Bits - Application Section group position

4065

4066

#define NVM_BLBA0_bm (1<<4) // Boot Lock Bits - Application Section bit 0 mask

4067

#define NVM_BLBA0_bp 4 // Boot Lock Bits - Application Section bit 0 position

4068

#define NVM_BLBA1_bm (1<<5) // Boot Lock Bits - Application Section bit 1 mask

4069

#define NVM_BLBA1_bp 5 // Boot Lock Bits - Application Section bit 1 position

4070

#define NVM_BLBAT_gm 0x0C // Boot Lock Bits - Application Table group mask

4071

#define NVM_BLBAT_bp 2 // Boot Lock Bits - Application Table group position

4072

4073

#define NVM_BLBAT0_bm (1<<2) // Boot Lock Bits - Application Table bit 0 mask

4074

#define NVM_BLBAT0_bp 2 // Boot Lock Bits - Application Table bit 0 position

4075

#define NVM_BLBAT1_bm (1<<3) // Boot Lock Bits - Application Table bit 1 mask

4076

#define NVM_BLBAT1_bp 3 // Boot Lock Bits - Application Table bit 1 position

4077

#define NVM_LB_gm 0x03 // Lock Bits group mask

4078

#define NVM_LB_bp 0 // Lock Bits group position

4079

4080

#define NVM_LB0_bm (1<<0) // Lock Bits bit 0 mask

4081

#define NVM_LB0_bp 0 // Lock Bits bit 0 position

4082

#define NVM_LB1_bm (1<<1) // Lock Bits bit 1 mask

4083

#define NVM_LB1_bp 1 // Lock Bits bit 1 position

4084

4085

/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */

4086

4087

4088

#define NVM_LOCKBITS_BLBB_gm 0xC0 // Boot Lock Bits - Boot Section group mask

4089

#define NVM_LOCKBITS_BLBB_bp 6 // Boot Lock Bits - Boot Section group position

4090

4091

#define NVM_LOCKBITS_BLBB0_bm (1<<6) // Boot Lock Bits - Boot Section bit 0 mask

4092

#define NVM_LOCKBITS_BLBB0_bp 6 // Boot Lock Bits - Boot Section bit 0 position

4093

#define NVM_LOCKBITS_BLBB1_bm (1<<7) // Boot Lock Bits - Boot Section bit 1 mask

4094

#define NVM_LOCKBITS_BLBB1_bp 7 // Boot Lock Bits - Boot Section bit 1 position

4095

#define NVM_LOCKBITS_BLBA_gm 0x30 // Boot Lock Bits - Application Section group mask

4096

#define NVM_LOCKBITS_BLBA_bp 4 // Boot Lock Bits - Application Section group position

4097

4098

#define NVM_LOCKBITS_BLBA0_bm (1<<4) // Boot Lock Bits - Application Section bit 0 mask

4099

#define NVM_LOCKBITS_BLBA0_bp 4 // Boot Lock Bits - Application Section bit 0 position

4100

#define NVM_LOCKBITS_BLBA1_bm (1<<5) // Boot Lock Bits - Application Section bit 1 mask

4101

#define NVM_LOCKBITS_BLBA1_bp 5 // Boot Lock Bits - Application Section bit 1 position

4102

#define NVM_LOCKBITS_BLBAT_gm 0x0C // Boot Lock Bits - Application Table group mask

4103

#define NVM_LOCKBITS_BLBAT_bp 2 // Boot Lock Bits - Application Table group position

4104

4105

#define NVM_LOCKBITS_BLBAT0_bm (1<<2) // Boot Lock Bits - Application Table bit 0 mask

4106

#define NVM_LOCKBITS_BLBAT0_bp 2 // Boot Lock Bits - Application Table bit 0 position

4107

#define NVM_LOCKBITS_BLBAT1_bm (1<<3) // Boot Lock Bits - Application Table bit 1 mask

4108

#define NVM_LOCKBITS_BLBAT1_bp 3 // Boot Lock Bits - Application Table bit 1 position

4109

#define NVM_LOCKBITS_LB_gm 0x03 // Lock Bits group mask

4110

#define NVM_LOCKBITS_LB_bp 0 // Lock Bits group position

4111

4112

#define NVM_LOCKBITS_LB0_bm (1<<0) // Lock Bits bit 0 mask

4113

#define NVM_LOCKBITS_LB0_bp 0 // Lock Bits bit 0 position

4114

#define NVM_LOCKBITS_LB1_bm (1<<1) // Lock Bits bit 1 mask

4115

#define NVM_LOCKBITS_LB1_bp 1 // Lock Bits bit 1 position

4116

4117

/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */

4118

4119

4120

#define NVM_FUSES_JTAGUSERID_gm 0xFF // JTAG User ID group mask

4121

#define NVM_FUSES_JTAGUSERID_bp 0 // JTAG User ID group position

4122

4123

#define NVM_FUSES_JTAGUSERID0_bm (1<<0) // JTAG User ID bit 0 mask

4124

#define NVM_FUSES_JTAGUSERID0_bp 0 // JTAG User ID bit 0 position

4125

#define NVM_FUSES_JTAGUSERID1_bm (1<<1) // JTAG User ID bit 1 mask

4126

#define NVM_FUSES_JTAGUSERID1_bp 1 // JTAG User ID bit 1 position

4127

#define NVM_FUSES_JTAGUSERID2_bm (1<<2) // JTAG User ID bit 2 mask

4128

#define NVM_FUSES_JTAGUSERID2_bp 2 // JTAG User ID bit 2 position

4129

#define NVM_FUSES_JTAGUSERID3_bm (1<<3) // JTAG User ID bit 3 mask

4130

#define NVM_FUSES_JTAGUSERID3_bp 3 // JTAG User ID bit 3 position

4131

#define NVM_FUSES_JTAGUSERID4_bm (1<<4) // JTAG User ID bit 4 mask

4132

#define NVM_FUSES_JTAGUSERID4_bp 4 // JTAG User ID bit 4 position

4133

#define NVM_FUSES_JTAGUSERID5_bm (1<<5) // JTAG User ID bit 5 mask

4134

#define NVM_FUSES_JTAGUSERID5_bp 5 // JTAG User ID bit 5 position

4135

#define NVM_FUSES_JTAGUSERID6_bm (1<<6) // JTAG User ID bit 6 mask

4136

#define NVM_FUSES_JTAGUSERID6_bp 6 // JTAG User ID bit 6 position

4137

#define NVM_FUSES_JTAGUSERID7_bm (1<<7) // JTAG User ID bit 7 mask

4138

#define NVM_FUSES_JTAGUSERID7_bp 7 // JTAG User ID bit 7 position

4139

4140

/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */

4141

4142

4143

#define NVM_FUSES_WDWP_gm 0xF0 // Watchdog Window Timeout Period group mask

4144

#define NVM_FUSES_WDWP_bp 4 // Watchdog Window Timeout Period group position

4145

4146

#define NVM_FUSES_WDWP0_bm (1<<4) // Watchdog Window Timeout Period bit 0 mask

4147

#define NVM_FUSES_WDWP0_bp 4 // Watchdog Window Timeout Period bit 0 position

4148

#define NVM_FUSES_WDWP1_bm (1<<5) // Watchdog Window Timeout Period bit 1 mask

4149

#define NVM_FUSES_WDWP1_bp 5 // Watchdog Window Timeout Period bit 1 position

4150

#define NVM_FUSES_WDWP2_bm (1<<6) // Watchdog Window Timeout Period bit 2 mask

4151

#define NVM_FUSES_WDWP2_bp 6 // Watchdog Window Timeout Period bit 2 position

4152

#define NVM_FUSES_WDWP3_bm (1<<7) // Watchdog Window Timeout Period bit 3 mask

4153

#define NVM_FUSES_WDWP3_bp 7 // Watchdog Window Timeout Period bit 3 position

4154

#define NVM_FUSES_WDP_gm 0x0F // Watchdog Timeout Period group mask

4155

#define NVM_FUSES_WDP_bp 0 // Watchdog Timeout Period group position

4156

4157

#define NVM_FUSES_WDP0_bm (1<<0) // Watchdog Timeout Period bit 0 mask

4158

#define NVM_FUSES_WDP0_bp 0 // Watchdog Timeout Period bit 0 position

4159

#define NVM_FUSES_WDP1_bm (1<<1) // Watchdog Timeout Period bit 1 mask

4160

#define NVM_FUSES_WDP1_bp 1 // Watchdog Timeout Period bit 1 position

4161

#define NVM_FUSES_WDP2_bm (1<<2) // Watchdog Timeout Period bit 2 mask

4162

#define NVM_FUSES_WDP2_bp 2 // Watchdog Timeout Period bit 2 position

4163

#define NVM_FUSES_WDP3_bm (1<<3) // Watchdog Timeout Period bit 3 mask

4164

#define NVM_FUSES_WDP3_bp 3 // Watchdog Timeout Period bit 3 position

4165

4166

/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */

4167

4168

4169

#define NVM_FUSES_DVSDON_bm 0x80 // Spike Detector Enable bit mask

4170

#define NVM_FUSES_DVSDON_bp 7 // Spike Detector Enable bit position

4171

#define NVM_FUSES_BOOTRST_bm 0x40 // Boot Loader Section Reset Vector bit mask

4172

#define NVM_FUSES_BOOTRST_bp 6 // Boot Loader Section Reset Vector bit position

4173

#define NVM_FUSES_BODACT_gm 0x0C // BOD Operation in Active Mode group mask

4174

#define NVM_FUSES_BODACT_bp 2 // BOD Operation in Active Mode group position

4175

4176

#define NVM_FUSES_BODACT0_bm (1<<2) // BOD Operation in Active Mode bit 0 mask

4177

#define NVM_FUSES_BODACT0_bp 2 // BOD Operation in Active Mode bit 0 position

4178

#define NVM_FUSES_BODACT1_bm (1<<3) // BOD Operation in Active Mode bit 1 mask

4179

#define NVM_FUSES_BODACT1_bp 3 // BOD Operation in Active Mode bit 1 position

4180

#define NVM_FUSES_BODPD_gm 0x03 // BOD Operation in Power-Down Mode group mask

4181

#define NVM_FUSES_BODPD_bp 0 // BOD Operation in Power-Down Mode group position

4182

4183

#define NVM_FUSES_BODPD0_bm (1<<0) // BOD Operation in Power-Down Mode bit 0 mask

4184

#define NVM_FUSES_BODPD0_bp 0 // BOD Operation in Power-Down Mode bit 0 position

4185

#define NVM_FUSES_BODPD1_bm (1<<1) // BOD Operation in Power-Down Mode bit 1 mask

4186

#define NVM_FUSES_BODPD1_bp 1 // BOD Operation in Power-Down Mode bit 1 position

4187

4188

/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */

4189

4190

4191

#define NVM_FUSES_SUT_gm 0x0C // Start-up Time group mask

4192

#define NVM_FUSES_SUT_bp 2 // Start-up Time group position

4193

4194

#define NVM_FUSES_SUT0_bm (1<<2) // Start-up Time bit 0 mask

4195

#define NVM_FUSES_SUT0_bp 2 // Start-up Time bit 0 position

4196

#define NVM_FUSES_SUT1_bm (1<<3) // Start-up Time bit 1 mask

4197

#define NVM_FUSES_SUT1_bp 3 // Start-up Time bit 1 position

4198

#define NVM_FUSES_WDLOCK_bm 0x02 // Watchdog Timer Lock bit mask

4199

#define NVM_FUSES_WDLOCK_bp 1 // Watchdog Timer Lock bit position

4200

#define NVM_FUSES_JTAGEN_bm 0x01 // JTAG Interface Enable bit mask

4201

#define NVM_FUSES_JTAGEN_bp 0 // JTAG Interface Enable bit position

4202

4203

/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */

4204

4205

4206

#define NVM_FUSES_EESAVE_bm 0x08 // Preserve EEPROM Through Chip Erase bit mask

4207

#define NVM_FUSES_EESAVE_bp 3 // Preserve EEPROM Through Chip Erase bit position

4208

#define NVM_FUSES_BODLVL_gm 0x07 // Brown Out Detection Voltage Level group mask

4209

#define NVM_FUSES_BODLVL_bp 0 // Brown Out Detection Voltage Level group position

4210

4211

#define NVM_FUSES_BODLVL0_bm (1<<0) // Brown Out Detection Voltage Level bit 0 mask

4212

#define NVM_FUSES_BODLVL0_bp 0 // Brown Out Detection Voltage Level bit 0 position

4213

#define NVM_FUSES_BODLVL1_bm (1<<1) // Brown Out Detection Voltage Level bit 1 mask

4214

#define NVM_FUSES_BODLVL1_bp 1 // Brown Out Detection Voltage Level bit 1 position

4215

#define NVM_FUSES_BODLVL2_bm (1<<2) // Brown Out Detection Voltage Level bit 2 mask

4216

#define NVM_FUSES_BODLVL2_bp 2 // Brown Out Detection Voltage Level bit 2 position

4217

4218

#if !defined (__ASSEMBLER__)

4219

/* */

4220

typedef enum NVM_CMD_enum

4221

{

4222

NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */

4223

NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */

4224

NVM_CMD_READ_USER_SIG_ROW_gc = (0x03<<0), /* Read user signature row */

4225

NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */

4226

NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */

4227

NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */

4228

NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */

4229

NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */

4230

NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */

4231

NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */

4232

NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */

4233

NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */

4234

NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */

4235

NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */

4236

NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */

4237

NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */

4238

NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */

4239

NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */

4240

NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */

4241

NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */

4242

NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */

4243

NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */

4244

NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */

4245

NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */

4246

NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */

4247

} NVM_CMD_t;

4248

#endif /* !defined (__ASSEMBLER__) */

4249

4250

#if !defined (__ASSEMBLER__)

4251

/* */

4252

typedef enum NVM_SPMLVL_enum

4253

{

4254

NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */

4255

NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */

4256

NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */

4257

NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */

4258

} NVM_SPMLVL_t;

4259

#endif /* !defined (__ASSEMBLER__) */

4260

4261

#if !defined (__ASSEMBLER__)

4262

/* */

4263

typedef enum NVM_EELVL_enum

4264

{

4265

NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */

4266

NVM_EELVL_LO_gc = (0x01<<0), /* Low level */

4267

NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */

4268

NVM_EELVL_HI_gc = (0x03<<0), /* High level */

4269

} NVM_EELVL_t;

4270

#endif /* !defined (__ASSEMBLER__) */

4271

4272

#if !defined (__ASSEMBLER__)

4273

/* */

4274

typedef enum NVM_BLBB_enum

4275

{

4276

NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */

4277

NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */

4278

NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */

4279

NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */

4280

} NVM_BLBB_t;

4281

#endif /* !defined (__ASSEMBLER__) */

4282

4283

#if !defined (__ASSEMBLER__)

4284

/* */

4285

typedef enum NVM_BLBA_enum

4286

{

4287

NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */

4288

NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */

4289

NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */

4290

NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */

4291

} NVM_BLBA_t;

4292

#endif /* !defined (__ASSEMBLER__) */

4293

4294

#if !defined (__ASSEMBLER__)

4295

/* */

4296

typedef enum NVM_BLBAT_enum

4297

{

4298

NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */

4299

NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */

4300

NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */

4301

NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */

4302

} NVM_BLBAT_t;

4303

#endif /* !defined (__ASSEMBLER__) */

4304

4305

#if !defined (__ASSEMBLER__)

4306

/* */

4307

typedef enum NVM_LB_enum

4308

{

4309

NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */

4310

NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */

4311

NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */

4312

} NVM_LB_t;

4313

#endif /* !defined (__ASSEMBLER__) */

4314

4315

#if !defined (__ASSEMBLER__)

4316

/* Boot Loader Section Reset Vector */

4317

typedef enum BOOTRST_enum

4318

{

4319

BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */

4320

BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */

4321

} BOOTRST_t;

4322

#endif /* !defined (__ASSEMBLER__) */

4323

4324

#if !defined (__ASSEMBLER__)

4325

/* BOD operation */

4326

typedef enum BOD_enum

4327

{

4328

BOD_INSAMPLEDMODE_gc = (0x01<<2), /* BOD enabled in sampled mode */

4329

BOD_CONTINOUSLY_gc = (0x02<<2), /* BOD enabled continuously */

4330

BOD_DISABLED_gc = (0x03<<2), /* BOD Disabled */

4331

} BOD_t;

4332

#endif /* !defined (__ASSEMBLER__) */

4333

4334

#if !defined (__ASSEMBLER__)

4335

/* Watchdog (Window) Timeout Period */

4336

typedef enum WD_enum

4337

{

4338

WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */

4339

WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */

4340

WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */

4341

WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */

4342

WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */

4343

WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */

4344

WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */

4345

WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */

4346

WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */

4347

WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */

4348

WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */

4349

} WD_t;

4350

#endif /* !defined (__ASSEMBLER__) */

4351

4352

#if !defined (__ASSEMBLER__)

4353

/* Start-up Time */

4354

typedef enum SUT_enum

4355

{

4356

SUT_0MS_gc = (0x03<<2), /* 0 ms */

4357

SUT_4MS_gc = (0x01<<2), /* 4 ms */

4358

SUT_64MS_gc = (0x00<<2), /* 64 ms */

4359

} SUT_t;

4360

#endif /* !defined (__ASSEMBLER__) */

4361

4362

#if !defined (__ASSEMBLER__)

4363

/* Brown Out Detection Voltage Level */

4364

typedef enum BODLVL_enum

4365

{

4366

BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */

4367

BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */

4368

BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */

4369

BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */

4370

BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */

4371

BODLVL_2V7_gc = (0x02<<0), /* 2.7 V */

4372

BODLVL_2V9_gc = (0x01<<0), /* 2.9 V */

4373

BODLVL_3V2_gc = (0x00<<0), /* 3.2 V */

4374

} BODLVL_t;

4375

#endif /* !defined (__ASSEMBLER__) */

4376

4377

4378

/*

4379

--------------------------------------------------------------------------

4380

AC - Analog Comparator

4381

--------------------------------------------------------------------------

4382

*/

4383

4384

/* AC.AC0CTRL bit masks and bit positions */

4385

4386

4387

#define AC_INTMODE_gm 0xC0 // Interrupt Mode group mask

4388

#define AC_INTMODE_bp 6 // Interrupt Mode group position

4389

4390

#define AC_INTMODE0_bm (1<<6) // Interrupt Mode bit 0 mask

4391

#define AC_INTMODE0_bp 6 // Interrupt Mode bit 0 position

4392

#define AC_INTMODE1_bm (1<<7) // Interrupt Mode bit 1 mask

4393

#define AC_INTMODE1_bp 7 // Interrupt Mode bit 1 position

4394

#define AC_INTLVL_gm 0x30 // Interrupt Level group mask

4395

#define AC_INTLVL_bp 4 // Interrupt Level group position

4396

4397

#define AC_INTLVL0_bm (1<<4) // Interrupt Level bit 0 mask

4398

#define AC_INTLVL0_bp 4 // Interrupt Level bit 0 position

4399

#define AC_INTLVL1_bm (1<<5) // Interrupt Level bit 1 mask

4400

#define AC_INTLVL1_bp 5 // Interrupt Level bit 1 position

4401

#define AC_HSMODE_bm 0x08 // High-speed Mode bit mask

4402

#define AC_HSMODE_bp 3 // High-speed Mode bit position

4403

#define AC_HYSMODE_gm 0x06 // Hysteresis Mode group mask

4404

#define AC_HYSMODE_bp 1 // Hysteresis Mode group position

4405

4406

#define AC_HYSMODE0_bm (1<<1) // Hysteresis Mode bit 0 mask

4407

#define AC_HYSMODE0_bp 1 // Hysteresis Mode bit 0 position

4408

#define AC_HYSMODE1_bm (1<<2) // Hysteresis Mode bit 1 mask

4409

#define AC_HYSMODE1_bp 2 // Hysteresis Mode bit 1 position

4410

#define AC_ENABLE_bm 0x01 // Enable bit mask

4411

#define AC_ENABLE_bp 0 // Enable bit position

4412

4413

/* AC.AC1CTRL bit masks and bit positions */

4414

4415

4416

/* Masks for INTMODE aready defined */

4417

4418

/* Masks for INTLVL aready defined */

4419

4420

/* Masks for HSMODE aready defined */

4421

4422

/* Masks for HYSMODE aready defined */

4423

4424

/* Masks for ENABLE aready defined */

4425

4426

4427

/* AC.AC0MUXCTRL bit masks and bit positions */

4428

4429

4430

#define AC_MUXPOS_gm 0x38 // MUX Positive Input group mask

4431

#define AC_MUXPOS_bp 3 // MUX Positive Input group position

4432

4433

#define AC_MUXPOS0_bm (1<<3) // MUX Positive Input bit 0 mask

4434

#define AC_MUXPOS0_bp 3 // MUX Positive Input bit 0 position

4435

#define AC_MUXPOS1_bm (1<<4) // MUX Positive Input bit 1 mask

4436

#define AC_MUXPOS1_bp 4 // MUX Positive Input bit 1 position

4437

#define AC_MUXPOS2_bm (1<<5) // MUX Positive Input bit 2 mask

4438

#define AC_MUXPOS2_bp 5 // MUX Positive Input bit 2 position

4439

#define AC_MUXNEG_gm 0x07 // MUX Negative Input group mask

4440

#define AC_MUXNEG_bp 0 // MUX Negative Input group position

4441

4442

#define AC_MUXNEG0_bm (1<<0) // MUX Negative Input bit 0 mask

4443

#define AC_MUXNEG0_bp 0 // MUX Negative Input bit 0 position

4444

#define AC_MUXNEG1_bm (1<<1) // MUX Negative Input bit 1 mask

4445

#define AC_MUXNEG1_bp 1 // MUX Negative Input bit 1 position

4446

#define AC_MUXNEG2_bm (1<<2) // MUX Negative Input bit 2 mask

4447

#define AC_MUXNEG2_bp 2 // MUX Negative Input bit 2 position

4448

4449

/* AC.AC1MUXCTRL bit masks and bit positions */

4450

4451

4452

/* Masks for MUXPOS aready defined */

4453

4454

/* Masks for MUXNEG aready defined */

4455

4456

4457

/* AC.CTRLA bit masks and bit positions */

4458

4459

4460

#define AC_AC0OUT_bm 0x01 // Comparator 0 Output Enable bit mask

4461

#define AC_AC0OUT_bp 0 // Comparator 0 Output Enable bit position

4462

4463

/* AC.CTRLB bit masks and bit positions */

4464

4465

4466

#define AC_SCALEFAC_gm 0x3F // VCC Voltage Scaler Factor group mask

4467

#define AC_SCALEFAC_bp 0 // VCC Voltage Scaler Factor group position

4468

4469

#define AC_SCALEFAC0_bm (1<<0) // VCC Voltage Scaler Factor bit 0 mask

4470

#define AC_SCALEFAC0_bp 0 // VCC Voltage Scaler Factor bit 0 position

4471

#define AC_SCALEFAC1_bm (1<<1) // VCC Voltage Scaler Factor bit 1 mask

4472

#define AC_SCALEFAC1_bp 1 // VCC Voltage Scaler Factor bit 1 position

4473

#define AC_SCALEFAC2_bm (1<<2) // VCC Voltage Scaler Factor bit 2 mask

4474

#define AC_SCALEFAC2_bp 2 // VCC Voltage Scaler Factor bit 2 position

4475

#define AC_SCALEFAC3_bm (1<<3) // VCC Voltage Scaler Factor bit 3 mask

4476

#define AC_SCALEFAC3_bp 3 // VCC Voltage Scaler Factor bit 3 position

4477

#define AC_SCALEFAC4_bm (1<<4) // VCC Voltage Scaler Factor bit 4 mask

4478

#define AC_SCALEFAC4_bp 4 // VCC Voltage Scaler Factor bit 4 position

4479

#define AC_SCALEFAC5_bm (1<<5) // VCC Voltage Scaler Factor bit 5 mask

4480

#define AC_SCALEFAC5_bp 5 // VCC Voltage Scaler Factor bit 5 position

4481

4482

/* AC.WINCTRL bit masks and bit positions */

4483

4484

4485

#define AC_WEN_bm 0x10 // Window Mode Enable bit mask

4486

#define AC_WEN_bp 4 // Window Mode Enable bit position

4487

#define AC_WINTMODE_gm 0x0C // Window Interrupt Mode group mask

4488

#define AC_WINTMODE_bp 2 // Window Interrupt Mode group position

4489

4490

#define AC_WINTMODE0_bm (1<<2) // Window Interrupt Mode bit 0 mask

4491

#define AC_WINTMODE0_bp 2 // Window Interrupt Mode bit 0 position

4492

#define AC_WINTMODE1_bm (1<<3) // Window Interrupt Mode bit 1 mask

4493

#define AC_WINTMODE1_bp 3 // Window Interrupt Mode bit 1 position

4494

#define AC_WINTLVL_gm 0x03 // Window Interrupt Level group mask

4495

#define AC_WINTLVL_bp 0 // Window Interrupt Level group position

4496

4497

#define AC_WINTLVL0_bm (1<<0) // Window Interrupt Level bit 0 mask

4498

#define AC_WINTLVL0_bp 0 // Window Interrupt Level bit 0 position

4499

#define AC_WINTLVL1_bm (1<<1) // Window Interrupt Level bit 1 mask

4500

#define AC_WINTLVL1_bp 1 // Window Interrupt Level bit 1 position

4501

4502

/* AC.STATUS bit masks and bit positions */

4503

4504

4505

#define AC_WSTATE_gm 0xC0 // Window Mode State group mask

4506

#define AC_WSTATE_bp 6 // Window Mode State group position

4507

4508

#define AC_WSTATE0_bm (1<<6) // Window Mode State bit 0 mask

4509

#define AC_WSTATE0_bp 6 // Window Mode State bit 0 position

4510

#define AC_WSTATE1_bm (1<<7) // Window Mode State bit 1 mask

4511

#define AC_WSTATE1_bp 7 // Window Mode State bit 1 position

4512

#define AC_AC1STATE_bm 0x20 // Comparator 1 State bit mask

4513

#define AC_AC1STATE_bp 5 // Comparator 1 State bit position

4514

#define AC_AC0STATE_bm 0x10 // Comparator 0 State bit mask

4515

#define AC_AC0STATE_bp 4 // Comparator 0 State bit position

4516

#define AC_WIF_bm 0x04 // Window Mode Interrupt Flag bit mask

4517

#define AC_WIF_bp 2 // Window Mode Interrupt Flag bit position

4518

#define AC_AC1IF_bm 0x02 // Comparator 1 Interrupt Flag bit mask

4519

#define AC_AC1IF_bp 1 // Comparator 1 Interrupt Flag bit position

4520

#define AC_AC0IF_bm 0x01 // Comparator 0 Interrupt Flag bit mask

4521

#define AC_AC0IF_bp 0 // Comparator 0 Interrupt Flag bit position

4522

4523

#if !defined (__ASSEMBLER__)

4524

/* */

4525

typedef enum AC_INTMODE_enum

4526

{

4527

AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */

4528

AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */

4529

AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */

4530

} AC_INTMODE_t;

4531

#endif /* !defined (__ASSEMBLER__) */

4532

4533

#if !defined (__ASSEMBLER__)

4534

/* */

4535

typedef enum AC_INTLVL_enum

4536

{

4537

AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */

4538

AC_INTLVL_LO_gc = (0x01<<4), /* Low level */

4539

AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */

4540

AC_INTLVL_HI_gc = (0x03<<4), /* High level */

4541

} AC_INTLVL_t;

4542

#endif /* !defined (__ASSEMBLER__) */

4543

4544

#if !defined (__ASSEMBLER__)

4545

/* */

4546

typedef enum AC_HYSMODE_enum

4547

{

4548

AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */

4549

AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */

4550

AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */

4551

} AC_HYSMODE_t;

4552

#endif /* !defined (__ASSEMBLER__) */

4553

4554

#if !defined (__ASSEMBLER__)

4555

/* */

4556

typedef enum AC_MUXPOS_enum

4557

{

4558

AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */

4559

AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */

4560

AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */

4561

AC_MUXPOS_PIN3_gc = (0x02<<3), /* Pin 3 */

4562

AC_MUXPOS_PIN4_gc = (0x03<<3), /* Pin 4 */

4563

AC_MUXPOS_PIN5_gc = (0x04<<3), /* Pin 5 */

4564

AC_MUXPOS_PIN6_gc = (0x05<<3), /* Pin 6 */

4565

AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */

4566

} AC_MUXPOS_t;

4567

#endif /* !defined (__ASSEMBLER__) */

4568

4569

#if !defined (__ASSEMBLER__)

4570

/* */

4571

typedef enum AC_MUXNEG_enum

4572

{

4573

AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */

4574

AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */

4575

AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */

4576

AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */

4577

AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */

4578

AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */

4579

AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */

4580

AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */

4581

} AC_MUXNEG_t;

4582

#endif /* !defined (__ASSEMBLER__) */

4583

4584

#if !defined (__ASSEMBLER__)

4585

/* */

4586

typedef enum AC_WINTMODE_enum

4587

{

4588

AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */

4589

AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */

4590

AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */

4591

AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */

4592

} AC_WINTMODE_t;

4593

#endif /* !defined (__ASSEMBLER__) */

4594

4595

#if !defined (__ASSEMBLER__)

4596

/* */

4597

typedef enum AC_WINTLVL_enum

4598

{

4599

AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */

4600

AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */

4601

AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */

4602

AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */

4603

} AC_WINTLVL_t;

4604

#endif /* !defined (__ASSEMBLER__) */

4605

4606

#if !defined (__ASSEMBLER__)

4607

/* */

4608

typedef enum AC_WSTATE_enum

4609

{

4610

AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */

4611

AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */

4612

AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */

4613

} AC_WSTATE_t;

4614

#endif /* !defined (__ASSEMBLER__) */

4615

4616

4617

/*

4618

--------------------------------------------------------------------------

4619

ADC - Analog/Digital Converter

4620

--------------------------------------------------------------------------

4621

*/

4622

4623

/* ADC_CH.CTRL bit masks and bit positions */

4624

4625

4626

#define ADC_CH_START_bm 0x80 // Channel Start Conversion bit mask

4627

#define ADC_CH_START_bp 7 // Channel Start Conversion bit position

4628

#define ADC_CH_GAINFAC_gm 0x1C // Gain Factor group mask

4629

#define ADC_CH_GAINFAC_bp 2 // Gain Factor group position

4630

4631

#define ADC_CH_GAINFAC0_bm (1<<2) // Gain Factor bit 0 mask

4632

#define ADC_CH_GAINFAC0_bp 2 // Gain Factor bit 0 position

4633

#define ADC_CH_GAINFAC1_bm (1<<3) // Gain Factor bit 1 mask

4634

#define ADC_CH_GAINFAC1_bp 3 // Gain Factor bit 1 position

4635

#define ADC_CH_GAINFAC2_bm (1<<4) // Gain Factor bit 2 mask

4636

#define ADC_CH_GAINFAC2_bp 4 // Gain Factor bit 2 position

4637

#define ADC_CH_INPUTMODE_gm 0x03 // Negative Input Select group mask

4638

#define ADC_CH_INPUTMODE_bp 0 // Negative Input Select group position

4639

4640

#define ADC_CH_INPUTMODE0_bm (1<<0) // Negative Input Select bit 0 mask

4641

#define ADC_CH_INPUTMODE0_bp 0 // Negative Input Select bit 0 position

4642

#define ADC_CH_INPUTMODE1_bm (1<<1) // Negative Input Select bit 1 mask

4643

#define ADC_CH_INPUTMODE1_bp 1 // Negative Input Select bit 1 position

4644

4645

/* ADC_CH.MUXCTRL bit masks and bit positions */

4646

4647

4648

#define ADC_CH_MUXPOS_gm 0xF0 // Positive Input Select group mask

4649

#define ADC_CH_MUXPOS_bp 4 // Positive Input Select group position

4650

4651

#define ADC_CH_MUXPOS0_bm (1<<4) // Positive Input Select bit 0 mask

4652

#define ADC_CH_MUXPOS0_bp 4 // Positive Input Select bit 0 position

4653

#define ADC_CH_MUXPOS1_bm (1<<5) // Positive Input Select bit 1 mask

4654

#define ADC_CH_MUXPOS1_bp 5 // Positive Input Select bit 1 position

4655

#define ADC_CH_MUXPOS2_bm (1<<6) // Positive Input Select bit 2 mask

4656

#define ADC_CH_MUXPOS2_bp 6 // Positive Input Select bit 2 position

4657

#define ADC_CH_MUXPOS3_bm (1<<7) // Positive Input Select bit 3 mask

4658

#define ADC_CH_MUXPOS3_bp 7 // Positive Input Select bit 3 position

4659

#define ADC_CH_MUXINT_gm 0xF0 // Internal Input Select group mask

4660

#define ADC_CH_MUXINT_bp 4 // Internal Input Select group position

4661

4662

#define ADC_CH_MUXINT0_bm (1<<4) // Internal Input Select bit 0 mask

4663

#define ADC_CH_MUXINT0_bp 4 // Internal Input Select bit 0 position

4664

#define ADC_CH_MUXINT1_bm (1<<5) // Internal Input Select bit 1 mask

4665

#define ADC_CH_MUXINT1_bp 5 // Internal Input Select bit 1 position

4666

#define ADC_CH_MUXINT2_bm (1<<6) // Internal Input Select bit 2 mask

4667

#define ADC_CH_MUXINT2_bp 6 // Internal Input Select bit 2 position

4668

#define ADC_CH_MUXINT3_bm (1<<7) // Internal Input Select bit 3 mask

4669

#define ADC_CH_MUXINT3_bp 7 // Internal Input Select bit 3 position

4670

#define ADC_CH_MUXNEG_gm 0x03 // Negative Input Select group mask

4671

#define ADC_CH_MUXNEG_bp 0 // Negative Input Select group position

4672

4673

#define ADC_CH_MUXNEG0_bm (1<<0) // Negative Input Select bit 0 mask

4674

#define ADC_CH_MUXNEG0_bp 0 // Negative Input Select bit 0 position

4675

#define ADC_CH_MUXNEG1_bm (1<<1) // Negative Input Select bit 1 mask

4676

#define ADC_CH_MUXNEG1_bp 1 // Negative Input Select bit 1 position

4677

4678

/* ADC_CH.INTCTRL bit masks and bit positions */

4679

4680

4681

#define ADC_CH_INTMODE_gm 0x0C // Interrupt Mode group mask

4682

#define ADC_CH_INTMODE_bp 2 // Interrupt Mode group position

4683

4684

#define ADC_CH_INTMODE0_bm (1<<2) // Interrupt Mode bit 0 mask

4685

#define ADC_CH_INTMODE0_bp 2 // Interrupt Mode bit 0 position

4686

#define ADC_CH_INTMODE1_bm (1<<3) // Interrupt Mode bit 1 mask

4687

#define ADC_CH_INTMODE1_bp 3 // Interrupt Mode bit 1 position

4688

#define ADC_CH_INTLVL_gm 0x03 // Interrupt Level group mask

4689

#define ADC_CH_INTLVL_bp 0 // Interrupt Level group position

4690

4691

#define ADC_CH_INTLVL0_bm (1<<0) // Interrupt Level bit 0 mask

4692

#define ADC_CH_INTLVL0_bp 0 // Interrupt Level bit 0 position

4693

#define ADC_CH_INTLVL1_bm (1<<1) // Interrupt Level bit 1 mask

4694

#define ADC_CH_INTLVL1_bp 1 // Interrupt Level bit 1 position

4695

4696

/* ADC_CH.INTFLAGS bit masks and bit positions */

4697

4698

4699

#define ADC_CH_CHIF_bm 0x01 // Channel Interrupt Flag bit mask

4700

#define ADC_CH_CHIF_bp 0 // Channel Interrupt Flag bit position

4701

4702

/* ADC.CTRLA bit masks and bit positions */

4703

4704

4705

#define ADC_DMASEL_gm 0xE0 // DMA Selection group mask

4706

#define ADC_DMASEL_bp 5 // DMA Selection group position

4707

4708

#define ADC_DMASEL0_bm (1<<5) // DMA Selection bit 0 mask

4709

#define ADC_DMASEL0_bp 5 // DMA Selection bit 0 position

4710

#define ADC_DMASEL1_bm (1<<6) // DMA Selection bit 1 mask

4711

#define ADC_DMASEL1_bp 6 // DMA Selection bit 1 position

4712

#define ADC_DMASEL2_bm (1<<7) // DMA Selection bit 2 mask

4713

#define ADC_DMASEL2_bp 7 // DMA Selection bit 2 position

4714

#define ADC_CH3START_bm 0x20 // Channel 3 Start Conversion bit mask

4715

#define ADC_CH3START_bp 5 // Channel 3 Start Conversion bit position

4716

#define ADC_CH2START_bm 0x10 // Channel 2 Start Conversion bit mask

4717

#define ADC_CH2START_bp 4 // Channel 2 Start Conversion bit position

4718

#define ADC_CH1START_bm 0x08 // Channel 1 Start Conversion bit mask

4719

#define ADC_CH1START_bp 3 // Channel 1 Start Conversion bit position

4720

#define ADC_CH0START_bm 0x04 // Channel 0 Start Conversion bit mask

4721

#define ADC_CH0START_bp 2 // Channel 0 Start Conversion bit position

4722

#define ADC_FLUSH_bm 0x02 // Flush Pipeline bit mask

4723

#define ADC_FLUSH_bp 1 // Flush Pipeline bit position

4724

#define ADC_ENABLE_bm 0x01 // Enable ADC bit mask

4725

#define ADC_ENABLE_bp 0 // Enable ADC bit position

4726

4727

/* ADC.CTRLB bit masks and bit positions */

4728

4729

4730

#define ADC_CONMODE_bm 0x10 // Conversion Mode bit mask

4731

#define ADC_CONMODE_bp 4 // Conversion Mode bit position

4732

#define ADC_FREERUN_bm 0x08 // Free Running Mode Enable bit mask

4733

#define ADC_FREERUN_bp 3 // Free Running Mode Enable bit position

4734

#define ADC_RESOLUTION_gm 0x06 // Result Resolution group mask

4735

#define ADC_RESOLUTION_bp 1 // Result Resolution group position

4736

4737

#define ADC_RESOLUTION0_bm (1<<1) // Result Resolution bit 0 mask

4738

#define ADC_RESOLUTION0_bp 1 // Result Resolution bit 0 position

4739

#define ADC_RESOLUTION1_bm (1<<2) // Result Resolution bit 1 mask

4740

#define ADC_RESOLUTION1_bp 2 // Result Resolution bit 1 position

4741

4742

/* ADC.REFCTRL bit masks and bit positions */

4743

4744

4745

#define ADC_REFSEL_gm 0x30 // Reference Selection group mask

4746

#define ADC_REFSEL_bp 4 // Reference Selection group position

4747

4748

#define ADC_REFSEL0_bm (1<<4) // Reference Selection bit 0 mask

4749

#define ADC_REFSEL0_bp 4 // Reference Selection bit 0 position

4750

#define ADC_REFSEL1_bm (1<<5) // Reference Selection bit 1 mask

4751

#define ADC_REFSEL1_bp 5 // Reference Selection bit 1 position

4752

#define ADC_BANDGAP_bm 0x02 // Bandgap enable bit mask

4753

#define ADC_BANDGAP_bp 1 // Bandgap enable bit position

4754

#define ADC_TEMPREF_bm 0x01 // Temperature Reference Enable bit mask

4755

#define ADC_TEMPREF_bp 0 // Temperature Reference Enable bit position

4756

4757

/* ADC.EVCTRL bit masks and bit positions */

4758

4759

4760

#define ADC_SWEEP_gm 0xC0 // Channel Sweep Selection group mask

4761

#define ADC_SWEEP_bp 6 // Channel Sweep Selection group position

4762

4763

#define ADC_SWEEP0_bm (1<<6) // Channel Sweep Selection bit 0 mask

4764

#define ADC_SWEEP0_bp 6 // Channel Sweep Selection bit 0 position

4765

#define ADC_SWEEP1_bm (1<<7) // Channel Sweep Selection bit 1 mask

4766

#define ADC_SWEEP1_bp 7 // Channel Sweep Selection bit 1 position

4767

#define ADC_EVSEL_gm 0x38 // Event Input Select group mask

4768

#define ADC_EVSEL_bp 3 // Event Input Select group position

4769

4770

#define ADC_EVSEL0_bm (1<<3) // Event Input Select bit 0 mask

4771

#define ADC_EVSEL0_bp 3 // Event Input Select bit 0 position

4772

#define ADC_EVSEL1_bm (1<<4) // Event Input Select bit 1 mask

4773

#define ADC_EVSEL1_bp 4 // Event Input Select bit 1 position

4774

#define ADC_EVSEL2_bm (1<<5) // Event Input Select bit 2 mask

4775

#define ADC_EVSEL2_bp 5 // Event Input Select bit 2 position

4776

#define ADC_EVACT_gm 0x07 // Event Action Select group mask

4777

#define ADC_EVACT_bp 0 // Event Action Select group position

4778

4779

#define ADC_EVACT0_bm (1<<0) // Event Action Select bit 0 mask

4780

#define ADC_EVACT0_bp 0 // Event Action Select bit 0 position

4781

#define ADC_EVACT1_bm (1<<1) // Event Action Select bit 1 mask

4782

#define ADC_EVACT1_bp 1 // Event Action Select bit 1 position

4783

#define ADC_EVACT2_bm (1<<2) // Event Action Select bit 2 mask

4784

#define ADC_EVACT2_bp 2 // Event Action Select bit 2 position

4785

4786

/* ADC.PRESCALER bit masks and bit positions */

4787

4788

4789

#define ADC_PRESCALER_gm 0x07 // Clock Prescaler Selection group mask

4790

#define ADC_PRESCALER_bp 0 // Clock Prescaler Selection group position

4791

4792

#define ADC_PRESCALER0_bm (1<<0) // Clock Prescaler Selection bit 0 mask

4793

#define ADC_PRESCALER0_bp 0 // Clock Prescaler Selection bit 0 position

4794

#define ADC_PRESCALER1_bm (1<<1) // Clock Prescaler Selection bit 1 mask

4795

#define ADC_PRESCALER1_bp 1 // Clock Prescaler Selection bit 1 position

4796

#define ADC_PRESCALER2_bm (1<<2) // Clock Prescaler Selection bit 2 mask

4797

#define ADC_PRESCALER2_bp 2 // Clock Prescaler Selection bit 2 position

4798

4799

/* ADC.CALCTRL bit masks and bit positions */

4800

4801

4802

#define ADC_CAL_bm 0x01 // ADC Calibration Start bit mask

4803

#define ADC_CAL_bp 0 // ADC Calibration Start bit position

4804

4805

/* ADC.INTFLAGS bit masks and bit positions */

4806

4807

4808

#define ADC_CH3IF_bm 0x08 // Channel 3 Interrupt Flag bit mask

4809

#define ADC_CH3IF_bp 3 // Channel 3 Interrupt Flag bit position

4810

#define ADC_CH2IF_bm 0x04 // Channel 2 Interrupt Flag bit mask

4811

#define ADC_CH2IF_bp 2 // Channel 2 Interrupt Flag bit position

4812

#define ADC_CH1IF_bm 0x02 // Channel 1 Interrupt Flag bit mask

4813

#define ADC_CH1IF_bp 1 // Channel 1 Interrupt Flag bit position

4814

#define ADC_CH0IF_bm 0x01 // Channel 0 Interrupt Flag bit mask

4815

#define ADC_CH0IF_bp 0 // Channel 0 Interrupt Flag bit position

4816

4817

#if !defined (__ASSEMBLER__)

4818

/* */

4819

typedef enum ADC_CH_MUXPOS_enum

4820

{

4821

ADC_CH_MUXPOS_PIN0_gc = (0x00<<4), /* Input pin 0 */

4822

ADC_CH_MUXPOS_PIN1_gc = (0x01<<4), /* Input pin 1 */

4823

ADC_CH_MUXPOS_PIN2_gc = (0x02<<4), /* Input pin 2 */

4824

ADC_CH_MUXPOS_PIN3_gc = (0x03<<4), /* Input pin 3 */

4825

ADC_CH_MUXPOS_PIN4_gc = (0x04<<4), /* Input pin 4 */

4826

ADC_CH_MUXPOS_PIN5_gc = (0x05<<4), /* Input pin 5 */

4827

ADC_CH_MUXPOS_PIN6_gc = (0x06<<4), /* Input pin 6 */

4828

ADC_CH_MUXPOS_PIN7_gc = (0x07<<4), /* Input pin 7 */

4829

} ADC_CH_MUXPOS_t;

4830

#endif /* !defined (__ASSEMBLER__) */

4831

4832

#if !defined (__ASSEMBLER__)

4833

/* */

4834

typedef enum ADC_CH_MUXINT_enum

4835

{

4836

ADC_CH_MUXINT_TEMP_gc = (0x00<<0), /* Temperature Reference */

4837

ADC_CH_MUXINT_BANDGAP_gc = (0x01<<0), /* Bandgap Reference */

4838

ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<0), /* 1/10 scaled VCC */

4839

ADC_CH_MUXINT_DAC_gc = (0x03<<0), /* DAC output */

4840

} ADC_CH_MUXINT_t;

4841

#endif /* !defined (__ASSEMBLER__) */

4842

4843

#if !defined (__ASSEMBLER__)

4844

/* */

4845

typedef enum ADC_CH_MUXNEG_enum

4846

{

4847

ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */

4848

ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */

4849

ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */

4850

ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */

4851

ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */

4852

ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */

4853

ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */

4854

ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */

4855

} ADC_CH_MUXNEG_t;

4856

#endif /* !defined (__ASSEMBLER__) */

4857

4858

#if !defined (__ASSEMBLER__)

4859

/* */

4860

typedef enum ADC_CH_INPUTMODE_enum

4861

{

4862

ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */

4863

ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */

4864

ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */

4865

ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */

4866

} ADC_CH_INPUTMODE_t;

4867

#endif /* !defined (__ASSEMBLER__) */

4868

4869

#if !defined (__ASSEMBLER__)

4870

/* */

4871

typedef enum ADC_CH_GAINFAC_enum

4872

{

4873

ADC_CH_GAINFAC_1X_gc = (0x00<<0), /* 1x gain */

4874

ADC_CH_GAINFAC_2X_gc = (0x01<<0), /* 2x gain */

4875

ADC_CH_GAINFAC_4X_gc = (0x02<<0), /* 4x gain */

4876

ADC_CH_GAINFAC_8X_gc = (0x03<<0), /* 8x gain */

4877

ADC_CH_GAINFAC_16X_gc = (0x04<<0), /* 16x gain */

4878

ADC_CH_GAINFAC_32X_gc = (0x05<<0), /* 32x gain */

4879

ADC_CH_GAINFAC_64X_gc = (0x06<<0), /* 64x gain */

4880

} ADC_CH_GAINFAC_t;

4881

#endif /* !defined (__ASSEMBLER__) */

4882

4883

#if !defined (__ASSEMBLER__)

4884

/* */

4885

typedef enum ADC_RESOLUTION_enum

4886

{

4887

ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */

4888

ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */

4889

ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */

4890

} ADC_RESOLUTION_t;

4891

#endif /* !defined (__ASSEMBLER__) */

4892

4893

#if !defined (__ASSEMBLER__)

4894

/* */

4895

typedef enum ADC_REFSEL_enum

4896

{

4897

ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */

4898

ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC-0.6V */

4899

ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */

4900

ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */

4901

} ADC_REFSEL_t;

4902

#endif /* !defined (__ASSEMBLER__) */

4903

4904

#if !defined (__ASSEMBLER__)

4905

/* */

4906

typedef enum ADC_SWEEP_enum

4907

{

4908

ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */

4909

ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */

4910

ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */

4911

ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */

4912

} ADC_SWEEP_t;

4913

#endif /* !defined (__ASSEMBLER__) */

4914

4915

#if !defined (__ASSEMBLER__)

4916

/* */

4917

typedef enum ADC_EVSEL_enum

4918

{

4919

ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */

4920

ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */

4921

ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */

4922

ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */

4923

ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */

4924

ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */

4925

ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */

4926

ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */

4927

} ADC_EVSEL_t;

4928

#endif /* !defined (__ASSEMBLER__) */

4929

4930

#if !defined (__ASSEMBLER__)

4931

/* */

4932

typedef enum ADC_EVACT_enum

4933

{

4934

ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */

4935

ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */

4936

ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */

4937

ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */

4938

ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */

4939

ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */

4940

ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */

4941

} ADC_EVACT_t;

4942

#endif /* !defined (__ASSEMBLER__) */

4943

4944

#if !defined (__ASSEMBLER__)

4945

/* */

4946

typedef enum ADC_CH_INTMODE_enum

4947

{

4948

ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */

4949

ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */

4950

ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */

4951

} ADC_CH_INTMODE_t;

4952

#endif /* !defined (__ASSEMBLER__) */

4953

4954

#if !defined (__ASSEMBLER__)

4955

/* */

4956

typedef enum ADC_CH_INTLVL_enum

4957

{

4958

ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */

4959

ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */

4960

ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */

4961

ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */

4962

} ADC_CH_INTLVL_t;

4963

#endif /* !defined (__ASSEMBLER__) */

4964

4965

#if !defined (__ASSEMBLER__)

4966

/* */

4967

typedef enum ADC_DMASEL_enum

4968

{

4969

ADC_DMASEL_OFF_gc = (0x00<<5), /* Combined DMA request OFF */

4970

ADC_DMASEL_CH01_gc = (0x01<<5), /* ADC Channel 0 or 1 */

4971

ADC_DMASEL_CH012_gc = (0x02<<5), /* ADC Channel 0 or 1 or 2 */

4972

ADC_DMASEL_CH0123_gc = (0x03<<5), /* ADC Channel 0 or 1 or 2 or 3 */

4973

} ADC_DMASEL_t;

4974

#endif /* !defined (__ASSEMBLER__) */

4975

4976

#if !defined (__ASSEMBLER__)

4977

/* */

4978

typedef enum ADC_PRESCALER_enum

4979

{

4980

ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */

4981

ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */

4982

ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */

4983

ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */

4984

ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */

4985

ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */

4986

ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */

4987

ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */

4988

} ADC_PRESCALER_t;

4989

#endif /* !defined (__ASSEMBLER__) */

4990

4991

4992

/*

4993

--------------------------------------------------------------------------

4994

DAC - Digital/Analog Converter

4995

--------------------------------------------------------------------------

4996

*/

4997

4998

/* DAC.CTRLA bit masks and bit positions */

4999

5000

5001

#define DAC_IDOEN_bm 0x10 // Internal Output Enable bit mask

5002

#define DAC_IDOEN_bp 4 // Internal Output Enable bit position

5003

#define DAC_CH1EN_bm 0x08 // Channel 1 Output Enable bit mask

5004

#define DAC_CH1EN_bp 3 // Channel 1 Output Enable bit position

5005

#define DAC_CH0EN_bm 0x04 // Channel 0 Output Enable bit mask

5006

#define DAC_CH0EN_bp 2 // Channel 0 Output Enable bit position

5007

#define DAC_LPMODE_bm 0x02 // Low Power Mode bit mask

5008

#define DAC_LPMODE_bp 1 // Low Power Mode bit position

5009

#define DAC_ENABLE_bm 0x01 // Enable bit mask

5010

#define DAC_ENABLE_bp 0 // Enable bit position

5011

5012

/* DAC.CTRLB bit masks and bit positions */

5013

5014

5015

#define DAC_CHSEL_gm 0x60 // Channel Select group mask

5016

#define DAC_CHSEL_bp 5 // Channel Select group position

5017

5018

#define DAC_CHSEL0_bm (1<<5) // Channel Select bit 0 mask

5019

#define DAC_CHSEL0_bp 5 // Channel Select bit 0 position

5020

#define DAC_CHSEL1_bm (1<<6) // Channel Select bit 1 mask

5021

#define DAC_CHSEL1_bp 6 // Channel Select bit 1 position

5022

#define DAC_CH1TRIG_bm 0x02 // Channel 1 Event Trig Enable bit mask

5023

#define DAC_CH1TRIG_bp 1 // Channel 1 Event Trig Enable bit position

5024

#define DAC_CH0TRIG_bm 0x01 // Channel 0 Event Trig Enable bit mask

5025

#define DAC_CH0TRIG_bp 0 // Channel 0 Event Trig Enable bit position

5026

5027

/* DAC.CTRLC bit masks and bit positions */

5028

5029

5030

#define DAC_REFSEL_gm 0x18 // Reference Select group mask

5031

#define DAC_REFSEL_bp 3 // Reference Select group position

5032

5033

#define DAC_REFSEL0_bm (1<<3) // Reference Select bit 0 mask

5034

#define DAC_REFSEL0_bp 3 // Reference Select bit 0 position

5035

#define DAC_REFSEL1_bm (1<<4) // Reference Select bit 1 mask

5036

#define DAC_REFSEL1_bp 4 // Reference Select bit 1 position

5037

#define DAC_LEFTADJ_bm 0x01 // Left-adjust Result bit mask

5038

#define DAC_LEFTADJ_bp 0 // Left-adjust Result bit position

5039

5040

/* DAC.EVCTRL bit masks and bit positions */

5041

5042

5043

#define DAC_EVSEL_gm 0x07 // Event Input Selection group mask

5044

#define DAC_EVSEL_bp 0 // Event Input Selection group position

5045

5046

#define DAC_EVSEL0_bm (1<<0) // Event Input Selection bit 0 mask

5047

#define DAC_EVSEL0_bp 0 // Event Input Selection bit 0 position

5048

#define DAC_EVSEL1_bm (1<<1) // Event Input Selection bit 1 mask

5049

#define DAC_EVSEL1_bp 1 // Event Input Selection bit 1 position

5050

#define DAC_EVSEL2_bm (1<<2) // Event Input Selection bit 2 mask

5051

#define DAC_EVSEL2_bp 2 // Event Input Selection bit 2 position

5052

5053

/* DAC.TIMCTRL bit masks and bit positions */

5054

5055

5056

#define DAC_CONINTVAL_gm 0x70 // Conversion Intercal group mask

5057

#define DAC_CONINTVAL_bp 4 // Conversion Intercal group position

5058

5059

#define DAC_CONINTVAL0_bm (1<<4) // Conversion Intercal bit 0 mask

5060

#define DAC_CONINTVAL0_bp 4 // Conversion Intercal bit 0 position

5061

#define DAC_CONINTVAL1_bm (1<<5) // Conversion Intercal bit 1 mask

5062

#define DAC_CONINTVAL1_bp 5 // Conversion Intercal bit 1 position

5063

#define DAC_CONINTVAL2_bm (1<<6) // Conversion Intercal bit 2 mask

5064

#define DAC_CONINTVAL2_bp 6 // Conversion Intercal bit 2 position

5065

#define DAC_REFRESH_gm 0x0F // Refresh Timing Control group mask

5066

#define DAC_REFRESH_bp 0 // Refresh Timing Control group position

5067

5068

#define DAC_REFRESH0_bm (1<<0) // Refresh Timing Control bit 0 mask

5069

#define DAC_REFRESH0_bp 0 // Refresh Timing Control bit 0 position

5070

#define DAC_REFRESH1_bm (1<<1) // Refresh Timing Control bit 1 mask

5071

#define DAC_REFRESH1_bp 1 // Refresh Timing Control bit 1 position

5072

#define DAC_REFRESH2_bm (1<<2) // Refresh Timing Control bit 2 mask

5073

#define DAC_REFRESH2_bp 2 // Refresh Timing Control bit 2 position

5074

#define DAC_REFRESH3_bm (1<<3) // Refresh Timing Control bit 3 mask

5075

#define DAC_REFRESH3_bp 3 // Refresh Timing Control bit 3 position

5076

5077

/* DAC.STATUS bit masks and bit positions */

5078

5079

5080

#define DAC_CH1DRE_bm 0x02 // Channel 1 Data Register Empty bit mask

5081

#define DAC_CH1DRE_bp 1 // Channel 1 Data Register Empty bit position

5082

#define DAC_CH0DRE_bm 0x01 // Channel 0 Data Register Empty bit mask

5083

#define DAC_CH0DRE_bp 0 // Channel 0 Data Register Empty bit position

5084

5085

#if !defined (__ASSEMBLER__)

5086

/* */

5087

typedef enum DAC_CHSEL_enum

5088

{

5089

DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */

5090

DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */

5091

} DAC_CHSEL_t;

5092

#endif /* !defined (__ASSEMBLER__) */

5093

5094

#if !defined (__ASSEMBLER__)

5095

/* */

5096

typedef enum DAC_REFSEL_enum

5097

{

5098

DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */

5099

DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */

5100

DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */

5101

DAC_REFSEL_AREFB_gc = (0x02<<3), /* External reference on AREF on PORTB */

5102

} DAC_REFSEL_t;

5103

#endif /* !defined (__ASSEMBLER__) */

5104

5105

#if !defined (__ASSEMBLER__)

5106

/* */

5107

typedef enum DAC_EVSEL_enum

5108

{

5109

DAC_EVSEL_EV0_gc = (0x00<<0), /* Event Channel 0 */

5110

DAC_EVSEL_EV1_gc = (0x01<<0), /* Event Channel 1 */

5111

DAC_EVSEL_EV2_gc = (0x02<<0), /* Event Channel 2 */

5112

DAC_EVSEL_EV3_gc = (0x03<<0), /* Event Channele 3 */

5113

DAC_EVSEL_EV4_gc = (0x04<<0), /* Event Channel 4 */

5114

DAC_EVSEL_EV5_gc = (0x05<<0), /* Event Channel 5 */

5115

DAC_EVSEL_EV6_gc = (0x06<<0), /* Event Channel 6 */

5116

DAC_EVSEL_EV7_gc = (0x07<<0), /* Event Channel 7 */

5117

} DAC_EVSEL_t;

5118

#endif /* !defined (__ASSEMBLER__) */

5119

5120

#if !defined (__ASSEMBLER__)

5121

/* */

5122

typedef enum DAC_CONINTVAL_enum

5123

{

5124

DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */

5125

DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */

5126

DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */

5127

DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */

5128

DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */

5129

DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */

5130

DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */

5131

DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */

5132

} DAC_CONINTVAL_t;

5133

#endif /* !defined (__ASSEMBLER__) */

5134

5135

#if !defined (__ASSEMBLER__)

5136

/* */

5137

typedef enum DAC_REFRESH_enum

5138

{

5139

DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */

5140

DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */

5141

DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */

5142

DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */

5143

DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */

5144

DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */

5145

DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */

5146

DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */

5147

DAC_REFRESH_4086CLK_gc = (0x08<<0), /* 4096 CLK */

5148

DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */

5149

DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */

5150

DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */

5151

DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */

5152

DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */

5153

} DAC_REFRESH_t;

5154

#endif /* !defined (__ASSEMBLER__) */

5155

5156

5157

/*

5158

--------------------------------------------------------------------------

5159

RTC - Real-Time Clock

5160

--------------------------------------------------------------------------

5161

*/

5162

5163

/* RTC.CTRL bit masks and bit positions */

5164

5165

5166

#define RTC_PRESCALER_gm 0x07 // Prescaling Factor group mask

5167

#define RTC_PRESCALER_bp 0 // Prescaling Factor group position

5168

5169

#define RTC_PRESCALER0_bm (1<<0) // Prescaling Factor bit 0 mask

5170

#define RTC_PRESCALER0_bp 0 // Prescaling Factor bit 0 position

5171

#define RTC_PRESCALER1_bm (1<<1) // Prescaling Factor bit 1 mask

5172

#define RTC_PRESCALER1_bp 1 // Prescaling Factor bit 1 position

5173

#define RTC_PRESCALER2_bm (1<<2) // Prescaling Factor bit 2 mask

5174

#define RTC_PRESCALER2_bp 2 // Prescaling Factor bit 2 position

5175

5176

/* RTC.STATUS bit masks and bit positions */

5177

5178

5179

#define RTC_SYNCBUSY_bm 0x01 // Synchronization Busy Flag bit mask

5180

#define RTC_SYNCBUSY_bp 0 // Synchronization Busy Flag bit position

5181

5182

/* RTC.INTCTRL bit masks and bit positions */

5183

5184

5185

#define RTC_COMPINTLVL_gm 0x0C // Compare Match Interrupt Level group mask

5186

#define RTC_COMPINTLVL_bp 2 // Compare Match Interrupt Level group position

5187

5188

#define RTC_COMPINTLVL0_bm (1<<2) // Compare Match Interrupt Level bit 0 mask

5189

#define RTC_COMPINTLVL0_bp 2 // Compare Match Interrupt Level bit 0 position

5190

#define RTC_COMPINTLVL1_bm (1<<3) // Compare Match Interrupt Level bit 1 mask

5191

#define RTC_COMPINTLVL1_bp 3 // Compare Match Interrupt Level bit 1 position

5192

#define RTC_OVFINTLVL_gm 0x03 // Overflow Interrupt Level group mask

5193

#define RTC_OVFINTLVL_bp 0 // Overflow Interrupt Level group position

5194

5195

#define RTC_OVFINTLVL0_bm (1<<0) // Overflow Interrupt Level bit 0 mask

5196

#define RTC_OVFINTLVL0_bp 0 // Overflow Interrupt Level bit 0 position

5197

#define RTC_OVFINTLVL1_bm (1<<1) // Overflow Interrupt Level bit 1 mask

5198

#define RTC_OVFINTLVL1_bp 1 // Overflow Interrupt Level bit 1 position

5199

5200

/* RTC.INTFLAGS bit masks and bit positions */

5201

5202

5203

#define RTC_COMPIF_bm 0x02 // Compare Match Interrupt Flag bit mask

5204

#define RTC_COMPIF_bp 1 // Compare Match Interrupt Flag bit position

5205

#define RTC_OVFIF_bm 0x01 // Overflow Interrupt Flag bit mask

5206

#define RTC_OVFIF_bp 0 // Overflow Interrupt Flag bit position

5207

5208

#if !defined (__ASSEMBLER__)

5209

/* Prescaler Factor */

5210

typedef enum RTC_PRESCALER_enum

5211

{

5212

RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */

5213

RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */

5214

RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */

5215

RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */

5216

RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */

5217

RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */

5218

RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */

5219

RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */

5220

} RTC_PRESCALER_t;

5221

#endif /* !defined (__ASSEMBLER__) */

5222

5223

#if !defined (__ASSEMBLER__)

5224

/* Compare Interrupt level */

5225

typedef enum RTC_COMPINTLVL_enum

5226

{

5227

RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */

5228

RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */

5229

RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */

5230

RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */

5231

} RTC_COMPINTLVL_t;

5232

#endif /* !defined (__ASSEMBLER__) */

5233

5234

#if !defined (__ASSEMBLER__)

5235

/* Overflow Interrupt level */

5236

typedef enum RTC_OVFINTLVL_enum

5237

{

5238

RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */

5239

RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */

5240

RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */

5241

RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */

5242

} RTC_OVFINTLVL_t;

5243

#endif /* !defined (__ASSEMBLER__) */

5244

5245

5246

/*

5247

--------------------------------------------------------------------------

5248

EBI - External Bus Interface

5249

--------------------------------------------------------------------------

5250

*/

5251

5252

/* EBI_CS.CTRLA bit masks and bit positions */

5253

5254

5255

#define EBI_CS_ASPACE_gm 0x7C // Address Space group mask

5256

#define EBI_CS_ASPACE_bp 2 // Address Space group position

5257

5258

#define EBI_CS_ASPACE0_bm (1<<2) // Address Space bit 0 mask

5259

#define EBI_CS_ASPACE0_bp 2 // Address Space bit 0 position

5260

#define EBI_CS_ASPACE1_bm (1<<3) // Address Space bit 1 mask

5261

#define EBI_CS_ASPACE1_bp 3 // Address Space bit 1 position

5262

#define EBI_CS_ASPACE2_bm (1<<4) // Address Space bit 2 mask

5263

#define EBI_CS_ASPACE2_bp 4 // Address Space bit 2 position

5264

#define EBI_CS_ASPACE3_bm (1<<5) // Address Space bit 3 mask

5265

#define EBI_CS_ASPACE3_bp 5 // Address Space bit 3 position

5266

#define EBI_CS_ASPACE4_bm (1<<6) // Address Space bit 4 mask

5267

#define EBI_CS_ASPACE4_bp 6 // Address Space bit 4 position

5268

#define EBI_CS_MODE_gm 0x03 // Memory Mode group mask

5269

#define EBI_CS_MODE_bp 0 // Memory Mode group position

5270

5271

#define EBI_CS_MODE0_bm (1<<0) // Memory Mode bit 0 mask

5272

#define EBI_CS_MODE0_bp 0 // Memory Mode bit 0 position

5273

#define EBI_CS_MODE1_bm (1<<1) // Memory Mode bit 1 mask

5274

#define EBI_CS_MODE1_bp 1 // Memory Mode bit 1 position

5275

5276

/* EBI_CS.CTRLB bit masks and bit positions */

5277

5278

5279

#define EBI_CS_SRWS_gm 0x07 // SRAM Wait State Cycles group mask

5280

#define EBI_CS_SRWS_bp 0 // SRAM Wait State Cycles group position

5281

5282

#define EBI_CS_SRWS0_bm (1<<0) // SRAM Wait State Cycles bit 0 mask

5283

#define EBI_CS_SRWS0_bp 0 // SRAM Wait State Cycles bit 0 position

5284

#define EBI_CS_SRWS1_bm (1<<1) // SRAM Wait State Cycles bit 1 mask

5285

#define EBI_CS_SRWS1_bp 1 // SRAM Wait State Cycles bit 1 position

5286

#define EBI_CS_SRWS2_bm (1<<2) // SRAM Wait State Cycles bit 2 mask

5287

#define EBI_CS_SRWS2_bp 2 // SRAM Wait State Cycles bit 2 position

5288

#define EBI_CS_SDINITDONE_bm 0x80 // SDRAM Initialization Done bit mask

5289

#define EBI_CS_SDINITDONE_bp 7 // SDRAM Initialization Done bit position

5290

#define EBI_CS_SDSREN_bm 0x04 // SDRAM Self-refresh Enable bit mask

5291

#define EBI_CS_SDSREN_bp 2 // SDRAM Self-refresh Enable bit position

5292

#define EBI_CS_SDMODE_gm 0x03 // SDRAM Mode group mask

5293

#define EBI_CS_SDMODE_bp 0 // SDRAM Mode group position

5294

5295

#define EBI_CS_SDMODE0_bm (1<<0) // SDRAM Mode bit 0 mask

5296

#define EBI_CS_SDMODE0_bp 0 // SDRAM Mode bit 0 position

5297

#define EBI_CS_SDMODE1_bm (1<<1) // SDRAM Mode bit 1 mask

5298

#define EBI_CS_SDMODE1_bp 1 // SDRAM Mode bit 1 position

5299

5300

/* EBI.CTRL bit masks and bit positions */

5301

5302

5303

#define EBI_SDDATAW_gm 0xC0 // SDRAM Data Width Setting group mask

5304

#define EBI_SDDATAW_bp 6 // SDRAM Data Width Setting group position

5305

5306

#define EBI_SDDATAW0_bm (1<<6) // SDRAM Data Width Setting bit 0 mask

5307

#define EBI_SDDATAW0_bp 6 // SDRAM Data Width Setting bit 0 position

5308

#define EBI_SDDATAW1_bm (1<<7) // SDRAM Data Width Setting bit 1 mask

5309

#define EBI_SDDATAW1_bp 7 // SDRAM Data Width Setting bit 1 position

5310

#define EBI_LPCMODE_gm 0x30 // SRAM LPC Mode group mask

5311

#define EBI_LPCMODE_bp 4 // SRAM LPC Mode group position

5312

5313

#define EBI_LPCMODE0_bm (1<<4) // SRAM LPC Mode bit 0 mask

5314

#define EBI_LPCMODE0_bp 4 // SRAM LPC Mode bit 0 position

5315

#define EBI_LPCMODE1_bm (1<<5) // SRAM LPC Mode bit 1 mask

5316

#define EBI_LPCMODE1_bp 5 // SRAM LPC Mode bit 1 position

5317

#define EBI_SRMODE_gm 0x0C // SRAM Mode group mask

5318

#define EBI_SRMODE_bp 2 // SRAM Mode group position

5319

5320

#define EBI_SRMODE0_bm (1<<2) // SRAM Mode bit 0 mask

5321

#define EBI_SRMODE0_bp 2 // SRAM Mode bit 0 position

5322

#define EBI_SRMODE1_bm (1<<3) // SRAM Mode bit 1 mask

5323

#define EBI_SRMODE1_bp 3 // SRAM Mode bit 1 position

5324

#define EBI_IFMODE_gm 0x03 // Interface Mode group mask

5325

#define EBI_IFMODE_bp 0 // Interface Mode group position

5326

5327

#define EBI_IFMODE0_bm (1<<0) // Interface Mode bit 0 mask

5328

#define EBI_IFMODE0_bp 0 // Interface Mode bit 0 position

5329

#define EBI_IFMODE1_bm (1<<1) // Interface Mode bit 1 mask

5330

#define EBI_IFMODE1_bp 1 // Interface Mode bit 1 position

5331

5332

/* EBI.SDRAMCTRLA bit masks and bit positions */

5333

5334

5335

#define EBI_SDCAS_bm 0x08 // SDRAM CAS Latency Setting bit mask

5336

#define EBI_SDCAS_bp 3 // SDRAM CAS Latency Setting bit position

5337

#define EBI_SDROW_bm 0x04 // SDRAM ROW Bits Setting bit mask

5338

#define EBI_SDROW_bp 2 // SDRAM ROW Bits Setting bit position

5339

#define EBI_SDCOL_gm 0x03 // SDRAM Column Bits Setting group mask

5340

#define EBI_SDCOL_bp 0 // SDRAM Column Bits Setting group position

5341

5342

#define EBI_SDCOL0_bm (1<<0) // SDRAM Column Bits Setting bit 0 mask

5343

#define EBI_SDCOL0_bp 0 // SDRAM Column Bits Setting bit 0 position

5344

#define EBI_SDCOL1_bm (1<<1) // SDRAM Column Bits Setting bit 1 mask

5345

#define EBI_SDCOL1_bp 1 // SDRAM Column Bits Setting bit 1 position

5346

5347

/* EBI.SDRAMCTRLB bit masks and bit positions */

5348

5349

5350

#define EBI_MRDLY_gm 0xC0 // SDRAM Mode Register Delay group mask

5351

#define EBI_MRDLY_bp 6 // SDRAM Mode Register Delay group position

5352

5353

#define EBI_MRDLY0_bm (1<<6) // SDRAM Mode Register Delay bit 0 mask

5354

#define EBI_MRDLY0_bp 6 // SDRAM Mode Register Delay bit 0 position

5355

#define EBI_MRDLY1_bm (1<<7) // SDRAM Mode Register Delay bit 1 mask

5356

#define EBI_MRDLY1_bp 7 // SDRAM Mode Register Delay bit 1 position

5357

#define EBI_ROWCYCDLY_gm 0x38 // SDRAM Row Cycle Delay group mask

5358

#define EBI_ROWCYCDLY_bp 3 // SDRAM Row Cycle Delay group position

5359

5360

#define EBI_ROWCYCDLY0_bm (1<<3) // SDRAM Row Cycle Delay bit 0 mask

5361

#define EBI_ROWCYCDLY0_bp 3 // SDRAM Row Cycle Delay bit 0 position

5362

#define EBI_ROWCYCDLY1_bm (1<<4) // SDRAM Row Cycle Delay bit 1 mask

5363

#define EBI_ROWCYCDLY1_bp 4 // SDRAM Row Cycle Delay bit 1 position

5364

#define EBI_ROWCYCDLY2_bm (1<<5) // SDRAM Row Cycle Delay bit 2 mask

5365

#define EBI_ROWCYCDLY2_bp 5 // SDRAM Row Cycle Delay bit 2 position

5366

#define EBI_RPDLY_gm 0x07 // SDRAM Row-to-Precharge Delay group mask

5367

#define EBI_RPDLY_bp 0 // SDRAM Row-to-Precharge Delay group position

5368

5369

#define EBI_RPDLY0_bm (1<<0) // SDRAM Row-to-Precharge Delay bit 0 mask

5370

#define EBI_RPDLY0_bp 0 // SDRAM Row-to-Precharge Delay bit 0 position

5371

#define EBI_RPDLY1_bm (1<<1) // SDRAM Row-to-Precharge Delay bit 1 mask

5372

#define EBI_RPDLY1_bp 1 // SDRAM Row-to-Precharge Delay bit 1 position

5373

#define EBI_RPDLY2_bm (1<<2) // SDRAM Row-to-Precharge Delay bit 2 mask

5374

#define EBI_RPDLY2_bp 2 // SDRAM Row-to-Precharge Delay bit 2 position

5375

5376

/* EBI.SDRAMCTRLC bit masks and bit positions */

5377

5378

5379

#define EBI_WRDLY_gm 0xC0 // SDRAM Write Recovery Delay group mask

5380

#define EBI_WRDLY_bp 6 // SDRAM Write Recovery Delay group position

5381

5382

#define EBI_WRDLY0_bm (1<<6) // SDRAM Write Recovery Delay bit 0 mask

5383

#define EBI_WRDLY0_bp 6 // SDRAM Write Recovery Delay bit 0 position

5384

#define EBI_WRDLY1_bm (1<<7) // SDRAM Write Recovery Delay bit 1 mask

5385

#define EBI_WRDLY1_bp 7 // SDRAM Write Recovery Delay bit 1 position

5386

#define EBI_ESRDLY_gm 0x38 // SDRAM Exit-Self-refresh-to-Active Delay group mask

5387

#define EBI_ESRDLY_bp 3 // SDRAM Exit-Self-refresh-to-Active Delay group position

5388

5389

#define EBI_ESRDLY0_bm (1<<3) // SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask

5390

#define EBI_ESRDLY0_bp 3 // SDRAM Exit-Self-refresh-to-Active Delay bit 0 position

5391

#define EBI_ESRDLY1_bm (1<<4) // SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask

5392

#define EBI_ESRDLY1_bp 4 // SDRAM Exit-Self-refresh-to-Active Delay bit 1 position

5393

#define EBI_ESRDLY2_bm (1<<5) // SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask

5394

#define EBI_ESRDLY2_bp 5 // SDRAM Exit-Self-refresh-to-Active Delay bit 2 position

5395

#define EBI_ROWCOLDLY_gm 0x07 // SDRAM Row-to-Column Delay group mask

5396

#define EBI_ROWCOLDLY_bp 0 // SDRAM Row-to-Column Delay group position

5397

5398

#define EBI_ROWCOLDLY0_bm (1<<0) // SDRAM Row-to-Column Delay bit 0 mask

5399

#define EBI_ROWCOLDLY0_bp 0 // SDRAM Row-to-Column Delay bit 0 position

5400

#define EBI_ROWCOLDLY1_bm (1<<1) // SDRAM Row-to-Column Delay bit 1 mask

5401

#define EBI_ROWCOLDLY1_bp 1 // SDRAM Row-to-Column Delay bit 1 position

5402

#define EBI_ROWCOLDLY2_bm (1<<2) // SDRAM Row-to-Column Delay bit 2 mask

5403

#define EBI_ROWCOLDLY2_bp 2 // SDRAM Row-to-Column Delay bit 2 position

5404

5405

#if !defined (__ASSEMBLER__)

5406

/* */

5407

typedef enum EBI_CS_ASPACE_enum

5408

{

5409

EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */

5410

EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */

5411

EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */

5412

EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */

5413

EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */

5414

EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */

5415

EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */

5416

EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */

5417

EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */

5418

EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */

5419

EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */

5420

EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */

5421

EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */

5422

EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */

5423

EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */

5424

EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */

5425

EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */

5426

} EBI_CS_ASPACE_t;

5427

#endif /* !defined (__ASSEMBLER__) */

5428

5429

#if !defined (__ASSEMBLER__)

5430

/* */

5431

typedef enum EBI_CS_MODE_enum

5432

{

5433

EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */

5434

EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */

5435

EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */

5436

EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */

5437

} EBI_CS_MODE_t;

5438

#endif /* !defined (__ASSEMBLER__) */

5439

5440

#if !defined (__ASSEMBLER__)

5441

/* */

5442

typedef enum EBI_CS_SDMODE_enum

5443

{

5444

EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */

5445

EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */

5446

} EBI_CS_SDMODE_t;

5447

#endif /* !defined (__ASSEMBLER__) */

5448

5449

#if !defined (__ASSEMBLER__)

5450

/* */

5451

typedef enum EBI_SDDATAW_enum

5452

{

5453

EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */

5454

EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */

5455

} EBI_SDDATAW_t;

5456

#endif /* !defined (__ASSEMBLER__) */

5457

5458

#if !defined (__ASSEMBLER__)

5459

/* */

5460

typedef enum EBI_LPCMODE_enum

5461

{

5462

EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */

5463

EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */

5464

} EBI_LPCMODE_t;

5465

#endif /* !defined (__ASSEMBLER__) */

5466

5467

#if !defined (__ASSEMBLER__)

5468

/* */

5469

typedef enum EBI_SRMODE_enum

5470

{

5471

EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */

5472

EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */

5473

EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */

5474

EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */

5475

} EBI_SRMODE_t;

5476

#endif /* !defined (__ASSEMBLER__) */

5477

5478

#if !defined (__ASSEMBLER__)

5479

/* */

5480

typedef enum EBI_IFMODE_enum

5481

{

5482

EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */

5483

EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */

5484

EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */

5485

EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */

5486

} EBI_IFMODE_t;

5487

#endif /* !defined (__ASSEMBLER__) */

5488

5489

#if !defined (__ASSEMBLER__)

5490

/* */

5491

typedef enum EBI_SDCOL_enum

5492

{

5493

EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */

5494

EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */

5495

EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */

5496

EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */

5497

} EBI_SDCOL_t;

5498

#endif /* !defined (__ASSEMBLER__) */

5499

5500

#if !defined (__ASSEMBLER__)

5501

/* */

5502

typedef enum EBI_MRDLY_enum

5503

{

5504

EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */

5505

EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */

5506

EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */

5507

EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */

5508

} EBI_MRDLY_t;

5509

#endif /* !defined (__ASSEMBLER__) */

5510

5511

#if !defined (__ASSEMBLER__)

5512

/* */

5513

typedef enum EBI_ROWCYCDLY_enum

5514

{

5515

EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */

5516

EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */

5517

EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */

5518

EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */

5519

EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */

5520

EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */

5521

EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */

5522

EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */

5523

} EBI_ROWCYCDLY_t;

5524

#endif /* !defined (__ASSEMBLER__) */

5525

5526

#if !defined (__ASSEMBLER__)

5527

/* */

5528

typedef enum EBI_RPDLY_enum

5529

{

5530

EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */

5531

EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */

5532

EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */

5533

EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */

5534

EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */

5535

EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */

5536

EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */

5537

EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */

5538

} EBI_RPDLY_t;

5539

#endif /* !defined (__ASSEMBLER__) */

5540

5541

#if !defined (__ASSEMBLER__)

5542

/* */

5543

typedef enum EBI_WRDLY_enum

5544

{

5545

EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */

5546

EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */

5547

EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */

5548

EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */

5549

} EBI_WRDLY_t;

5550

#endif /* !defined (__ASSEMBLER__) */

5551

5552

#if !defined (__ASSEMBLER__)

5553

/* */

5554

typedef enum EBI_ESRDLY_enum

5555

{

5556

EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */

5557

EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */

5558

EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */

5559

EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */

5560

EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */

5561

EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */

5562

EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */

5563

EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */

5564

} EBI_ESRDLY_t;

5565

#endif /* !defined (__ASSEMBLER__) */

5566

5567

#if !defined (__ASSEMBLER__)

5568

/* */

5569

typedef enum EBI_ROWCOLDLY_enum

5570

{

5571

EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */

5572

EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */

5573

EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */

5574

EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */

5575

EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */

5576

EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */

5577

EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */

5578

EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */

5579

} EBI_ROWCOLDLY_t;

5580

#endif /* !defined (__ASSEMBLER__) */

5581

5582

5583

/*

5584

--------------------------------------------------------------------------

5585

TWI - Two-Wire Interface

5586

--------------------------------------------------------------------------

5587

*/

5588

5589

/* TWI_MASTER.CTRLA bit masks and bit positions */

5590

5591

5592

#define TWI_MASTER_INTLVL_gm 0xC0 // Interrupt Level group mask

5593

#define TWI_MASTER_INTLVL_bp 6 // Interrupt Level group position

5594

5595

#define TWI_MASTER_INTLVL0_bm (1<<6) // Interrupt Level bit 0 mask

5596

#define TWI_MASTER_INTLVL0_bp 6 // Interrupt Level bit 0 position

5597

#define TWI_MASTER_INTLVL1_bm (1<<7) // Interrupt Level bit 1 mask

5598

#define TWI_MASTER_INTLVL1_bp 7 // Interrupt Level bit 1 position

5599

#define TWI_MASTER_RIEN_bm 0x20 // Read Interrupt Enable bit mask

5600

#define TWI_MASTER_RIEN_bp 5 // Read Interrupt Enable bit position

5601

#define TWI_MASTER_WIEN_bm 0x10 // Write Interrupt Enable bit mask

5602

#define TWI_MASTER_WIEN_bp 4 // Write Interrupt Enable bit position

5603

#define TWI_MASTER_ENABLE_bm 0x08 // Enable TWI Master bit mask

5604

#define TWI_MASTER_ENABLE_bp 3 // Enable TWI Master bit position

5605

5606

/* TWI_MASTER.CTRLB bit masks and bit positions */

5607

5608

5609

#define TWI_MASTER_TIMEOUT_gm 0x0C // Inactive Bus Timeout group mask

5610

#define TWI_MASTER_TIMEOUT_bp 2 // Inactive Bus Timeout group position

5611

5612

#define TWI_MASTER_TIMEOUT0_bm (1<<2) // Inactive Bus Timeout bit 0 mask

5613

#define TWI_MASTER_TIMEOUT0_bp 2 // Inactive Bus Timeout bit 0 position

5614

#define TWI_MASTER_TIMEOUT1_bm (1<<3) // Inactive Bus Timeout bit 1 mask

5615

#define TWI_MASTER_TIMEOUT1_bp 3 // Inactive Bus Timeout bit 1 position

5616

#define TWI_MASTER_QCEN_bm 0x02 // Quick Command Enable bit mask

5617

#define TWI_MASTER_QCEN_bp 1 // Quick Command Enable bit position

5618

#define TWI_MASTER_SMEN_bm 0x01 // Smart Mode Enable bit mask

5619

#define TWI_MASTER_SMEN_bp 0 // Smart Mode Enable bit position

5620

5621

/* TWI_MASTER.CTRLC bit masks and bit positions */

5622

5623

5624

#define TWI_MASTER_ACKACT_bm 0x04 // Acknowledge Action bit mask

5625

#define TWI_MASTER_ACKACT_bp 2 // Acknowledge Action bit position

5626

#define TWI_MASTER_CMD_gm 0x03 // Command group mask

5627

#define TWI_MASTER_CMD_bp 0 // Command group position

5628

5629

#define TWI_MASTER_CMD0_bm (1<<0) // Command bit 0 mask

5630

#define TWI_MASTER_CMD0_bp 0 // Command bit 0 position

5631

#define TWI_MASTER_CMD1_bm (1<<1) // Command bit 1 mask

5632

#define TWI_MASTER_CMD1_bp 1 // Command bit 1 position

5633

5634

/* TWI_MASTER.STATUS bit masks and bit positions */

5635

5636

5637

#define TWI_MASTER_RIF_bm 0x80 // Read Interrupt Flag bit mask

5638

#define TWI_MASTER_RIF_bp 7 // Read Interrupt Flag bit position

5639

#define TWI_MASTER_WIF_bm 0x40 // Write Interrupt Flag bit mask

5640

#define TWI_MASTER_WIF_bp 6 // Write Interrupt Flag bit position

5641

#define TWI_MASTER_CLKHOLD_bm 0x20 // Clock Hold bit mask

5642

#define TWI_MASTER_CLKHOLD_bp 5 // Clock Hold bit position

5643

#define TWI_MASTER_RXACK_bm 0x10 // Received Acknowledge bit mask

5644

#define TWI_MASTER_RXACK_bp 4 // Received Acknowledge bit position

5645

#define TWI_MASTER_ARBLOST_bm 0x08 // Arbitration Lost bit mask

5646

#define TWI_MASTER_ARBLOST_bp 3 // Arbitration Lost bit position

5647

#define TWI_MASTER_BUSERR_bm 0x04 // Bus Error bit mask

5648

#define TWI_MASTER_BUSERR_bp 2 // Bus Error bit position

5649

#define TWI_MASTER_BUSSTATE_gm 0x03 // Bus State group mask

5650

#define TWI_MASTER_BUSSTATE_bp 0 // Bus State group position

5651

5652

#define TWI_MASTER_BUSSTATE0_bm (1<<0) // Bus State bit 0 mask

5653

#define TWI_MASTER_BUSSTATE0_bp 0 // Bus State bit 0 position

5654

#define TWI_MASTER_BUSSTATE1_bm (1<<1) // Bus State bit 1 mask

5655

#define TWI_MASTER_BUSSTATE1_bp 1 // Bus State bit 1 position

5656

5657

/* TWI_SLAVE.CTRLA bit masks and bit positions */

5658

5659

5660

#define TWI_SLAVE_INTLVL_gm 0xC0 // Interrupt Level group mask

5661

#define TWI_SLAVE_INTLVL_bp 6 // Interrupt Level group position

5662

5663

#define TWI_SLAVE_INTLVL0_bm (1<<6) // Interrupt Level bit 0 mask

5664

#define TWI_SLAVE_INTLVL0_bp 6 // Interrupt Level bit 0 position

5665

#define TWI_SLAVE_INTLVL1_bm (1<<7) // Interrupt Level bit 1 mask

5666

#define TWI_SLAVE_INTLVL1_bp 7 // Interrupt Level bit 1 position

5667

#define TWI_SLAVE_DIEN_bm 0x20 // Data Interrupt Enable bit mask

5668

#define TWI_SLAVE_DIEN_bp 5 // Data Interrupt Enable bit position

5669

#define TWI_SLAVE_APIEN_bm 0x10 // Address/Stop Interrupt Enable bit mask

5670

#define TWI_SLAVE_APIEN_bp 4 // Address/Stop Interrupt Enable bit position

5671

#define TWI_SLAVE_ENABLE_bm 0x08 // Enable TWI Slave bit mask

5672

#define TWI_SLAVE_ENABLE_bp 3 // Enable TWI Slave bit position

5673

#define TWI_SLAVE_PIEN_bm 0x04 // Stop Interrupt Enable bit mask

5674

#define TWI_SLAVE_PIEN_bp 2 // Stop Interrupt Enable bit position

5675

#define TWI_SLAVE_PMEN_bm 0x02 // Promiscuous Mode Enable bit mask

5676

#define TWI_SLAVE_PMEN_bp 1 // Promiscuous Mode Enable bit position

5677

#define TWI_SLAVE_SMEN_bm 0x01 // Smart Mode Enable bit mask

5678

#define TWI_SLAVE_SMEN_bp 0 // Smart Mode Enable bit position

5679

5680

/* TWI_SLAVE.CTRLB bit masks and bit positions */

5681

5682

5683

#define TWI_SLAVE_ACKACT_bm 0x04 // Acknowledge Action bit mask

5684

#define TWI_SLAVE_ACKACT_bp 2 // Acknowledge Action bit position

5685

#define TWI_SLAVE_CMD_gm 0x03 // Command group mask

5686

#define TWI_SLAVE_CMD_bp 0 // Command group position

5687

5688

#define TWI_SLAVE_CMD0_bm (1<<0) // Command bit 0 mask

5689

#define TWI_SLAVE_CMD0_bp 0 // Command bit 0 position

5690

#define TWI_SLAVE_CMD1_bm (1<<1) // Command bit 1 mask

5691

#define TWI_SLAVE_CMD1_bp 1 // Command bit 1 position

5692

5693

/* TWI_SLAVE.STATUS bit masks and bit positions */

5694

5695

5696

#define TWI_SLAVE_DIF_bm 0x80 // Data Interrupt Flag bit mask

5697

#define TWI_SLAVE_DIF_bp 7 // Data Interrupt Flag bit position

5698

#define TWI_SLAVE_APIF_bm 0x40 // Address/Stop Interrupt Flag bit mask

5699

#define TWI_SLAVE_APIF_bp 6 // Address/Stop Interrupt Flag bit position

5700

#define TWI_SLAVE_CLKHOLD_bm 0x20 // Clock Hold bit mask

5701

#define TWI_SLAVE_CLKHOLD_bp 5 // Clock Hold bit position

5702

#define TWI_SLAVE_RXACK_bm 0x10 // Received Acknowledge bit mask

5703

#define TWI_SLAVE_RXACK_bp 4 // Received Acknowledge bit position

5704

#define TWI_SLAVE_COLL_bm 0x08 // Collision bit mask

5705

#define TWI_SLAVE_COLL_bp 3 // Collision bit position

5706

#define TWI_SLAVE_BUSERR_bm 0x04 // Bus Error bit mask

5707

#define TWI_SLAVE_BUSERR_bp 2 // Bus Error bit position

5708

#define TWI_SLAVE_DIR_bm 0x02 // Read/Write Direction bit mask

5709

#define TWI_SLAVE_DIR_bp 1 // Read/Write Direction bit position

5710

#define TWI_SLAVE_AP_bm 0x01 // Slave Address or Stop bit mask

5711

#define TWI_SLAVE_AP_bp 0 // Slave Address or Stop bit position

5712

5713

/* TWI.CTRL bit masks and bit positions */

5714

5715

5716

#define TWI_SDAHOLD_bm 0x02 // SDA Hold Time Enable bit mask

5717

#define TWI_SDAHOLD_bp 1 // SDA Hold Time Enable bit position

5718

#define TWI_EDIEN_bm 0x01 // External Driver Interface Enable bit mask

5719

#define TWI_EDIEN_bp 0 // External Driver Interface Enable bit position

5720

5721

#if !defined (__ASSEMBLER__)

5722

/* Master Interrupt Level */

5723

typedef enum TWI_MASTER_INTLVL_enum

5724

{

5725

TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */

5726

TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */

5727

TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */

5728

TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */

5729

} TWI_MASTER_INTLVL_t;

5730

#endif /* !defined (__ASSEMBLER__) */

5731

5732

#if !defined (__ASSEMBLER__)

5733

/* Inactive Timeout */

5734

typedef enum TWI_MASTER_TIMEOUT_enum

5735

{

5736

TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */

5737

TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */

5738

TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */

5739

TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */

5740

} TWI_MASTER_TIMEOUT_t;

5741

#endif /* !defined (__ASSEMBLER__) */

5742

5743

#if !defined (__ASSEMBLER__)

5744

/* Master Command */

5745

typedef enum TWI_MASTER_CMD_enum

5746

{

5747

TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */

5748

TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */

5749

TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */

5750

TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */

5751

} TWI_MASTER_CMD_t;

5752

#endif /* !defined (__ASSEMBLER__) */

5753

5754

#if !defined (__ASSEMBLER__)

5755

/* Master Bus State */

5756

typedef enum TWI_MASTER_BUSSTATE_enum

5757

{

5758

TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */

5759

TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */

5760

TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */

5761

TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */

5762

} TWI_MASTER_BUSSTATE_t;

5763

#endif /* !defined (__ASSEMBLER__) */

5764

5765

#if !defined (__ASSEMBLER__)

5766

/* Slave Interrupt Level */

5767

typedef enum TWI_SLAVE_INTLVL_enum

5768

{

5769

TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */

5770

TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */

5771

TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */

5772

TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */

5773

} TWI_SLAVE_INTLVL_t;

5774

#endif /* !defined (__ASSEMBLER__) */

5775

5776

#if !defined (__ASSEMBLER__)

5777

/* Slave Command */

5778

typedef enum TWI_SLAVE_CMD_enum

5779

{

5780

TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */

5781

TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */

5782

TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */

5783

} TWI_SLAVE_CMD_t;

5784

#endif /* !defined (__ASSEMBLER__) */

5785

5786

5787

/*

5788

--------------------------------------------------------------------------

5789

PORT - Port Configuration

5790

--------------------------------------------------------------------------

5791

*/

5792

5793

/* PORTCFG.VPCTRLA bit masks and bit positions */

5794

5795

5796

#define PORTCFG_VP1MAP_gm 0xF0 // Virtual Port 1 Mapping group mask

5797

#define PORTCFG_VP1MAP_bp 4 // Virtual Port 1 Mapping group position

5798

5799

#define PORTCFG_VP1MAP0_bm (1<<4) // Virtual Port 1 Mapping bit 0 mask

5800

#define PORTCFG_VP1MAP0_bp 4 // Virtual Port 1 Mapping bit 0 position

5801

#define PORTCFG_VP1MAP1_bm (1<<5) // Virtual Port 1 Mapping bit 1 mask

5802

#define PORTCFG_VP1MAP1_bp 5 // Virtual Port 1 Mapping bit 1 position

5803

#define PORTCFG_VP1MAP2_bm (1<<6) // Virtual Port 1 Mapping bit 2 mask

5804

#define PORTCFG_VP1MAP2_bp 6 // Virtual Port 1 Mapping bit 2 position

5805

#define PORTCFG_VP1MAP3_bm (1<<7) // Virtual Port 1 Mapping bit 3 mask

5806

#define PORTCFG_VP1MAP3_bp 7 // Virtual Port 1 Mapping bit 3 position

5807

#define PORTCFG_VP0MAP_gm 0x0F // Virtual Port 0 Mapping group mask

5808

#define PORTCFG_VP0MAP_bp 0 // Virtual Port 0 Mapping group position

5809

5810

#define PORTCFG_VP0MAP0_bm (1<<0) // Virtual Port 0 Mapping bit 0 mask

5811

#define PORTCFG_VP0MAP0_bp 0 // Virtual Port 0 Mapping bit 0 position

5812

#define PORTCFG_VP0MAP1_bm (1<<1) // Virtual Port 0 Mapping bit 1 mask

5813

#define PORTCFG_VP0MAP1_bp 1 // Virtual Port 0 Mapping bit 1 position

5814

#define PORTCFG_VP0MAP2_bm (1<<2) // Virtual Port 0 Mapping bit 2 mask

5815

#define PORTCFG_VP0MAP2_bp 2 // Virtual Port 0 Mapping bit 2 position

5816

#define PORTCFG_VP0MAP3_bm (1<<3) // Virtual Port 0 Mapping bit 3 mask

5817

#define PORTCFG_VP0MAP3_bp 3 // Virtual Port 0 Mapping bit 3 position

5818

5819

/* PORTCFG.VPCTRLB bit masks and bit positions */

5820

5821

5822

#define PORTCFG_VP3MAP_gm 0xF0 // Virtual Port 3 Mapping group mask

5823

#define PORTCFG_VP3MAP_bp 4 // Virtual Port 3 Mapping group position

5824

5825

#define PORTCFG_VP3MAP0_bm (1<<4) // Virtual Port 3 Mapping bit 0 mask

5826

#define PORTCFG_VP3MAP0_bp 4 // Virtual Port 3 Mapping bit 0 position

5827

#define PORTCFG_VP3MAP1_bm (1<<5) // Virtual Port 3 Mapping bit 1 mask

5828

#define PORTCFG_VP3MAP1_bp 5 // Virtual Port 3 Mapping bit 1 position

5829

#define PORTCFG_VP3MAP2_bm (1<<6) // Virtual Port 3 Mapping bit 2 mask

5830

#define PORTCFG_VP3MAP2_bp 6 // Virtual Port 3 Mapping bit 2 position

5831

#define PORTCFG_VP3MAP3_bm (1<<7) // Virtual Port 3 Mapping bit 3 mask

5832

#define PORTCFG_VP3MAP3_bp 7 // Virtual Port 3 Mapping bit 3 position

5833

#define PORTCFG_VP2MAP_gm 0x0F // Virtual Port 2 Mapping group mask

5834

#define PORTCFG_VP2MAP_bp 0 // Virtual Port 2 Mapping group position

5835

5836

#define PORTCFG_VP2MAP0_bm (1<<0) // Virtual Port 2 Mapping bit 0 mask

5837

#define PORTCFG_VP2MAP0_bp 0 // Virtual Port 2 Mapping bit 0 position

5838

#define PORTCFG_VP2MAP1_bm (1<<1) // Virtual Port 2 Mapping bit 1 mask

5839

#define PORTCFG_VP2MAP1_bp 1 // Virtual Port 2 Mapping bit 1 position

5840

#define PORTCFG_VP2MAP2_bm (1<<2) // Virtual Port 2 Mapping bit 2 mask

5841

#define PORTCFG_VP2MAP2_bp 2 // Virtual Port 2 Mapping bit 2 position

5842

#define PORTCFG_VP2MAP3_bm (1<<3) // Virtual Port 2 Mapping bit 3 mask

5843

#define PORTCFG_VP2MAP3_bp 3 // Virtual Port 2 Mapping bit 3 position

5844

5845

/* PORTCFG.CLKEVOUT bit masks and bit positions */

5846

5847

5848

#define PORTCFG_CLKOUT_gm 0x30 // Clock Output Port group mask

5849

#define PORTCFG_CLKOUT_bp 4 // Clock Output Port group position

5850

5851

#define PORTCFG_CLKOUT0_bm (1<<4) // Clock Output Port bit 0 mask

5852

#define PORTCFG_CLKOUT0_bp 4 // Clock Output Port bit 0 position

5853

#define PORTCFG_CLKOUT1_bm (1<<5) // Clock Output Port bit 1 mask

5854

#define PORTCFG_CLKOUT1_bp 5 // Clock Output Port bit 1 position

5855

#define PORTCFG_EVOUT_gm 0x03 // Event Output Port group mask

5856

#define PORTCFG_EVOUT_bp 0 // Event Output Port group position

5857

5858

#define PORTCFG_EVOUT0_bm (1<<0) // Event Output Port bit 0 mask

5859

#define PORTCFG_EVOUT0_bp 0 // Event Output Port bit 0 position

5860

#define PORTCFG_EVOUT1_bm (1<<1) // Event Output Port bit 1 mask

5861

#define PORTCFG_EVOUT1_bp 1 // Event Output Port bit 1 position

5862

5863

/* VPORT.INTFLAGS bit masks and bit positions */

5864

5865

5866

#define VPORT_INT1IF_bm 0x02 // Port Interrupt 1 Flag bit mask

5867

#define VPORT_INT1IF_bp 1 // Port Interrupt 1 Flag bit position

5868

#define VPORT_INT0IF_bm 0x01 // Port Interrupt 0 Flag bit mask

5869

#define VPORT_INT0IF_bp 0 // Port Interrupt 0 Flag bit position

5870

5871

/* PORT.INTCTRL bit masks and bit positions */

5872

5873

5874

#define PORT_INT1LVL_gm 0x0C // Port Interrupt 1 Level group mask

5875

#define PORT_INT1LVL_bp 2 // Port Interrupt 1 Level group position

5876

5877

#define PORT_INT1LVL0_bm (1<<2) // Port Interrupt 1 Level bit 0 mask

5878

#define PORT_INT1LVL0_bp 2 // Port Interrupt 1 Level bit 0 position

5879

#define PORT_INT1LVL1_bm (1<<3) // Port Interrupt 1 Level bit 1 mask

5880

#define PORT_INT1LVL1_bp 3 // Port Interrupt 1 Level bit 1 position

5881

#define PORT_INT0LVL_gm 0x03 // Port Interrupt 0 Level group mask

5882

#define PORT_INT0LVL_bp 0 // Port Interrupt 0 Level group position

5883

5884

#define PORT_INT0LVL0_bm (1<<0) // Port Interrupt 0 Level bit 0 mask

5885

#define PORT_INT0LVL0_bp 0 // Port Interrupt 0 Level bit 0 position

5886

#define PORT_INT0LVL1_bm (1<<1) // Port Interrupt 0 Level bit 1 mask

5887

#define PORT_INT0LVL1_bp 1 // Port Interrupt 0 Level bit 1 position

5888

5889

/* PORT.INTFLAGS bit masks and bit positions */

5890

5891

5892

#define PORT_INT1IF_bm 0x02 // Port Interrupt 1 Flag bit mask

5893

#define PORT_INT1IF_bp 1 // Port Interrupt 1 Flag bit position

5894

#define PORT_INT0IF_bm 0x01 // Port Interrupt 0 Flag bit mask

5895

#define PORT_INT0IF_bp 0 // Port Interrupt 0 Flag bit position

5896

5897

/* PORT.PIN0CTRL bit masks and bit positions */

5898

5899

5900

#define PORT_SRLEN_bm 0x80 // Slew Rate Enable bit mask

5901

#define PORT_SRLEN_bp 7 // Slew Rate Enable bit position

5902

#define PORT_INVEN_bm 0x40 // Inverted I/O Enable bit mask

5903

#define PORT_INVEN_bp 6 // Inverted I/O Enable bit position

5904

#define PORT_OPC_gm 0x38 // Output/Pull Configuration group mask

5905

#define PORT_OPC_bp 3 // Output/Pull Configuration group position

5906

5907

#define PORT_OPC0_bm (1<<3) // Output/Pull Configuration bit 0 mask

5908

#define PORT_OPC0_bp 3 // Output/Pull Configuration bit 0 position

5909

#define PORT_OPC1_bm (1<<4) // Output/Pull Configuration bit 1 mask

5910

#define PORT_OPC1_bp 4 // Output/Pull Configuration bit 1 position

5911

#define PORT_OPC2_bm (1<<5) // Output/Pull Configuration bit 2 mask

5912

#define PORT_OPC2_bp 5 // Output/Pull Configuration bit 2 position

5913

#define PORT_ISC_gm 0x07 // Input/Sense Configuration group mask

5914

#define PORT_ISC_bp 0 // Input/Sense Configuration group position

5915

5916

#define PORT_ISC0_bm (1<<0) // Input/Sense Configuration bit 0 mask

5917

#define PORT_ISC0_bp 0 // Input/Sense Configuration bit 0 position

5918

#define PORT_ISC1_bm (1<<1) // Input/Sense Configuration bit 1 mask

5919

#define PORT_ISC1_bp 1 // Input/Sense Configuration bit 1 position

5920

#define PORT_ISC2_bm (1<<2) // Input/Sense Configuration bit 2 mask

5921

#define PORT_ISC2_bp 2 // Input/Sense Configuration bit 2 position

5922

5923

/* PORT.PIN1CTRL bit masks and bit positions */

5924

5925

5926

/* Masks for SRLEN aready defined */

5927

5928

/* Masks for INVEN aready defined */

5929

5930

/* Masks for OPC aready defined */

5931

5932

/* Masks for ISC aready defined */

5933

5934

5935

/* PORT.PIN2CTRL bit masks and bit positions */

5936

5937

5938

/* Masks for SRLEN aready defined */

5939

5940

/* Masks for INVEN aready defined */

5941

5942

/* Masks for OPC aready defined */

5943

5944

/* Masks for ISC aready defined */

5945

5946

5947

/* PORT.PIN3CTRL bit masks and bit positions */

5948

5949

5950

/* Masks for SRLEN aready defined */

5951

5952

/* Masks for INVEN aready defined */

5953

5954

/* Masks for OPC aready defined */

5955

5956

/* Masks for ISC aready defined */

5957

5958

5959

/* PORT.PIN4CTRL bit masks and bit positions */

5960

5961

5962

/* Masks for SRLEN aready defined */

5963

5964

/* Masks for INVEN aready defined */

5965

5966

/* Masks for OPC aready defined */

5967

5968

/* Masks for ISC aready defined */

5969

5970

5971

/* PORT.PIN5CTRL bit masks and bit positions */

5972

5973

5974

/* Masks for SRLEN aready defined */

5975

5976

/* Masks for INVEN aready defined */

5977

5978

/* Masks for OPC aready defined */

5979

5980

/* Masks for ISC aready defined */

5981

5982

5983

/* PORT.PIN6CTRL bit masks and bit positions */

5984

5985

5986

/* Masks for SRLEN aready defined */

5987

5988

/* Masks for INVEN aready defined */

5989

5990

/* Masks for OPC aready defined */

5991

5992

/* Masks for ISC aready defined */

5993

5994

5995

/* PORT.PIN7CTRL bit masks and bit positions */

5996

5997

5998

/* Masks for SRLEN aready defined */

5999

6000

/* Masks for INVEN aready defined */

6001

6002

/* Masks for OPC aready defined */

6003

6004

/* Masks for ISC aready defined */

6005

6006

6007

#if !defined (__ASSEMBLER__)

6008

/* Virtual Port 0 Mapping */

6009

typedef enum PORTCFG_VP0MAP_enum

6010

{

6011

PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */

6012

PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */

6013

PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */

6014

PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */

6015

PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */

6016

PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */

6017

PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */

6018

PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */

6019

PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */

6020

PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */

6021

PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */

6022

PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */

6023

PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */

6024

PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */

6025

PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */

6026

PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */

6027

} PORTCFG_VP0MAP_t;

6028

#endif /* !defined (__ASSEMBLER__) */

6029

6030

#if !defined (__ASSEMBLER__)

6031

/* Virtual Port 1 Mapping */

6032

typedef enum PORTCFG_VP1MAP_enum

6033

{

6034

PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */

6035

PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */

6036

PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */

6037

PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */

6038

PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */

6039

PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */

6040

PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */

6041

PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */

6042

PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */

6043

PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */

6044

PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */

6045

PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */

6046

PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */

6047

PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */

6048

PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */

6049

PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */

6050

} PORTCFG_VP1MAP_t;

6051

#endif /* !defined (__ASSEMBLER__) */

6052

6053

#if !defined (__ASSEMBLER__)

6054

/* Virtual Port 2 Mapping */

6055

typedef enum PORTCFG_VP2MAP_enum

6056

{

6057

PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */

6058

PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */

6059

PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */

6060

PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */

6061

PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */

6062

PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */

6063

PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */

6064

PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */

6065

PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */

6066

PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */

6067

PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */

6068

PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */

6069

PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */

6070

PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */

6071

PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */

6072

PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */

6073

} PORTCFG_VP2MAP_t;

6074

#endif /* !defined (__ASSEMBLER__) */

6075

6076

#if !defined (__ASSEMBLER__)

6077

/* Virtual Port 3 Mapping */

6078

typedef enum PORTCFG_VP3MAP_enum

6079

{

6080

PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */

6081

PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */

6082

PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */

6083

PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */

6084

PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */

6085

PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */

6086

PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */

6087

PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */

6088

PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */

6089

PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */

6090

PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */

6091

PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */

6092

PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */

6093

PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */

6094

PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */

6095

PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */

6096

} PORTCFG_VP3MAP_t;

6097

#endif /* !defined (__ASSEMBLER__) */

6098

6099

#if !defined (__ASSEMBLER__)

6100

/* Clock Output Port */

6101

typedef enum PORTCFG_CLKOUT_enum

6102

{

6103

PORTCFG_CLKOUT_OFF_gc = (0x00<<4), /* Clock Output Disabled */

6104

PORTCFG_CLKOUT_PC7_gc = (0x01<<4), /* Clock Output on Port C pin 7 */

6105

PORTCFG_CLKOUT_PD7_gc = (0x02<<4), /* Clock Output on Port D pin 7 */

6106

PORTCFG_CLKOUT_PE7_gc = (0x03<<4), /* Clock Output on Port E pin 7 */

6107

} PORTCFG_CLKOUT_t;

6108

#endif /* !defined (__ASSEMBLER__) */

6109

6110

#if !defined (__ASSEMBLER__)

6111

/* Event Output Port */

6112

typedef enum PORTCFG_EVOUT_enum

6113

{

6114

PORTCFG_EVOUT_OFF_gc = (0x00<<0), /* Event Output Disabled */

6115

PORTCFG_EVOUT_PC7_gc = (0x01<<0), /* Event Channel 7 Output on Port C pin 7 */

6116

PORTCFG_EVOUT_PD7_gc = (0x02<<0), /* Event Channel 7 Output on Port D pin 7 */

6117

PORTCFG_EVOUT_PE7_gc = (0x03<<0), /* Event Channel 7 Output on Port E pin 7 */

6118

} PORTCFG_EVOUT_t;

6119

#endif /* !defined (__ASSEMBLER__) */

6120

6121

#if !defined (__ASSEMBLER__)

6122

/* Port Interrupt 0 Level */

6123

typedef enum PORT_INT0LVL_enum

6124

{

6125

PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */

6126

PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */

6127

PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */

6128

PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */

6129

} PORT_INT0LVL_t;

6130

#endif /* !defined (__ASSEMBLER__) */

6131

6132

#if !defined (__ASSEMBLER__)

6133

/* Port Interrupt 1 Level */

6134

typedef enum PORT_INT1LVL_enum

6135

{

6136

PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */

6137

PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */

6138

PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */

6139

PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */

6140

} PORT_INT1LVL_t;

6141

#endif /* !defined (__ASSEMBLER__) */

6142

6143

#if !defined (__ASSEMBLER__)

6144

/* Output/Pull Configuration */

6145

typedef enum PORT_OPC_enum

6146

{

6147

PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */

6148

PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */

6149

PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */

6150

PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */

6151

PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */

6152

PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */

6153

PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */

6154

PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */

6155

} PORT_OPC_t;

6156

#endif /* !defined (__ASSEMBLER__) */

6157

6158

#if !defined (__ASSEMBLER__)

6159

/* Input/Sense Configuration */

6160

typedef enum PORT_ISC_enum

6161

{

6162

PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */

6163

PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */

6164

PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */

6165

PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */

6166

PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */

6167

} PORT_ISC_t;

6168

#endif /* !defined (__ASSEMBLER__) */

6169

6170

6171

/*

6172

--------------------------------------------------------------------------

6173

TC - 16-bit Timer/Counter With PWM

6174

--------------------------------------------------------------------------

6175

*/

6176

6177

/* TC0.CTRLA bit masks and bit positions */

6178

6179

6180

#define TC0_CLKSEL_gm 0x0F // Clock Selection group mask

6181

#define TC0_CLKSEL_bp 0 // Clock Selection group position

6182

6183

#define TC0_CLKSEL0_bm (1<<0) // Clock Selection bit 0 mask

6184

#define TC0_CLKSEL0_bp 0 // Clock Selection bit 0 position

6185

#define TC0_CLKSEL1_bm (1<<1) // Clock Selection bit 1 mask

6186

#define TC0_CLKSEL1_bp 1 // Clock Selection bit 1 position

6187

#define TC0_CLKSEL2_bm (1<<2) // Clock Selection bit 2 mask

6188

#define TC0_CLKSEL2_bp 2 // Clock Selection bit 2 position

6189

#define TC0_CLKSEL3_bm (1<<3) // Clock Selection bit 3 mask

6190

#define TC0_CLKSEL3_bp 3 // Clock Selection bit 3 position

6191

6192

/* TC0.CTRLB bit masks and bit positions */

6193

6194

6195

#define TC0_CCDEN_bm 0x80 // Compare or Capture D Enable bit mask

6196

#define TC0_CCDEN_bp 7 // Compare or Capture D Enable bit position

6197

#define TC0_CCCEN_bm 0x40 // Compare or Capture C Enable bit mask

6198

#define TC0_CCCEN_bp 6 // Compare or Capture C Enable bit position

6199

#define TC0_CCBEN_bm 0x20 // Compare or Capture B Enable bit mask

6200

#define TC0_CCBEN_bp 5 // Compare or Capture B Enable bit position

6201

#define TC0_CCAEN_bm 0x10 // Compare or Capture A Enable bit mask

6202

#define TC0_CCAEN_bp 4 // Compare or Capture A Enable bit position

6203

#define TC0_WGMODE_gm 0x07 // Waveform generation mode group mask

6204

#define TC0_WGMODE_bp 0 // Waveform generation mode group position

6205

6206

#define TC0_WGMODE0_bm (1<<0) // Waveform generation mode bit 0 mask

6207

#define TC0_WGMODE0_bp 0 // Waveform generation mode bit 0 position

6208

#define TC0_WGMODE1_bm (1<<1) // Waveform generation mode bit 1 mask

6209

#define TC0_WGMODE1_bp 1 // Waveform generation mode bit 1 position

6210

#define TC0_WGMODE2_bm (1<<2) // Waveform generation mode bit 2 mask

6211

#define TC0_WGMODE2_bp 2 // Waveform generation mode bit 2 position

6212

6213

/* TC0.CTRLC bit masks and bit positions */

6214

6215

6216

#define TC0_CMPD_bm 0x08 // Compare D Output Value bit mask

6217

#define TC0_CMPD_bp 3 // Compare D Output Value bit position

6218

#define TC0_CMPC_bm 0x04 // Compare C Output Value bit mask

6219

#define TC0_CMPC_bp 2 // Compare C Output Value bit position

6220

#define TC0_CMPB_bm 0x02 // Compare B Output Value bit mask

6221

#define TC0_CMPB_bp 1 // Compare B Output Value bit position

6222

#define TC0_CMPA_bm 0x01 // Compare A Output Value bit mask

6223

#define TC0_CMPA_bp 0 // Compare A Output Value bit position

6224

6225

/* TC0.CTRLD bit masks and bit positions */

6226

6227

6228

#define TC0_EVACT_gm 0xE0 // Event Action group mask

6229

#define TC0_EVACT_bp 5 // Event Action group position

6230

6231

#define TC0_EVACT0_bm (1<<5) // Event Action bit 0 mask

6232

#define TC0_EVACT0_bp 5 // Event Action bit 0 position

6233

#define TC0_EVACT1_bm (1<<6) // Event Action bit 1 mask

6234

#define TC0_EVACT1_bp 6 // Event Action bit 1 position

6235

#define TC0_EVACT2_bm (1<<7) // Event Action bit 2 mask

6236

#define TC0_EVACT2_bp 7 // Event Action bit 2 position

6237

#define TC0_EVDLY_bm 0x10 // Event Delay bit mask

6238

#define TC0_EVDLY_bp 4 // Event Delay bit position

6239

#define TC0_EVSEL_gm 0x0F // Event Source Select group mask

6240

#define TC0_EVSEL_bp 0 // Event Source Select group position

6241

6242

#define TC0_EVSEL0_bm (1<<0) // Event Source Select bit 0 mask

6243

#define TC0_EVSEL0_bp 0 // Event Source Select bit 0 position

6244

#define TC0_EVSEL1_bm (1<<1) // Event Source Select bit 1 mask

6245

#define TC0_EVSEL1_bp 1 // Event Source Select bit 1 position

6246

#define TC0_EVSEL2_bm (1<<2) // Event Source Select bit 2 mask

6247

#define TC0_EVSEL2_bp 2 // Event Source Select bit 2 position

6248

#define TC0_EVSEL3_bm (1<<3) // Event Source Select bit 3 mask

6249

#define TC0_EVSEL3_bp 3 // Event Source Select bit 3 position

6250

6251

/* TC0.CTRLE bit masks and bit positions */

6252

6253

6254

#define TC0_DTHM_bm 0x02 // Dead Time Hold Mode bit mask

6255

#define TC0_DTHM_bp 1 // Dead Time Hold Mode bit position

6256

#define TC0_BYTEM_bm 0x01 // Byte Mode bit mask

6257

#define TC0_BYTEM_bp 0 // Byte Mode bit position

6258

6259

/* TC0.INTCTRLA bit masks and bit positions */

6260

6261

6262

#define TC0_ERRINTLVL_gm 0x0C // Error Interrupt Level group mask

6263

#define TC0_ERRINTLVL_bp 2 // Error Interrupt Level group position

6264

6265

#define TC0_ERRINTLVL0_bm (1<<2) // Error Interrupt Level bit 0 mask

6266

#define TC0_ERRINTLVL0_bp 2 // Error Interrupt Level bit 0 position

6267

#define TC0_ERRINTLVL1_bm (1<<3) // Error Interrupt Level bit 1 mask

6268

#define TC0_ERRINTLVL1_bp 3 // Error Interrupt Level bit 1 position

6269

#define TC0_OVFINTLVL_gm 0x03 // Overflow interrupt level group mask

6270

#define TC0_OVFINTLVL_bp 0 // Overflow interrupt level group position

6271

6272

#define TC0_OVFINTLVL0_bm (1<<0) // Overflow interrupt level bit 0 mask

6273

#define TC0_OVFINTLVL0_bp 0 // Overflow interrupt level bit 0 position

6274

#define TC0_OVFINTLVL1_bm (1<<1) // Overflow interrupt level bit 1 mask

6275

#define TC0_OVFINTLVL1_bp 1 // Overflow interrupt level bit 1 position

6276

6277

/* TC0.INTCTRLB bit masks and bit positions */

6278

6279

6280

#define TC0_CCDINTLVL_gm 0xC0 // Compare or Capture D Interrupt Level group mask

6281

#define TC0_CCDINTLVL_bp 6 // Compare or Capture D Interrupt Level group position

6282

6283

#define TC0_CCDINTLVL0_bm (1<<6) // Compare or Capture D Interrupt Level bit 0 mask

6284

#define TC0_CCDINTLVL0_bp 6 // Compare or Capture D Interrupt Level bit 0 position

6285

#define TC0_CCDINTLVL1_bm (1<<7) // Compare or Capture D Interrupt Level bit 1 mask

6286

#define TC0_CCDINTLVL1_bp 7 // Compare or Capture D Interrupt Level bit 1 position

6287

#define TC0_CCCINTLVL_gm 0x30 // Compare or Capture C Interrupt Level group mask

6288

#define TC0_CCCINTLVL_bp 4 // Compare or Capture C Interrupt Level group position

6289

6290

#define TC0_CCCINTLVL0_bm (1<<4) // Compare or Capture C Interrupt Level bit 0 mask

6291

#define TC0_CCCINTLVL0_bp 4 // Compare or Capture C Interrupt Level bit 0 position

6292

#define TC0_CCCINTLVL1_bm (1<<5) // Compare or Capture C Interrupt Level bit 1 mask

6293

#define TC0_CCCINTLVL1_bp 5 // Compare or Capture C Interrupt Level bit 1 position

6294

#define TC0_CCBINTLVL_gm 0x0C // Compare or Capture B Interrupt Level group mask

6295

#define TC0_CCBINTLVL_bp 2 // Compare or Capture B Interrupt Level group position

6296

6297

#define TC0_CCBINTLVL0_bm (1<<2) // Compare or Capture B Interrupt Level bit 0 mask

6298

#define TC0_CCBINTLVL0_bp 2 // Compare or Capture B Interrupt Level bit 0 position

6299

#define TC0_CCBINTLVL1_bm (1<<3) // Compare or Capture B Interrupt Level bit 1 mask

6300

#define TC0_CCBINTLVL1_bp 3 // Compare or Capture B Interrupt Level bit 1 position

6301

#define TC0_CCAINTLVL_gm 0x03 // Compare or Capture A Interrupt Level group mask

6302

#define TC0_CCAINTLVL_bp 0 // Compare or Capture A Interrupt Level group position

6303

6304

#define TC0_CCAINTLVL0_bm (1<<0) // Compare or Capture A Interrupt Level bit 0 mask

6305

#define TC0_CCAINTLVL0_bp 0 // Compare or Capture A Interrupt Level bit 0 position

6306

#define TC0_CCAINTLVL1_bm (1<<1) // Compare or Capture A Interrupt Level bit 1 mask

6307

#define TC0_CCAINTLVL1_bp 1 // Compare or Capture A Interrupt Level bit 1 position

6308

6309

/* TC0.CTRLFCLR bit masks and bit positions */

6310

6311

6312

#define TC0_CMD_gm 0x0C // Command group mask

6313

#define TC0_CMD_bp 2 // Command group position

6314

6315

#define TC0_CMD0_bm (1<<2) // Command bit 0 mask

6316

#define TC0_CMD0_bp 2 // Command bit 0 position

6317

#define TC0_CMD1_bm (1<<3) // Command bit 1 mask

6318

#define TC0_CMD1_bp 3 // Command bit 1 position

6319

#define TC0_LUPD_bm 0x02 // Lock Update bit mask

6320

#define TC0_LUPD_bp 1 // Lock Update bit position

6321

#define TC0_DIR_bm 0x01 // Direction bit mask

6322

#define TC0_DIR_bp 0 // Direction bit position

6323

6324

/* TC0.CTRLFSET bit masks and bit positions */

6325

6326

6327

/* Masks for CMD aready defined */

6328

6329

/* Masks for LUPD aready defined */

6330

6331

/* Masks for DIR aready defined */

6332

6333

6334

/* TC0.CTRLGCLR bit masks and bit positions */

6335

6336

6337

#define TC0_CCDBV_bm 0x10 // Compare or Capture D Buffer Valid bit mask

6338

#define TC0_CCDBV_bp 4 // Compare or Capture D Buffer Valid bit position

6339

#define TC0_CCCBV_bm 0x08 // Compare or Capture C Buffer Valid bit mask

6340

#define TC0_CCCBV_bp 3 // Compare or Capture C Buffer Valid bit position

6341

#define TC0_CCBBV_bm 0x04 // Compare or Capture B Buffer Valid bit mask

6342

#define TC0_CCBBV_bp 2 // Compare or Capture B Buffer Valid bit position

6343

#define TC0_CCABV_bm 0x02 // Compare or Capture A Buffer Valid bit mask

6344

#define TC0_CCABV_bp 1 // Compare or Capture A Buffer Valid bit position

6345

#define TC0_PERBV_bm 0x01 // Period Buffer Valid bit mask

6346

#define TC0_PERBV_bp 0 // Period Buffer Valid bit position

6347

6348

/* TC0.CTRLGSET bit masks and bit positions */

6349

6350

6351

/* Masks for CCDBV aready defined */

6352

6353

/* Masks for CCCBV aready defined */

6354

6355

/* Masks for CCBBV aready defined */

6356

6357

/* Masks for CCABV aready defined */

6358

6359

/* Masks for PERBV aready defined */

6360

6361

6362

/* TC0.INTFLAGS bit masks and bit positions */

6363

6364

6365

#define TC0_CCDIF_bm 0x80 // Compare or Capture D Interrupt Flag bit mask

6366

#define TC0_CCDIF_bp 7 // Compare or Capture D Interrupt Flag bit position

6367

#define TC0_CCCIF_bm 0x40 // Compare or Capture C Interrupt Flag bit mask

6368

#define TC0_CCCIF_bp 6 // Compare or Capture C Interrupt Flag bit position

6369

#define TC0_CCBIF_bm 0x20 // Compare or Capture B Interrupt Flag bit mask

6370

#define TC0_CCBIF_bp 5 // Compare or Capture B Interrupt Flag bit position

6371

#define TC0_CCAIF_bm 0x10 // Compare or Capture A Interrupt Flag bit mask

6372

#define TC0_CCAIF_bp 4 // Compare or Capture A Interrupt Flag bit position

6373

#define TC0_ERRIF_bm 0x02 // Error Interrupt Flag bit mask

6374

#define TC0_ERRIF_bp 1 // Error Interrupt Flag bit position

6375

#define TC0_OVFIF_bm 0x01 // Overflow Interrupt Flag bit mask

6376

#define TC0_OVFIF_bp 0 // Overflow Interrupt Flag bit position

6377

6378

/* TC1.CTRLA bit masks and bit positions */

6379

6380

6381

#define TC1_CLKSEL_gm 0x0F // Clock Selection group mask

6382

#define TC1_CLKSEL_bp 0 // Clock Selection group position

6383

6384

#define TC1_CLKSEL0_bm (1<<0) // Clock Selection bit 0 mask

6385

#define TC1_CLKSEL0_bp 0 // Clock Selection bit 0 position

6386

#define TC1_CLKSEL1_bm (1<<1) // Clock Selection bit 1 mask

6387

#define TC1_CLKSEL1_bp 1 // Clock Selection bit 1 position

6388

#define TC1_CLKSEL2_bm (1<<2) // Clock Selection bit 2 mask

6389

#define TC1_CLKSEL2_bp 2 // Clock Selection bit 2 position

6390

#define TC1_CLKSEL3_bm (1<<3) // Clock Selection bit 3 mask

6391

#define TC1_CLKSEL3_bp 3 // Clock Selection bit 3 position

6392

6393

/* TC1.CTRLB bit masks and bit positions */

6394

6395

6396

#define TC1_CCBEN_bm 0x20 // Compare or Capture B Enable bit mask

6397

#define TC1_CCBEN_bp 5 // Compare or Capture B Enable bit position

6398

#define TC1_CCAEN_bm 0x10 // Compare or Capture A Enable bit mask

6399

#define TC1_CCAEN_bp 4 // Compare or Capture A Enable bit position

6400

#define TC1_WGMODE_gm 0x07 // Waveform generation mode group mask

6401

#define TC1_WGMODE_bp 0 // Waveform generation mode group position

6402

6403

#define TC1_WGMODE0_bm (1<<0) // Waveform generation mode bit 0 mask

6404

#define TC1_WGMODE0_bp 0 // Waveform generation mode bit 0 position

6405

#define TC1_WGMODE1_bm (1<<1) // Waveform generation mode bit 1 mask

6406

#define TC1_WGMODE1_bp 1 // Waveform generation mode bit 1 position

6407

#define TC1_WGMODE2_bm (1<<2) // Waveform generation mode bit 2 mask

6408

#define TC1_WGMODE2_bp 2 // Waveform generation mode bit 2 position

6409

6410

/* TC1.CTRLC bit masks and bit positions */

6411

6412

6413

#define TC1_CMPB_bm 0x02 // Compare B Output Value bit mask

6414

#define TC1_CMPB_bp 1 // Compare B Output Value bit position

6415

#define TC1_CMPA_bm 0x01 // Compare A Output Value bit mask

6416

#define TC1_CMPA_bp 0 // Compare A Output Value bit position

6417

6418

/* TC1.CTRLD bit masks and bit positions */

6419

6420

6421

#define TC1_EVACT_gm 0xE0 // Event Action group mask

6422

#define TC1_EVACT_bp 5 // Event Action group position

6423

6424

#define TC1_EVACT0_bm (1<<5) // Event Action bit 0 mask

6425

#define TC1_EVACT0_bp 5 // Event Action bit 0 position

6426

#define TC1_EVACT1_bm (1<<6) // Event Action bit 1 mask

6427

#define TC1_EVACT1_bp 6 // Event Action bit 1 position

6428

#define TC1_EVACT2_bm (1<<7) // Event Action bit 2 mask

6429

#define TC1_EVACT2_bp 7 // Event Action bit 2 position

6430

#define TC1_EVDLY_bm 0x10 // Event Delay bit mask

6431

#define TC1_EVDLY_bp 4 // Event Delay bit position

6432

#define TC1_EVSEL_gm 0x0F // Event Source Select group mask

6433

#define TC1_EVSEL_bp 0 // Event Source Select group position

6434

6435

#define TC1_EVSEL0_bm (1<<0) // Event Source Select bit 0 mask

6436

#define TC1_EVSEL0_bp 0 // Event Source Select bit 0 position

6437

#define TC1_EVSEL1_bm (1<<1) // Event Source Select bit 1 mask

6438

#define TC1_EVSEL1_bp 1 // Event Source Select bit 1 position

6439

#define TC1_EVSEL2_bm (1<<2) // Event Source Select bit 2 mask

6440

#define TC1_EVSEL2_bp 2 // Event Source Select bit 2 position

6441

#define TC1_EVSEL3_bm (1<<3) // Event Source Select bit 3 mask

6442

#define TC1_EVSEL3_bp 3 // Event Source Select bit 3 position

6443

6444

/* TC1.CTRLE bit masks and bit positions */

6445

6446

6447

#define TC1_DTHM_bm 0x02 // Dead Time Hold Mode bit mask

6448

#define TC1_DTHM_bp 1 // Dead Time Hold Mode bit position

6449

#define TC1_BYTEM_bm 0x01 // Byte Mode bit mask

6450

#define TC1_BYTEM_bp 0 // Byte Mode bit position

6451

6452

/* TC1.INTCTRLA bit masks and bit positions */

6453

6454

6455

#define TC1_ERRINTLVL_gm 0x0C // Error Interrupt Level group mask

6456

#define TC1_ERRINTLVL_bp 2 // Error Interrupt Level group position

6457

6458

#define TC1_ERRINTLVL0_bm (1<<2) // Error Interrupt Level bit 0 mask

6459

#define TC1_ERRINTLVL0_bp 2 // Error Interrupt Level bit 0 position

6460

#define TC1_ERRINTLVL1_bm (1<<3) // Error Interrupt Level bit 1 mask

6461

#define TC1_ERRINTLVL1_bp 3 // Error Interrupt Level bit 1 position

6462

#define TC1_OVFINTLVL_gm 0x03 // Overflow interrupt level group mask

6463

#define TC1_OVFINTLVL_bp 0 // Overflow interrupt level group position

6464

6465

#define TC1_OVFINTLVL0_bm (1<<0) // Overflow interrupt level bit 0 mask

6466

#define TC1_OVFINTLVL0_bp 0 // Overflow interrupt level bit 0 position

6467

#define TC1_OVFINTLVL1_bm (1<<1) // Overflow interrupt level bit 1 mask

6468

#define TC1_OVFINTLVL1_bp 1 // Overflow interrupt level bit 1 position

6469

6470

/* TC1.INTCTRLB bit masks and bit positions */

6471

6472

6473

#define TC1_CCBINTLVL_gm 0x0C // Compare or Capture B Interrupt Level group mask

6474

#define TC1_CCBINTLVL_bp 2 // Compare or Capture B Interrupt Level group position

6475

6476

#define TC1_CCBINTLVL0_bm (1<<2) // Compare or Capture B Interrupt Level bit 0 mask

6477

#define TC1_CCBINTLVL0_bp 2 // Compare or Capture B Interrupt Level bit 0 position

6478

#define TC1_CCBINTLVL1_bm (1<<3) // Compare or Capture B Interrupt Level bit 1 mask

6479

#define TC1_CCBINTLVL1_bp 3 // Compare or Capture B Interrupt Level bit 1 position

6480

#define TC1_CCAINTLVL_gm 0x03 // Compare or Capture A Interrupt Level group mask

6481

#define TC1_CCAINTLVL_bp 0 // Compare or Capture A Interrupt Level group position

6482

6483

#define TC1_CCAINTLVL0_bm (1<<0) // Compare or Capture A Interrupt Level bit 0 mask

6484

#define TC1_CCAINTLVL0_bp 0 // Compare or Capture A Interrupt Level bit 0 position

6485

#define TC1_CCAINTLVL1_bm (1<<1) // Compare or Capture A Interrupt Level bit 1 mask

6486

#define TC1_CCAINTLVL1_bp 1 // Compare or Capture A Interrupt Level bit 1 position

6487

6488

/* TC1.CTRLFCLR bit masks and bit positions */

6489

6490

6491

#define TC1_CMD_gm 0x0C // Command group mask

6492

#define TC1_CMD_bp 2 // Command group position

6493

6494

#define TC1_CMD0_bm (1<<2) // Command bit 0 mask

6495

#define TC1_CMD0_bp 2 // Command bit 0 position

6496

#define TC1_CMD1_bm (1<<3) // Command bit 1 mask

6497

#define TC1_CMD1_bp 3 // Command bit 1 position

6498

#define TC1_LUPD_bm 0x02 // Lock Update bit mask

6499

#define TC1_LUPD_bp 1 // Lock Update bit position

6500

#define TC1_DIR_bm 0x01 // Direction bit mask

6501

#define TC1_DIR_bp 0 // Direction bit position

6502

6503

/* TC1.CTRLFSET bit masks and bit positions */

6504

6505

6506

/* Masks for CMD aready defined */

6507

6508

/* Masks for LUPD aready defined */

6509

6510

/* Masks for DIR aready defined */

6511

6512

6513

/* TC1.CTRLGCLR bit masks and bit positions */

6514

6515

6516

#define TC1_CCBBV_bm 0x04 // Compare or Capture B Buffer Valid bit mask

6517

#define TC1_CCBBV_bp 2 // Compare or Capture B Buffer Valid bit position

6518

#define TC1_CCABV_bm 0x02 // Compare or Capture A Buffer Valid bit mask

6519

#define TC1_CCABV_bp 1 // Compare or Capture A Buffer Valid bit position

6520

#define TC1_PERBV_bm 0x01 // Period Buffer Valid bit mask

6521

#define TC1_PERBV_bp 0 // Period Buffer Valid bit position

6522

6523

/* TC1.CTRLGSET bit masks and bit positions */

6524

6525

6526

/* Masks for CCBBV aready defined */

6527

6528

/* Masks for CCABV aready defined */

6529

6530

/* Masks for PERBV aready defined */

6531

6532

6533

/* TC1.INTFLAGS bit masks and bit positions */

6534

6535

6536

#define TC1_CCBIF_bm 0x20 // Compare or Capture B Interrupt Flag bit mask

6537

#define TC1_CCBIF_bp 5 // Compare or Capture B Interrupt Flag bit position

6538

#define TC1_CCAIF_bm 0x10 // Compare or Capture A Interrupt Flag bit mask

6539

#define TC1_CCAIF_bp 4 // Compare or Capture A Interrupt Flag bit position

6540

#define TC1_ERRIF_bm 0x02 // Error Interrupt Flag bit mask

6541

#define TC1_ERRIF_bp 1 // Error Interrupt Flag bit position

6542

#define TC1_OVFIF_bm 0x01 // Overflow Interrupt Flag bit mask

6543

#define TC1_OVFIF_bp 0 // Overflow Interrupt Flag bit position

6544

6545

/* AWEX.CTRL bit masks and bit positions */

6546

6547

6548

#define AWEX_PGM_bm 0x20 // Pattern Generation Mode bit mask

6549

#define AWEX_PGM_bp 5 // Pattern Generation Mode bit position

6550

#define AWEX_CWCM_bm 0x10 // Common Waveform Channel Mode bit mask

6551

#define AWEX_CWCM_bp 4 // Common Waveform Channel Mode bit position

6552

#define AWEX_DTICCDEN_bm 0x08 // Dead Time Insertion Compare Channel D Enable bit mask

6553

#define AWEX_DTICCDEN_bp 3 // Dead Time Insertion Compare Channel D Enable bit position

6554

#define AWEX_DTICCCEN_bm 0x04 // Dead Time Insertion Compare Channel C Enable bit mask

6555

#define AWEX_DTICCCEN_bp 2 // Dead Time Insertion Compare Channel C Enable bit position

6556

#define AWEX_DTICCBEN_bm 0x02 // Dead Time Insertion Compare Channel B Enable bit mask

6557

#define AWEX_DTICCBEN_bp 1 // Dead Time Insertion Compare Channel B Enable bit position

6558

#define AWEX_DTICCAEN_bm 0x01 // Dead Time Insertion Compare Channel A Enable bit mask

6559

#define AWEX_DTICCAEN_bp 0 // Dead Time Insertion Compare Channel A Enable bit position

6560

6561

/* AWEX.DFCTRL bit masks and bit positions */

6562

6563

6564

#define AWEX_FDDBD_bm 0x10 // Fault Detect on Disable Break Disable bit mask

6565

#define AWEX_FDDBD_bp 4 // Fault Detect on Disable Break Disable bit position

6566

#define AWEX_FDMODE_bm 0x04 // Fault Detect Mode bit mask

6567

#define AWEX_FDMODE_bp 2 // Fault Detect Mode bit position

6568

#define AWEX_FDACT_gm 0x03 // Fault Detect Action group mask

6569

#define AWEX_FDACT_bp 0 // Fault Detect Action group position

6570

6571

#define AWEX_FDACT0_bm (1<<0) // Fault Detect Action bit 0 mask

6572

#define AWEX_FDACT0_bp 0 // Fault Detect Action bit 0 position

6573

#define AWEX_FDACT1_bm (1<<1) // Fault Detect Action bit 1 mask

6574

#define AWEX_FDACT1_bp 1 // Fault Detect Action bit 1 position

6575

6576

/* AWEX.STATUS bit masks and bit positions */

6577

6578

6579

#define AWEX_FDF_bm 0x04 // Fault Detect Flag bit mask

6580

#define AWEX_FDF_bp 2 // Fault Detect Flag bit position

6581

#define AWEX_DTHSBUFV_bm 0x02 // Dead Time High Side Buffer Valid bit mask

6582

#define AWEX_DTHSBUFV_bp 1 // Dead Time High Side Buffer Valid bit position

6583

#define AWEX_DTLSBUFV_bm 0x01 // Dead Time Low Side Buffer Valid bit mask

6584

#define AWEX_DTLSBUFV_bp 0 // Dead Time Low Side Buffer Valid bit position

6585

6586

/* HIRES.CTRL bit masks and bit positions */

6587

6588

6589

#define HIRES_HREN_gm 0x03 // High Resolution Enable group mask

6590

#define HIRES_HREN_bp 0 // High Resolution Enable group position

6591

6592

#define HIRES_HREN0_bm (1<<0) // High Resolution Enable bit 0 mask

6593

#define HIRES_HREN0_bp 0 // High Resolution Enable bit 0 position

6594

#define HIRES_HREN1_bm (1<<1) // High Resolution Enable bit 1 mask

6595

#define HIRES_HREN1_bp 1 // High Resolution Enable bit 1 position

6596

6597

#if !defined (__ASSEMBLER__)

6598

/* Clock Selection */

6599

typedef enum TC_CLKSEL_enum

6600

{

6601

TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */

6602

TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */

6603

TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */

6604

TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */

6605

TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */

6606

TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */

6607

TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */

6608

TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */

6609

TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */

6610

TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */

6611

TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */

6612

TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */

6613

TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */

6614

TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */

6615

TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */

6616

TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */

6617

} TC_CLKSEL_t;

6618

#endif /* !defined (__ASSEMBLER__) */

6619

6620

#if !defined (__ASSEMBLER__)

6621

/* Waveform Generation Mode */

6622

typedef enum TC_WGMODE_enum

6623

{

6624

TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */

6625

TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */

6626

TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */

6627

TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */

6628

TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */

6629

TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */

6630

} TC_WGMODE_t;

6631

#endif /* !defined (__ASSEMBLER__) */

6632

6633

#if !defined (__ASSEMBLER__)

6634

/* Event Action */

6635

typedef enum TC_EVACT_enum

6636

{

6637

TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */

6638

TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */

6639

TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */

6640

TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */

6641

TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */

6642

TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */

6643

TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */

6644

} TC_EVACT_t;

6645

#endif /* !defined (__ASSEMBLER__) */

6646

6647

#if !defined (__ASSEMBLER__)

6648

/* Event Selection */

6649

typedef enum TC_EVSEL_enum

6650

{

6651

TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */

6652

TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */

6653

TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */

6654

TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */

6655

TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */

6656

TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */

6657

TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */

6658

TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */

6659

TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */

6660

} TC_EVSEL_t;

6661

#endif /* !defined (__ASSEMBLER__) */

6662

6663

#if !defined (__ASSEMBLER__)

6664

/* Error Interrupt Level */

6665

typedef enum TC_ERRINTLVL_enum

6666

{

6667

TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */

6668

TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */

6669

TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */

6670

TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */

6671

} TC_ERRINTLVL_t;

6672

#endif /* !defined (__ASSEMBLER__) */

6673

6674

#if !defined (__ASSEMBLER__)

6675

/* Overflow Interrupt Level */

6676

typedef enum TC_OVFINTLVL_enum

6677

{

6678

TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */

6679

TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */

6680

TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */

6681

TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */

6682

} TC_OVFINTLVL_t;

6683

#endif /* !defined (__ASSEMBLER__) */

6684

6685

#if !defined (__ASSEMBLER__)

6686

/* Compare or Capture D Interrupt Level */

6687

typedef enum TC_CCDINTLVL_enum

6688

{

6689

TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */

6690

TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */

6691

TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */

6692

TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */

6693

} TC_CCDINTLVL_t;

6694

#endif /* !defined (__ASSEMBLER__) */

6695

6696

#if !defined (__ASSEMBLER__)

6697

/* Compare or Capture C Interrupt Level */

6698

typedef enum TC_CCCINTLVL_enum

6699

{

6700

TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */

6701

TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */

6702

TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */

6703

TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */

6704

} TC_CCCINTLVL_t;

6705

#endif /* !defined (__ASSEMBLER__) */

6706

6707

#if !defined (__ASSEMBLER__)

6708

/* Compare or Capture B Interrupt Level */

6709

typedef enum TC_CCBINTLVL_enum

6710

{

6711

TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */

6712

TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */

6713

TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */

6714

TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */

6715

} TC_CCBINTLVL_t;

6716

#endif /* !defined (__ASSEMBLER__) */

6717

6718

#if !defined (__ASSEMBLER__)

6719

/* Compare or Capture A Interrupt Level */

6720

typedef enum TC_CCAINTLVL_enum

6721

{

6722

TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */

6723

TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */

6724

TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */

6725

TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */

6726

} TC_CCAINTLVL_t;

6727

#endif /* !defined (__ASSEMBLER__) */

6728

6729

#if !defined (__ASSEMBLER__)

6730

/* Timer/Counter Command */

6731

typedef enum TC_CMD_enum

6732

{

6733

TC_CMD_NONE_gc = (0x00<<2), /* No Command */

6734

TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */

6735

TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */

6736

TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */

6737

} TC_CMD_t;

6738

#endif /* !defined (__ASSEMBLER__) */

6739

6740

#if !defined (__ASSEMBLER__)

6741

/* Fault Detect Action */

6742

typedef enum AWEX_FDACT_enum

6743

{

6744

AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */

6745

AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */

6746

AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */

6747

} AWEX_FDACT_t;

6748

#endif /* !defined (__ASSEMBLER__) */

6749

6750

#if !defined (__ASSEMBLER__)

6751

/* High Resolution Enable */

6752

typedef enum HIRES_HREN_enum

6753

{

6754

HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */

6755

HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */

6756

HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */

6757

HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */

6758

} HIRES_HREN_t;

6759

#endif /* !defined (__ASSEMBLER__) */

6760

6761

6762

/*

6763

--------------------------------------------------------------------------

6764

USART - Universal Asynchronous Receiver-Transmitter

6765

--------------------------------------------------------------------------

6766

*/

6767

6768

/* USART.STATUS bit masks and bit positions */

6769

6770

6771

#define USART_RXCIF_bm 0x80 // Receive Interrupt Flag bit mask

6772

#define USART_RXCIF_bp 7 // Receive Interrupt Flag bit position

6773

#define USART_TXCIF_bm 0x40 // Transmit Interrupt Flag bit mask

6774

#define USART_TXCIF_bp 6 // Transmit Interrupt Flag bit position

6775

#define USART_DREIF_bm 0x20 // Data Register Empty Flag bit mask

6776

#define USART_DREIF_bp 5 // Data Register Empty Flag bit position

6777

#define USART_FERR_bm 0x10 // Frame Error bit mask

6778

#define USART_FERR_bp 4 // Frame Error bit position

6779

#define USART_BUFOVF_bm 0x08 // Buffer Overflow bit mask

6780

#define USART_BUFOVF_bp 3 // Buffer Overflow bit position

6781

#define USART_PERR_bm 0x04 // Parity Error bit mask

6782

#define USART_PERR_bp 2 // Parity Error bit position

6783

#define USART_RXB8_bm 0x01 // Receive Bit 8 bit mask

6784

#define USART_RXB8_bp 0 // Receive Bit 8 bit position

6785

6786

/* USART.CTRLA bit masks and bit positions */

6787

6788

6789

#define USART_RXCINTLVL_gm 0x30 // Receive Interrupt Level group mask

6790

#define USART_RXCINTLVL_bp 4 // Receive Interrupt Level group position

6791

6792

#define USART_RXCINTLVL0_bm (1<<4) // Receive Interrupt Level bit 0 mask

6793

#define USART_RXCINTLVL0_bp 4 // Receive Interrupt Level bit 0 position

6794

#define USART_RXCINTLVL1_bm (1<<5) // Receive Interrupt Level bit 1 mask

6795

#define USART_RXCINTLVL1_bp 5 // Receive Interrupt Level bit 1 position

6796

#define USART_TXCINTLVL_gm 0x0C // Transmit Interrupt Level group mask

6797

#define USART_TXCINTLVL_bp 2 // Transmit Interrupt Level group position

6798

6799

#define USART_TXCINTLVL0_bm (1<<2) // Transmit Interrupt Level bit 0 mask

6800

#define USART_TXCINTLVL0_bp 2 // Transmit Interrupt Level bit 0 position

6801

#define USART_TXCINTLVL1_bm (1<<3) // Transmit Interrupt Level bit 1 mask

6802

#define USART_TXCINTLVL1_bp 3 // Transmit Interrupt Level bit 1 position

6803

#define USART_DREINTLVL_gm 0x03 // Data Register Empty Interrupt Level group mask

6804

#define USART_DREINTLVL_bp 0 // Data Register Empty Interrupt Level group position

6805

6806

#define USART_DREINTLVL0_bm (1<<0) // Data Register Empty Interrupt Level bit 0 mask

6807

#define USART_DREINTLVL0_bp 0 // Data Register Empty Interrupt Level bit 0 position

6808

#define USART_DREINTLVL1_bm (1<<1) // Data Register Empty Interrupt Level bit 1 mask

6809

#define USART_DREINTLVL1_bp 1 // Data Register Empty Interrupt Level bit 1 position

6810

6811

/* USART.CTRLB bit masks and bit positions */

6812

6813

6814

#define USART_RXEN_bm 0x10 // Receiver Enable bit mask

6815

#define USART_RXEN_bp 4 // Receiver Enable bit position

6816

#define USART_TXEN_bm 0x08 // Transmitter Enable bit mask

6817

#define USART_TXEN_bp 3 // Transmitter Enable bit position

6818

#define USART_CLK2X_bm 0x04 // Double transmission speed bit mask

6819

#define USART_CLK2X_bp 2 // Double transmission speed bit position

6820

#define USART_MPCM_bm 0x02 // Multi-processor Communication Mode bit mask

6821

#define USART_MPCM_bp 1 // Multi-processor Communication Mode bit position

6822

#define USART_TXB8_bm 0x01 // Transmit bit 8 bit mask

6823

#define USART_TXB8_bp 0 // Transmit bit 8 bit position

6824

6825

/* USART.CTRLC bit masks and bit positions */

6826

6827

6828

#define USART_CMODE_gm 0xC0 // Communication Mode group mask

6829

#define USART_CMODE_bp 6 // Communication Mode group position

6830

6831

#define USART_CMODE0_bm (1<<6) // Communication Mode bit 0 mask

6832

#define USART_CMODE0_bp 6 // Communication Mode bit 0 position

6833

#define USART_CMODE1_bm (1<<7) // Communication Mode bit 1 mask

6834

#define USART_CMODE1_bp 7 // Communication Mode bit 1 position

6835

#define USART_PMODE_gm 0x30 // Parity Mode group mask

6836

#define USART_PMODE_bp 4 // Parity Mode group position

6837

6838

#define USART_PMODE0_bm (1<<4) // Parity Mode bit 0 mask

6839

#define USART_PMODE0_bp 4 // Parity Mode bit 0 position

6840

#define USART_PMODE1_bm (1<<5) // Parity Mode bit 1 mask

6841

#define USART_PMODE1_bp 5 // Parity Mode bit 1 position

6842

#define USART_SBMODE_bm 0x08 // Stop Bit Mode bit mask

6843

#define USART_SBMODE_bp 3 // Stop Bit Mode bit position

6844

#define USART_CHSIZE_gm 0x07 // Character Size group mask

6845

#define USART_CHSIZE_bp 0 // Character Size group position

6846

6847

#define USART_CHSIZE0_bm (1<<0) // Character Size bit 0 mask

6848

#define USART_CHSIZE0_bp 0 // Character Size bit 0 position

6849

#define USART_CHSIZE1_bm (1<<1) // Character Size bit 1 mask

6850

#define USART_CHSIZE1_bp 1 // Character Size bit 1 position

6851

#define USART_CHSIZE2_bm (1<<2) // Character Size bit 2 mask

6852

#define USART_CHSIZE2_bp 2 // Character Size bit 2 position

6853

6854

/* USART.BAUDCTRLA bit masks and bit positions */

6855

6856

6857

#define USART_BSEL_gm 0xFF // Baud Rate Selection Bits [7:0] group mask

6858

#define USART_BSEL_bp 0 // Baud Rate Selection Bits [7:0] group position

6859

6860

#define USART_BSEL0_bm (1<<0) // Baud Rate Selection Bits [7:0] bit 0 mask

6861

#define USART_BSEL0_bp 0 // Baud Rate Selection Bits [7:0] bit 0 position

6862

#define USART_BSEL1_bm (1<<1) // Baud Rate Selection Bits [7:0] bit 1 mask

6863

#define USART_BSEL1_bp 1 // Baud Rate Selection Bits [7:0] bit 1 position

6864

#define USART_BSEL2_bm (1<<2) // Baud Rate Selection Bits [7:0] bit 2 mask

6865

#define USART_BSEL2_bp 2 // Baud Rate Selection Bits [7:0] bit 2 position

6866

#define USART_BSEL3_bm (1<<3) // Baud Rate Selection Bits [7:0] bit 3 mask

6867

#define USART_BSEL3_bp 3 // Baud Rate Selection Bits [7:0] bit 3 position

6868

#define USART_BSEL4_bm (1<<4) // Baud Rate Selection Bits [7:0] bit 4 mask

6869

#define USART_BSEL4_bp 4 // Baud Rate Selection Bits [7:0] bit 4 position

6870

#define USART_BSEL5_bm (1<<5) // Baud Rate Selection Bits [7:0] bit 5 mask

6871

#define USART_BSEL5_bp 5 // Baud Rate Selection Bits [7:0] bit 5 position

6872

#define USART_BSEL6_bm (1<<6) // Baud Rate Selection Bits [7:0] bit 6 mask

6873

#define USART_BSEL6_bp 6 // Baud Rate Selection Bits [7:0] bit 6 position

6874

#define USART_BSEL7_bm (1<<7) // Baud Rate Selection Bits [7:0] bit 7 mask

6875

#define USART_BSEL7_bp 7 // Baud Rate Selection Bits [7:0] bit 7 position

6876

6877

/* USART.BAUDCTRLB bit masks and bit positions */

6878

6879

6880

#define USART_BSCALE_gm 0xF0 // Baud Rate Scale group mask

6881

#define USART_BSCALE_bp 4 // Baud Rate Scale group position

6882

6883

#define USART_BSCALE0_bm (1<<4) // Baud Rate Scale bit 0 mask

6884

#define USART_BSCALE0_bp 4 // Baud Rate Scale bit 0 position

6885

#define USART_BSCALE1_bm (1<<5) // Baud Rate Scale bit 1 mask

6886

#define USART_BSCALE1_bp 5 // Baud Rate Scale bit 1 position

6887

#define USART_BSCALE2_bm (1<<6) // Baud Rate Scale bit 2 mask

6888

#define USART_BSCALE2_bp 6 // Baud Rate Scale bit 2 position

6889

#define USART_BSCALE3_bm (1<<7) // Baud Rate Scale bit 3 mask

6890

#define USART_BSCALE3_bp 7 // Baud Rate Scale bit 3 position

6891

/* Masks for BSEL aready defined */

6892

6893

6894

#if !defined (__ASSEMBLER__)

6895

/* Receive Complete Interrupt level */

6896

typedef enum USART_RXCINTLVL_enum

6897

{

6898

USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */

6899

USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */

6900

USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */

6901

USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */

6902

} USART_RXCINTLVL_t;

6903

#endif /* !defined (__ASSEMBLER__) */

6904

6905

#if !defined (__ASSEMBLER__)

6906

/* Transmit Complete Interrupt level */

6907

typedef enum USART_TXCINTLVL_enum

6908

{

6909

USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */

6910

USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */

6911

USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */

6912

USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */

6913

} USART_TXCINTLVL_t;

6914

#endif /* !defined (__ASSEMBLER__) */

6915

6916

#if !defined (__ASSEMBLER__)

6917

/* Data Register Empty Interrupt level */

6918

typedef enum USART_DREINTLVL_enum

6919

{

6920

USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */

6921

USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */

6922

USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */

6923

USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */

6924

} USART_DREINTLVL_t;

6925

#endif /* !defined (__ASSEMBLER__) */

6926

6927

#if !defined (__ASSEMBLER__)

6928

/* Character Size */

6929

typedef enum USART_CHSIZE_enum

6930

{

6931

USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */

6932

USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */

6933

USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */

6934

USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */

6935

USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */

6936

} USART_CHSIZE_t;

6937

#endif /* !defined (__ASSEMBLER__) */

6938

6939

#if !defined (__ASSEMBLER__)

6940

/* Communication Mode */

6941

typedef enum USART_CMODE_enum

6942

{

6943

USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */

6944

USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */

6945

USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */

6946

USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */

6947

} USART_CMODE_t;

6948

#endif /* !defined (__ASSEMBLER__) */

6949

6950

#if !defined (__ASSEMBLER__)

6951

/* Parity Mode */

6952

typedef enum USART_PMODE_enum

6953

{

6954

USART_PMODE_DISABLED_gc = (0x00<<0), /* No Parity */

6955

USART_PMODE_EVEN_gc = (0x02<<0), /* Even Parity */

6956

USART_PMODE_ODD_gc = (0x03<<0), /* Odd Parity */

6957

} USART_PMODE_t;

6958

#endif /* !defined (__ASSEMBLER__) */

6959

6960

6961

/*

6962

--------------------------------------------------------------------------

6963

SPI - Serial Peripheral Interface

6964

--------------------------------------------------------------------------

6965

*/

6966

6967

/* SPI.CTRL bit masks and bit positions */

6968

6969

6970

#define SPI_CLK2X_bm 0x80 // TODO: Find documentation on this bit bit mask

6971

#define SPI_CLK2X_bp 7 // TODO: Find documentation on this bit bit position

6972

#define SPI_ENABLE_bm 0x40 // Enable Module bit mask

6973

#define SPI_ENABLE_bp 6 // Enable Module bit position

6974

#define SPI_DORD_bm 0x20 // Data Order Setting bit mask

6975

#define SPI_DORD_bp 5 // Data Order Setting bit position

6976

#define SPI_MASTER_bm 0x10 // Master Operation Enable bit mask

6977

#define SPI_MASTER_bp 4 // Master Operation Enable bit position

6978

#define SPI_MODE_gm 0x0C // SPI Mode group mask

6979

#define SPI_MODE_bp 2 // SPI Mode group position

6980

6981

#define SPI_MODE0_bm (1<<2) // SPI Mode bit 0 mask

6982

#define SPI_MODE0_bp 2 // SPI Mode bit 0 position

6983

#define SPI_MODE1_bm (1<<3) // SPI Mode bit 1 mask

6984

#define SPI_MODE1_bp 3 // SPI Mode bit 1 position

6985

#define SPI_PRESCALER_gm 0x03 // Prescaler group mask

6986

#define SPI_PRESCALER_bp 0 // Prescaler group position

6987

6988

#define SPI_PRESCALER0_bm (1<<0) // Prescaler bit 0 mask

6989

#define SPI_PRESCALER0_bp 0 // Prescaler bit 0 position

6990

#define SPI_PRESCALER1_bm (1<<1) // Prescaler bit 1 mask

6991

#define SPI_PRESCALER1_bp 1 // Prescaler bit 1 position

6992

6993

/* SPI.INTCTRL bit masks and bit positions */

6994

6995

6996

#define SPI_INTLVL_gm 0x03 // Interrupt level group mask

6997

#define SPI_INTLVL_bp 0 // Interrupt level group position

6998

6999

#define SPI_INTLVL0_bm (1<<0) // Interrupt level bit 0 mask

7000

#define SPI_INTLVL0_bp 0 // Interrupt level bit 0 position

7001

#define SPI_INTLVL1_bm (1<<1) // Interrupt level bit 1 mask

7002

#define SPI_INTLVL1_bp 1 // Interrupt level bit 1 position

7003

7004

/* SPI.STATUS bit masks and bit positions */

7005

7006

7007

#define SPI_IF_bm 0x80 // Interrupt Flag bit mask

7008

#define SPI_IF_bp 7 // Interrupt Flag bit position

7009

#define SPI_WRCOL_bm 0x40 // Write Collision bit mask

7010

#define SPI_WRCOL_bp 6 // Write Collision bit position

7011

7012

#if !defined (__ASSEMBLER__)

7013

/* SPI Mode */

7014

typedef enum SPI_MODE_enum

7015

{

7016

SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */

7017

SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */

7018

SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */

7019

SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */

7020

} SPI_MODE_t;

7021

#endif /* !defined (__ASSEMBLER__) */

7022

7023

#if !defined (__ASSEMBLER__)

7024

/* Prescaler setting */

7025

typedef enum SPI_PRESCALER_enum

7026

{

7027

SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */

7028

SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */

7029

SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */

7030

SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */

7031

} SPI_PRESCALER_t;

7032

#endif /* !defined (__ASSEMBLER__) */

7033

7034

#if !defined (__ASSEMBLER__)

7035

/* Interrupt level */

7036

typedef enum SPI_INTLVL_enum

7037

{

7038

SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */

7039

SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */

7040

SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */

7041

SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */

7042

} SPI_INTLVL_t;

7043

#endif /* !defined (__ASSEMBLER__) */

7044

7045

7046

/*

7047

--------------------------------------------------------------------------

7048

IRCOM - IR Communication Module

7049

--------------------------------------------------------------------------

7050

*/

7051

7052

/* IRCOM.CTRL bit masks and bit positions */

7053

7054

7055

#define IRCOM_EVSEL_gm 0x0F // Event Channel Select group mask

7056

#define IRCOM_EVSEL_bp 0 // Event Channel Select group position

7057

7058

#define IRCOM_EVSEL0_bm (1<<0) // Event Channel Select bit 0 mask

7059

#define IRCOM_EVSEL0_bp 0 // Event Channel Select bit 0 position

7060

#define IRCOM_EVSEL1_bm (1<<1) // Event Channel Select bit 1 mask

7061

#define IRCOM_EVSEL1_bp 1 // Event Channel Select bit 1 position

7062

#define IRCOM_EVSEL2_bm (1<<2) // Event Channel Select bit 2 mask

7063

#define IRCOM_EVSEL2_bp 2 // Event Channel Select bit 2 position

7064

#define IRCOM_EVSEL3_bm (1<<3) // Event Channel Select bit 3 mask

7065

#define IRCOM_EVSEL3_bp 3 // Event Channel Select bit 3 position

7066

7067

#if !defined (__ASSEMBLER__)

7068

/* Event Selection */

7069

typedef enum IRDA_EVSEL_enum

7070

{

7071

IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */

7072

IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */

7073

IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */

7074

IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */

7075

IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */

7076

IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */

7077

IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */

7078

IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */

7079

IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */

7080

} IRDA_EVSEL_t;

7081

#endif /* !defined (__ASSEMBLER__) */

7082

7083

7084

/*

7085

--------------------------------------------------------------------------

7086

AES - AES Module

7087

--------------------------------------------------------------------------

7088

*/

7089

7090

/* AES.CTRL bit masks and bit positions */

7091

7092

7093

#define AES_START_bm 0x80 // Start/Run bit mask

7094

#define AES_START_bp 7 // Start/Run bit position

7095

#define AES_AUTO_bm 0x40 // Auto Start Trigger bit mask

7096

#define AES_AUTO_bp 6 // Auto Start Trigger bit position

7097

#define AES_RESET_bm 0x20 // AES Software Reset bit mask

7098

#define AES_RESET_bp 5 // AES Software Reset bit position

7099

#define AES_DECRYPT_bm 0x10 // Decryption / Direction bit mask

7100

#define AES_DECRYPT_bp 4 // Decryption / Direction bit position

7101

#define AES_XOR_bm 0x04 // State XOR Load Enable bit mask

7102

#define AES_XOR_bp 2 // State XOR Load Enable bit position

7103

7104

/* AES.STATUS bit masks and bit positions */

7105

7106

7107

#define AES_ERROR_bm 0x80 // AES Error bit mask

7108

#define AES_ERROR_bp 7 // AES Error bit position

7109

#define AES_SRIF_bm 0x01 // State Ready Interrupt Flag bit mask

7110

#define AES_SRIF_bp 0 // State Ready Interrupt Flag bit position

7111

7112

/* AES.INTCTRL bit masks and bit positions */

7113

7114

7115

#define AES_INTLVL_gm 0x03 // Interrupt level group mask

7116

#define AES_INTLVL_bp 0 // Interrupt level group position

7117

7118

#define AES_INTLVL0_bm (1<<0) // Interrupt level bit 0 mask

7119

#define AES_INTLVL0_bp 0 // Interrupt level bit 0 position

7120

#define AES_INTLVL1_bm (1<<1) // Interrupt level bit 1 mask

7121

#define AES_INTLVL1_bp 1 // Interrupt level bit 1 position

7122

7123

#if !defined (__ASSEMBLER__)

7124

/* Interrupt level */

7125

typedef enum AES_INTLVL_enum

7126

{

7127

AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */

7128

AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */

7129

AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */

7130

AES_INTLVL_HI_gc = (0x03<<0), /* High Level */

7131

} AES_INTLVL_t;

7132

#endif /* !defined (__ASSEMBLER__) */

7133

7134

7135

// Port pins

7136

7137

#define PIN0_bm 0x01

7138

#define PIN0_bp 0

7139

#define PIN1_bm 0x02

7140

#define PIN1_bp 1

7141

#define PIN2_bm 0x04

7142

#define PIN2_bp 2

7143

#define PIN3_bm 0x08

7144

#define PIN3_bp 3

7145

#define PIN4_bm 0x10

7146

#define PIN4_bp 4

7147

#define PIN5_bm 0x20

7148

#define PIN5_bp 5

7149

#define PIN6_bm 0x40

7150

#define PIN6_bp 6

7151

#define PIN7_bm 0x80

7152

#define PIN7_bp 7

7153

7154

7155

/* ========== Interrupt Vector Definitions ========== */

7156

7157

/* OSC interrupt vectors */

7158

#define OSC_XOSCF_vect _VECTOR(1) // External Oscillator Failure Interrupt (NMI)

7159

7160

/* PORTC interrupt vectors */

7161

#define PORTC_INT0_vect _VECTOR(2) // External Interrupt 0

7162

#define PORTC_INT1_vect _VECTOR(3) // External Interrupt 1

7163

7164

/* PORTR interrupt vectors */

7165

#define PORTR_INT0_vect _VECTOR(4) // External Interrupt 0

7166

#define PORTR_INT1_vect _VECTOR(5) // External Interrupt 1

7167

7168

/* DMA interrupt vectors */

7169

#define DMA_CH0_vect _VECTOR(6) // Channel 0 Interrupt

7170

#define DMA_CH1_vect _VECTOR(7) // Channel 1 Interrupt

7171

#define DMA_CH2_vect _VECTOR(8) // Channel 2 Interrupt

7172

#define DMA_CH3_vect _VECTOR(9) // Channel 3 Interrupt

7173

7174

/* RTC interrupt vectors */

7175

#define RTC_OVF_vect _VECTOR(10) // Overflow Interrupt

7176

#define RTC_COMP_vect _VECTOR(11) // Compare Interrupt

7177

7178

/* TWIC interrupt vectors */

7179

#define TWIC_TWIS_vect _VECTOR(12) // TWI Slave Interrupt

7180

#define TWIC_TWIM_vect _VECTOR(13) // TWI Master Interrupt

7181

7182

/* TCC0 interrupt vectors */

7183

#define TCC0_OVF_vect _VECTOR(14) // Overflow Interrupt

7184

#define TCC0_ERR_vect _VECTOR(15) // Error Interrupt

7185

#define TCC0_CCA_vect _VECTOR(16) // Compare or Capture A Interrupt

7186

#define TCC0_CCB_vect _VECTOR(17) // Compare or Capture B Interrupt

7187

#define TCC0_CCC_vect _VECTOR(18) // Compare or Capture C Interrupt

7188

#define TCC0_CCD_vect _VECTOR(19) // Compare or Capture D Interrupt

7189

7190

/* TCC1 interrupt vectors */

7191

#define TCC1_OVF_vect _VECTOR(20) // Overflow Interrupt

7192

#define TCC1_ERR_vect _VECTOR(21) // Error Interrupt

7193

#define TCC1_CCA_vect _VECTOR(22) // Compare or Capture A Interrupt

7194

#define TCC1_CCB_vect _VECTOR(23) // Compare or Capture B Interrupt

7195

7196

/* SPIC interrupt vectors */

7197

#define SPIC_INT_vect _VECTOR(24) // SPI Interrupt

7198

7199

/* USARTC0 interrupt vectors */

7200

#define USARTC0_RXC_vect _VECTOR(25) // Reception Complete Interrupt

7201

#define USARTC0_DRE_vect _VECTOR(26) // Data Register Empty Interrupt

7202

#define USARTC0_TXC_vect _VECTOR(27) // Transmission Complete Interrupt

7203

7204

/* USARTC1 interrupt vectors */

7205

#define USARTC1_RXC_vect _VECTOR(28) // Reception Complete Interrupt

7206

#define USARTC1_DRE_vect _VECTOR(29) // Data Register Empty Interrupt

7207

#define USARTC1_TXC_vect _VECTOR(30) // Transmission Complete Interrupt

7208

7209

/* AES interrupt vectors */

7210

#define AES_INT_vect _VECTOR(31) // AES Interrupt

7211

7212

/* NVM interrupt vectors */

7213

#define NVM_EE_vect _VECTOR(32) // EE Interrupt

7214

#define NVM_SPM_vect _VECTOR(33) // SPM Interrupt

7215

7216

/* PORTB interrupt vectors */

7217

#define PORTB_INT0_vect _VECTOR(34) // External Interrupt 0

7218

#define PORTB_INT1_vect _VECTOR(35) // External Interrupt 1

7219

7220

/* ACB interrupt vectors */

7221

#define ACB_ACW_vect _VECTOR(38) // ACW Window Mode Interrupt

7222

#define ACB_AC1_vect _VECTOR(37) // AC1 Interrupt

7223

#define ACB_AC0_vect _VECTOR(36) // AC0 Interrupt

7224

7225

/* ADCB interrupt vectors */

7226

#define ADCB_CH0_vect _VECTOR(39) // Interrupt 0

7227

#define ADCB_CH1_vect _VECTOR(40) // Interrupt 1

7228

#define ADCB_CH2_vect _VECTOR(41) // Interrupt 2

7229

#define ADCB_CH3_vect _VECTOR(42) // Interrupt 3

7230

7231

/* PORTE interrupt vectors */

7232

#define PORTE_INT0_vect _VECTOR(43) // External Interrupt 0

7233

#define PORTE_INT1_vect _VECTOR(44) // External Interrupt 1

7234

7235

/* TWIE interrupt vectors */

7236

#define TWIE_TWIS_vect _VECTOR(45) // TWI Slave Interrupt

7237

#define TWIE_TWIM_vect _VECTOR(46) // TWI Master Interrupt

7238

7239

/* TCE0 interrupt vectors */

7240

#define TCE0_OVF_vect _VECTOR(47) // Overflow Interrupt

7241

#define TCE0_ERR_vect _VECTOR(48) // Error Interrupt

7242

#define TCE0_CCA_vect _VECTOR(49) // Compare or Capture A Interrupt

7243

#define TCE0_CCB_vect _VECTOR(50) // Compare or Capture B Interrupt

7244

#define TCE0_CCC_vect _VECTOR(51) // Compare or Capture C Interrupt

7245

#define TCE0_CCD_vect _VECTOR(52) // Compare or Capture D Interrupt

7246

7247

/* TCE1 interrupt vectors */

7248

#define TCE1_OVF_vect _VECTOR(53) // Overflow Interrupt

7249

#define TCE1_ERR_vect _VECTOR(54) // Error Interrupt

7250

#define TCE1_CCA_vect _VECTOR(55) // Compare or Capture A Interrupt

7251

#define TCE1_CCB_vect _VECTOR(56) // Compare or Capture B Interrupt

7252

7253

/* SPIE interrupt vectors */

7254

#define SPIE_INT_vect _VECTOR(57) // SPI Interrupt

7255

7256

/* USARTE0 interrupt vectors */

7257

#define USARTE0_RXC_vect _VECTOR(58) // Reception Complete Interrupt

7258

#define USARTE0_DRE_vect _VECTOR(59) // Data Register Empty Interrupt

7259

#define USARTE0_TXC_vect _VECTOR(60) // Transmission Complete Interrupt

7260

7261

/* USARTE1 interrupt vectors */

7262

#define USARTE1_RXC_vect _VECTOR(61) // Reception Complete Interrupt

7263

#define USARTE1_DRE_vect _VECTOR(62) // Data Register Empty Interrupt

7264

#define USARTE1_TXC_vect _VECTOR(63) // Transmission Complete Interrupt

7265

7266

/* PORTD interrupt vectors */

7267

#define PORTD_INT0_vect _VECTOR(64) // External Interrupt 0

7268

#define PORTD_INT1_vect _VECTOR(65) // External Interrupt 1

7269

7270

/* PORTA interrupt vectors */

7271

#define PORTA_INT0_vect _VECTOR(66) // External Interrupt 0

7272

#define PORTA_INT1_vect _VECTOR(67) // External Interrupt 1

7273

7274

/* ACA interrupt vectors */

7275

#define ACA_ACW_vect _VECTOR(70) // ACW Window Mode Interrupt

7276

#define ACA_AC1_vect _VECTOR(69) // AC1 Interrupt

7277

#define ACA_AC0_vect _VECTOR(68) // AC0 Interrupt

7278

7279

/* ADCA interrupt vectors */

7280

#define ADCA_CH0_vect _VECTOR(71) // Interrupt 0

7281

#define ADCA_CH1_vect _VECTOR(72) // Interrupt 1

7282

#define ADCA_CH2_vect _VECTOR(73) // Interrupt 2

7283

#define ADCA_CH3_vect _VECTOR(74) // Interrupt 3

7284

7285

/* TWID interrupt vectors */

7286

#define TWID_TWIS_vect _VECTOR(75) // TWI Slave Interrupt

7287

#define TWID_TWIM_vect _VECTOR(76) // TWI Master Interrupt

7288

7289

/* TCD0 interrupt vectors */

7290

#define TCD0_OVF_vect _VECTOR(77) // Overflow Interrupt

7291

#define TCD0_ERR_vect _VECTOR(78) // Error Interrupt

7292

#define TCD0_CCA_vect _VECTOR(79) // Compare or Capture A Interrupt

7293

#define TCD0_CCB_vect _VECTOR(80) // Compare or Capture B Interrupt

7294

#define TCD0_CCC_vect _VECTOR(81) // Compare or Capture C Interrupt

7295

#define TCD0_CCD_vect _VECTOR(82) // Compare or Capture D Interrupt

7296

7297

/* TCD1 interrupt vectors */

7298

#define TCD1_OVF_vect _VECTOR(83) // Overflow Interrupt

7299

#define TCD1_ERR_vect _VECTOR(84) // Error Interrupt

7300

#define TCD1_CCA_vect _VECTOR(85) // Compare or Capture A Interrupt

7301

#define TCD1_CCB_vect _VECTOR(86) // Compare or Capture B Interrupt

7302

7303

/* SPID interrupt vectors */

7304

#define SPID_INT_vect _VECTOR(87) // SPI Interrupt

7305

7306

/* USARTD0 interrupt vectors */

7307

#define USARTD0_RXC_vect _VECTOR(88) // Reception Complete Interrupt

7308

#define USARTD0_DRE_vect _VECTOR(89) // Data Register Empty Interrupt

7309

#define USARTD0_TXC_vect _VECTOR(90) // Transmission Complete Interrupt

7310

7311

/* USARTD1 interrupt vectors */

7312

#define USARTD1_RXC_vect _VECTOR(91) // Reception Complete Interrupt

7313

#define USARTD1_DRE_vect _VECTOR(92) // Data Register Empty Interrupt

7314

#define USARTD1_TXC_vect _VECTOR(93) // Transmission Complete Interrupt

7315

7316

/* PORTQ interrupt vectors */

7317

#define PORTQ_INT0_vect _VECTOR(94) // External Interrupt 0

7318

#define PORTQ_INT1_vect _VECTOR(95) // External Interrupt 1

7319

7320

/* PORTH interrupt vectors */

7321

#define PORTH_INT0_vect _VECTOR(96) // External Interrupt 0

7322

#define PORTH_INT1_vect _VECTOR(97) // External Interrupt 1

7323

7324

/* PORTJ interrupt vectors */

7325

#define PORTJ_INT0_vect _VECTOR(98) // External Interrupt 0

7326

#define PORTJ_INT1_vect _VECTOR(99) // External Interrupt 1

7327

7328

/* PORTK interrupt vectors */

7329

#define PORTK_INT0_vect _VECTOR(100) // External Interrupt 0

7330

#define PORTK_INT1_vect _VECTOR(101) // External Interrupt 1

7331

7332

/* PORTF interrupt vectors */

7333

#define PORTF_INT0_vect _VECTOR(104) // External Interrupt 0

7334

#define PORTF_INT1_vect _VECTOR(105) // External Interrupt 1

7335

7336

/* TWIF interrupt vectors */

7337

#define TWIF_TWIS_vect _VECTOR(106) // TWI Slave Interrupt

7338

#define TWIF_TWIM_vect _VECTOR(107) // TWI Master Interrupt

7339

7340

/* TCF0 interrupt vectors */

7341

#define TCF0_OVF_vect _VECTOR(108) // Overflow Interrupt

7342

#define TCF0_ERR_vect _VECTOR(109) // Error Interrupt

7343

#define TCF0_CCA_vect _VECTOR(110) // Compare or Capture A Interrupt

7344

#define TCF0_CCB_vect _VECTOR(111) // Compare or Capture B Interrupt

7345

#define TCF0_CCC_vect _VECTOR(112) // Compare or Capture C Interrupt

7346

#define TCF0_CCD_vect _VECTOR(113) // Compare or Capture D Interrupt

7347

7348

/* TCF1 interrupt vectors */

7349

#define TCF1_OVF_vect _VECTOR(114) // Overflow Interrupt

7350

#define TCF1_ERR_vect _VECTOR(115) // Error Interrupt

7351

#define TCF1_CCA_vect _VECTOR(116) // Compare or Capture A Interrupt

7352

#define TCF1_CCB_vect _VECTOR(117) // Compare or Capture B Interrupt

7353

7354

/* SPIF interrupt vectors */

7355

#define SPIF_INT_vect _VECTOR(118) // SPI Interrupt

7356

7357

/* USARTF0 interrupt vectors */

7358

#define USARTF0_RXC_vect _VECTOR(119) // Reception Complete Interrupt

7359

#define USARTF0_DRE_vect _VECTOR(120) // Data Register Empty Interrupt

7360

#define USARTF0_TXC_vect _VECTOR(121) // Transmission Complete Interrupt

7361

7362

/* USARTF1 interrupt vectors */

7363

#define USARTF1_RXC_vect _VECTOR(122) // Reception Complete Interrupt

7364

#define USARTF1_DRE_vect _VECTOR(123) // Data Register Empty Interrupt

7365

#define USARTF1_TXC_vect _VECTOR(124) // Transmission Complete Interrupt

7366

7367

#define _VECTORS_SIZE (125 * 4)

7368

7369

7370

7371

/* Constants */

7372

#define SPM_PAGESIZE (256)

7373

#define RAMSTART (0x2000)

7374

#define RAMSIZE (0x2000)

7375

#define RAMEND (RAMSTART + RAMSIZE - 1) /* Last On-Chip SRAM Location. */

7376

#define XRAMEND (0xFFFFFF)

7377

#define E2END (0x7FF)

7378

#define E2PAGESIZE (32)

7379

#define FLASHEND (0x23FFF)

7380

7381

7382

/* Fuses */

7383

#define FUSE_MEMORY_SIZE 5

7384

7385

/* Fuse Byte 0 */

7386

#define FUSE_USERID0 ~_BV(0)

7387

#define FUSE_USERID1 ~_BV(1)

7388

#define FUSE_USERID2 ~_BV(2)

7389

#define FUSE_USERID3 ~_BV(3)

7390

#define FUSE_USERID4 ~_BV(4)

7391

#define FUSE_USERID5 ~_BV(5)

7392

#define FUSE_USERID6 ~_BV(6)

7393

#define FUSE_USERID7 ~_BV(7)

7394

#define FUSE0_DEFAULT (0x00)

7395

7396

/* Fuse Byte 1 */

7397

#define FUSE_WDPER0 ~_BV(0)

7398

#define FUSE_WDPER1 ~_BV(1)

7399

#define FUSE_WDPER2 ~_BV(2)

7400

#define FUSE_WDPER3 ~_BV(3)

7401

#define FUSE_WDWPER0 ~_BV(4)

7402

#define FUSE_WDWPER1 ~_BV(5)

7403

#define FUSE_WDWPER2 ~_BV(6)

7404

#define FUSE_WDWPER3 ~_BV(7)

7405

#define FUSE1_DEFAULT (0x00)

7406

7407

/* Fuse Byte 2 */

7408

#define FUSE_BODPD0 ~_BV(0)

7409

#define FUSE_BODPD1 ~_BV(1)

7410

#define FUSE_BODACT0 ~_BV(3)

7411

#define FUSE_BODACT1 ~_BV(4)

7412

#define FUSE_BOOTRST ~_BV(6)

7413

#define FUSE_DVSDON ~_BV(7)

7414

#define FUSE2_DEFAULT (0x00)

7415

7416

/* Fuse Byte 3 */

7417

#define FUSE_JTAGEN ~_BV(0)

7418

#define FUSE_WDLOCK ~_BV(1)

7419

#define FUSE_SUT0 ~_BV(2)

7420

#define FUSE_SUT1 ~_BV(3)

7421

#define FUSE_RSTDISBL ~_BV(4)

7422

#define FUSE3_DEFAULT (0x00)

7423

7424

/* Fuse Byte 4 */

7425

#define FUSE_BOD0 ~_BV(0)

7426

#define FUSE_BOD1 ~_BV(1)

7427

#define FUSE_BOD2 ~_BV(2)

7428

#define FUSE_EESAVE ~_BV(3)

7429

#define FUSE4_DEFAULT (0x00)

7430

7431

7432

7433

/* Lock Bits */

7434

#define __LOCK_BITS_EXIST

7435

#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST

7436

#define __BOOT_LOCK_APPLICATION_BITS_EXIST

7437

#define __BOOT_LOCK_BOOT_BITS_EXIST

7438

7439

7440

7441

#endif /* _AVR_ATxmega128A1_H_ */