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  • Committer: Bazaar Package Importer
  • Author(s): Matthias Klose
  • Date: 2007-09-19 11:14:05 UTC
  • mfrom: (1.1.1 upstream)
  • Revision ID: james.westby@ubuntu.com-20070919111405-o1mwupec9d5e0waj
Tags: 6.6.50cvs20070623-1
* Update to SDK 3.0 earlyRel.
* Change cross-prefix to /usr/lib/cell/toolchain.  Do not change sysroot.
* debian/rules: Support parallel=<n> in DEB_BUILD_OPTIONS.

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        * opcode/spu-insns.h: Add dfceq, dfcmeq, dfcgt, dfcmgt, dftsv.
 
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diff -u -p -r1.1 spu-insns.h
 
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--- gdb-6.6/include/opcode/spu-insns.h  25 Oct 2006 06:49:18 -0000      1.1
 
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+++ gdb-6.6/include/opcode/spu-insns.h  1 Dec 2006 07:34:31 -0000
 
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@@ -403,6 +403,13 @@ APUOPFB(M_BITE,    RR,     0x129,  0x10,   "bite"
 
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 APUOPFB(M_BIFD,                RR,     0x128,  0x20,   "bifd",         _A2(A_T,A_A),   00011,  BR)     /* BIZ           IP<-RA_if(RT) */
 
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 APUOPFB(M_BIFE,                RR,     0x128,  0x10,   "bife",         _A2(A_T,A_A),   00011,  BR)     /* BIZ           IP<-RA_if(RT) */
 
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+/* New soma double-float insns.  */
 
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+APUOP(M_DFCEQ,         RR,     0x3c3,  "dfceq",        _A3(A_T,A_A,A_B),       00112,  FX2)    /* DFCEQ         RT<-(RA=RB) */
 
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+APUOP(M_DFCMEQ,                RR,     0x3cb,  "dfcmeq",       _A3(A_T,A_A,A_B),       00112,  FX2)    /* DFCMEQ        RT<-(|RA|=|RB|) */
 
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+APUOP(M_DFCGT,         RR,     0x2c3,  "dfcgt",        _A3(A_T,A_A,A_B),       00112,  FX2)    /* DFCGT         RT<-(RA>RB) */
 
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+APUOP(M_DFCMGT,                RR,     0x2cb,  "dfcmgt",       _A3(A_T,A_A,A_B),       00112,  FX2)    /* DFCMGT        RT<-(|RA|>|RB|) */
 
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+APUOP(M_DFTSV,         RI7,    0x3bf,  "dftsv",        _A3(A_T,A_A,A_U7),      00012,  FX2)    /* DFTSV         RT<-testspecial(RA,I7) */
 
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+
 
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 #undef _A0
 
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 #undef _A1
 
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 #undef _A2