890
890
struct s3c64xx_spi_driver_data *sdd = data;
891
891
struct spi_master *spi = sdd->master;
894
val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR);
896
val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR |
897
S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
898
S3C64XX_SPI_PND_TX_OVERRUN_CLR |
899
S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
901
writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR);
903
if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR)
892
unsigned int val, clr = 0;
894
val = readl(sdd->regs + S3C64XX_SPI_STATUS);
896
if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
897
clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
904
898
dev_err(&spi->dev, "RX overrun\n");
905
if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR)
900
if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
901
clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
906
902
dev_err(&spi->dev, "RX underrun\n");
907
if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR)
904
if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
905
clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
908
906
dev_err(&spi->dev, "TX overrun\n");
909
if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR)
908
if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
909
clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
910
910
dev_err(&spi->dev, "TX underrun\n");
913
/* Clear the pending irq by setting and then clearing it */
914
writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
915
writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
912
917
return IRQ_HANDLED;
931
936
writel(0, regs + S3C64XX_SPI_MODE_CFG);
932
937
writel(0, regs + S3C64XX_SPI_PACKET_CNT);
934
/* Clear any irq pending bits */
935
writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
936
regs + S3C64XX_SPI_PENDING_CLR);
939
/* Clear any irq pending bits, should set and clear the bits */
940
val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
941
S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
942
S3C64XX_SPI_PND_TX_OVERRUN_CLR |
943
S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
944
writel(val, regs + S3C64XX_SPI_PENDING_CLR);
945
writel(0, regs + S3C64XX_SPI_PENDING_CLR);
938
947
writel(0, regs + S3C64XX_SPI_SWAP_CFG);