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/////////////////////////////////////////////////////////////////////////
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// $Id: vmexit.cc,v 1.5 2009/02/17 19:20:47 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2009 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
27
#define LOG_THIS BX_CPU_THIS_PTR
29
#if BX_SUPPORT_X86_64==0
30
// Make life easier for merging cpu64 and cpu32 code.
37
Bit32u gen_instruction_info(bxInstruction_c *i, Bit32u reason)
39
Bit32u instr_info = 0;
42
case VMX_VMEXIT_VMREAD:
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case VMX_VMEXIT_VMWRITE:
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instr_info |= i->nnn() << 28;
51
// --------------------------------------
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// instruction information field format
53
// --------------------------------------
55
// [.2:.0] | Memory operand scale field (encoded)
56
// [.6:.3] | Reg1, undefined when memory operand
57
// [.9:.7] | Memory operand address size
58
// [10:10] | Memory/Register format (0 - mem, 1 - reg)
60
// [17:15] | Memory operand segment register field
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// [21:18] | Memory operand index field
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// [22:22] | Memory operand index field invalid
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// [26:23] | Memory operand base field
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// [27:27] | Memory operand base field invalid
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// [31:28] | Reg2, if exists
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instr_info |= (1 << 10) | (i->rm() << 3);
78
instr_info |= i->seg() << 15;
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if (i->sibIndex() != BX_NIL_REGISTER)
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instr_info |= i->sibScale() | (i->sibIndex() << 18);
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instr_info |= 1 << 22; // index invalid
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if (i->sibBase() != BX_NIL_REGISTER)
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instr_info |= i->sibBase() << 23;
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instr_info |= 1 << 27; // base invalid
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void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_Instruction(bxInstruction_c *i, Bit32u reason)
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Bit64u qualification = 0;
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Bit32u instr_info = 0;
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case VMX_VMEXIT_VMCALL:
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case VMX_VMEXIT_VMLAUNCH:
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case VMX_VMEXIT_VMRESUME:
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case VMX_VMEXIT_VMXOFF:
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// do not have VMEXIT instruction info
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case VMX_VMEXIT_VMREAD:
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case VMX_VMEXIT_VMWRITE:
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case VMX_VMEXIT_VMPTRLD:
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case VMX_VMEXIT_VMPTRST:
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case VMX_VMEXIT_VMCLEAR:
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case VMX_VMEXIT_VMXON:
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qualification = (Bit64u) ((bx_address) i->displ32s());
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#if BX_SUPPORT_X86_64
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if (i->sibBase() == BX_64BIT_REG_RIP)
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qualification += RIP;
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instr_info = gen_instruction_info(i, reason);
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VMwrite32(VMCS_32BIT_VMEXIT_INSTRUCTION_INFO, instr_info);
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BX_PANIC(("VMexit_Instruction reason %d", reason));
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VMexit(i, reason, qualification);
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_HLT(bxInstruction_c *i)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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if (VMEXIT(VMX_VM_EXEC_CTRL2_HLT_VMEXIT))
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BX_ERROR(("VMEXIT: HLT"));
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VMexit(i, VMX_VMEXIT_HLT, 0);
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_PAUSE(bxInstruction_c *i)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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if (VMEXIT(VMX_VM_EXEC_CTRL2_PAUSE_VMEXIT))
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BX_ERROR(("VMEXIT: PAUSE"));
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VMexit(i, VMX_VMEXIT_PAUSE, 0);
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void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_INVLPG(bxInstruction_c *i, bx_address laddr)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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if (VMEXIT(VMX_VM_EXEC_CTRL2_INVLPG_VMEXIT))
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BX_ERROR(("VMEXIT: INVLPG 0x" FMT_ADDRX, laddr));
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VMexit(i, VMX_VMEXIT_INVLPG, laddr);
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Bit64s BX_CPU_C::VMX_TSC_Offset(void)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return 0;
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if (VMEXIT(VMX_VM_EXEC_CTRL2_TSC_OFFSET))
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return (Bit64s) BX_CPU_THIS_PTR vmcs.tsc_offset;
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_RDTSC(bxInstruction_c *i)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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if (VMEXIT(VMX_VM_EXEC_CTRL2_RDTSC_VMEXIT))
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BX_ERROR(("VMEXIT: RDTSC"));
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VMexit(i, VMX_VMEXIT_RDTSC, 0);
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_RDPMC(bxInstruction_c *i)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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if (VMEXIT(VMX_VM_EXEC_CTRL2_RDPMC_VMEXIT))
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BX_ERROR(("VMEXIT: RDPMC"));
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VMexit(i, VMX_VMEXIT_RDPMC, 0);
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#if BX_SUPPORT_MONITOR_MWAIT
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_MONITOR(bxInstruction_c *i)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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if (VMEXIT(VMX_VM_EXEC_CTRL2_MONITOR_VMEXIT))
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BX_ERROR(("VMEXIT: MONITOR"));
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VMexit(i, VMX_VMEXIT_MONITOR, 0);
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_MWAIT(bxInstruction_c *i)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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if (VMEXIT(VMX_VM_EXEC_CTRL2_MWAIT_VMEXIT))
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BX_ERROR(("VMEXIT: MWAIT"));
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VMexit(i, VMX_VMEXIT_MWAIT, 0);
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void BX_CPU_C::VMexit_ExtInterrupt(void)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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if (PIN_VMEXIT(VMX_VM_EXEC_CTRL1_EXTERNAL_INTERRUPT_VMEXIT)) {
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if (! PIN_VMEXIT(VMX_VMEXIT_CTRL1_INTA_ON_VMEXIT)) {
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// interrupt wasn't acknowledged and still pending, interruption info is invalid
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VMwrite32(VMCS_32BIT_VMEXIT_INTERRUPTION_INFO, 0);
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VMexit(0, VMX_VMEXIT_EXTERNAL_INTERRUPT, 0);
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void BX_CPU_C::VMexit_Event(bxInstruction_c *i, unsigned type, unsigned vector, Bit16u errcode, bx_bool errcode_valid, Bit64u qualification)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
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VMX_vmexit_reason reason = VMX_VMEXIT_EXCEPTION_NMI;
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case BX_EXTERNAL_INTERRUPT:
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reason = VMX_VMEXIT_EXTERNAL_INTERRUPT;
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if (PIN_VMEXIT(VMX_VM_EXEC_CTRL1_EXTERNAL_INTERRUPT_VMEXIT))
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if (PIN_VMEXIT(VMX_VM_EXEC_CTRL1_NMI_VMEXIT))
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case BX_PRIVILEGED_SOFTWARE_INTERRUPT:
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case BX_SOFTWARE_EXCEPTION:
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case BX_HARDWARE_EXCEPTION:
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BX_ASSERT((vector < BX_CPU_HANDLED_EXCEPTIONS));
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if (vector == BX_PF_EXCEPTION) {
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// page faults are specially treated
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bx_bool err_match = ((errcode & vm->vm_pf_mask) == vm->vm_pf_match);
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bx_bool bitmap = (vm->vm_exceptions_bitmap >> BX_PF_EXCEPTION) & 1;
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vmexit = (err_match == bitmap);
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vmexit = (vm->vm_exceptions_bitmap >> vector) & 1;
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case BX_SOFTWARE_INTERRUPT:
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break; // no VMEXIT on software interrupt
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BX_ERROR(("VMexit_Event: unknown event type %d", type));
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// ----------------------------------------------------
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// VMExit interruption info
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// ----------------------------------------------------
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// [.7:.0] | Interrupt/Exception vector
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// [10:.8] | Interrupt/Exception type
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// [11:11] | error code pushed to the stack
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// [12:12] | NMI unblocking due to IRET
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// [30:13] | reserved
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// [31:31] | interruption info valid
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// record IDT vectoring information
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vm->idt_vector_error_code = errcode;
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vm->idt_vector_info = vector | (type << 8);
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vm->idt_vector_info |= (1 << 11); // error code delivered
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BX_ERROR(("VMEXIT: exception 0x%02x error code = 0x%04x", vector, errcode));
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// VMEXIT is not considered to occur during event delivery if it results
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// in a double fault exception that causes VMEXIT directly
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if (vector == BX_DF_EXCEPTION)
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BX_CPU_THIS_PTR in_event = 0; // clear in_event indication on #DF
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// qualifcation for debug exceptions similar to debug_trap field
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if (vector == BX_DB_EXCEPTION)
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qualification = BX_CPU_THIS_PTR debug_trap & 0x0000600f;
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Bit32u interruption_info = vector | (type << 8);
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interruption_info |= (1 << 11); // error code delivered
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interruption_info |= (1 << 31); // valid
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VMwrite32(VMCS_32BIT_VMEXIT_INTERRUPTION_INFO, interruption_info);
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VMwrite32(VMCS_32BIT_VMEXIT_INTERRUPTION_ERR_CODE, errcode);
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VMexit(i, reason, qualification);
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void BX_CPU_C::VMexit_TripleFault(void)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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BX_ERROR(("VMEXIT: triple fault"));
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// VMEXIT is not considered to occur during event delivery if it results
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// in a triple fault exception (that causes VMEXIT directly)
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BX_CPU_THIS_PTR in_event = 0;
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VMexit(0, VMX_VMEXIT_TRIPLE_FAULT, 0);
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void BX_CPP_AttrRegparmN(3) BX_CPU_C::VMexit_TaskSwitch(bxInstruction_c *i, Bit16u tss_selector, unsigned source)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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BX_ERROR(("VMEXIT: task switch"));
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VMexit(i, VMX_VMEXIT_TASK_SWITCH, tss_selector | (source << 30));
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_SoftwareInterrupt(bxInstruction_c *i)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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void BX_CPP_AttrRegparmN(3) BX_CPU_C::VMexit_MSR(bxInstruction_c *i, unsigned op, Bit32u msr)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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if (! VMEXIT(VMX_VM_EXEC_CTRL2_MSR_BITMAPS)) vmexit = 1;
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VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
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if (msr & 0xC0000000) {
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if (msr > 0xC0001FFF) vmexit = 1;
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// check MSR-HI bitmaps
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bx_phy_address pAddr = vm->msr_bitmap_addr + (msr >> 3) + 1024 + (op == VMX_VMEXIT_RDMSR) ? 0 : 2048;
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access_read_physical(pAddr, 1, &field);
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BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_READ, &field);
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if (field & (1 << (msr & 7)))
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if (msr > 0x00001FFF) vmexit = 1;
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// check MSR-LO bitmaps
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bx_phy_address pAddr = vm->msr_bitmap_addr + (msr >> 3) + (op == VMX_VMEXIT_RDMSR) ? 0 : 2048;
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access_read_physical(pAddr, 1, &field);
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BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 1, BX_READ, &field);
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if (field & (1 << (msr & 7)))
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BX_ERROR(("VMEXIT: %sMSR 0x%08x", (op == VMX_VMEXIT_RDMSR) ? "RD" : "WR", msr));
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#define VMX_VMEXIT_IO_PORTIN (1 << 3)
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#define VMX_VMEXIT_IO_INSTR_STRING (1 << 4)
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#define VMX_VMEXIT_IO_INSTR_REP (1 << 5)
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#define VMX_VMEXIT_IO_INSTR_IMM (1 << 6)
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void BX_CPP_AttrRegparmN(3) BX_CPU_C::VMexit_IO(bxInstruction_c *i, unsigned port, unsigned len)
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if (! BX_CPU_THIS_PTR in_vmx_guest) return;
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BX_ASSERT((port <= 0xFFFF));
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if (VMEXIT(VMX_VM_EXEC_CTRL2_IO_BITMAPS)) {
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// always VMEXIT on port "wrap around" case
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if (port + len > 0x10000) vmexit = 1;
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bx_phy_address pAddr = BX_CPU_THIS_PTR vmcs.io_bitmap_addr[(port >> 15) & 1] + ((port & 0x7fff) >> 4);
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access_read_physical(pAddr, 2, (Bit8u*) &bitmap);
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BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, pAddr, 2, BX_READ, (Bit8u*) &bitmap);
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for (unsigned n = port; n < port + len; n++) {
406
if (bitmap & (1 << (n & 15))) {
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else if (VMEXIT(VMX_VM_EXEC_CTRL2_IO_VMEXIT)) vmexit = 1;
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BX_ERROR(("VMEXIT: I/O port 0x%04x", port));
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Bit32u qualification = 0;
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case 0xe4: // IN_ALIb
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case 0xe5: // IN_AXIb, IN_EAXIb
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qualification = VMX_VMEXIT_IO_PORTIN | VMX_VMEXIT_IO_INSTR_IMM;
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case 0xe6: // OUT_IbAL
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case 0xe7: // OUT_IbAX, OUT_IbEAX
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qualification = VMX_VMEXIT_IO_INSTR_IMM;
431
case 0xec: // IN_ALDX
432
case 0xed: // IN_AXDX, IN_EAXDX
433
qualification = VMX_VMEXIT_IO_PORTIN; // no immediate
436
case 0xee: // OUT_DXAL
437
case 0xef: // OUT_DXAX, OUT_DXEAX
438
qualification = 0; // PORTOUT, no immediate
441
case 0x6c: // INSB_YbDX
442
case 0x6d: // INSW_YwDX, INSD_YdDX
443
qualification = VMX_VMEXIT_IO_PORTIN | VMX_VMEXIT_IO_INSTR_STRING;
445
qualification |= VMX_VMEXIT_IO_INSTR_REP;
448
case 0x6e: // OUTSB_DXXb
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case 0x6f: // OUTSW_DXXw, OUTSD_DXXd
450
qualification = VMX_VMEXIT_IO_INSTR_STRING; // PORTOUT
452
qualification |= VMX_VMEXIT_IO_INSTR_REP;
456
BX_PANIC(("VMexit_IO: I/O instruction b1()=%x unknown", i->b1()));
459
if (qualification & VMX_VMEXIT_IO_INSTR_STRING) {
460
bx_address asize_mask = BX_CONST64(0xffffffffffffffff), laddr;
462
if (i->as32L()) asize_mask = 0xffffffff;
463
else asize_mask = 0xffff;
466
if (qualification & VMX_VMEXIT_IO_PORTIN)
467
laddr = BX_CPU_THIS_PTR get_laddr(BX_SEG_REG_ES, RDI & asize_mask);
469
laddr = BX_CPU_THIS_PTR get_laddr(i->seg(), RSI & asize_mask);
471
VMwrite64(VMCS_GUEST_LINEAR_ADDR, laddr);
474
VMexit(i, VMX_VMEXIT_IO_INSTRUCTION, qualification | (len-1) | (port << 16));
479
// ----------------------------------------------------------------
480
// Exit qualification for CR access
481
// ----------------------------------------------------------------
482
// [.3:.0] | Number of CR register (CR0, CR3, CR4, CR8)
483
// [.5:.4] | CR access type (0 - MOV to CR, 1 - MOV from CR, 2 - CLTS, 3 - LMSW)
484
// [.6:.6] | LMSW operand reg/mem (cleared for CR access and CLTS)
485
// [.7:.7] | reserved
486
// [11:.8] | Source Operand Register for CR access (cleared for CLTS and LMSW)
487
// [15:12] | reserved
488
// [31:16] | LMSW source data (cleared for CR access and CLTS)
489
// [63:32] | reserved
492
bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_CLTS(bxInstruction_c *i)
494
if (! BX_CPU_THIS_PTR in_vmx_guest) return 0;
496
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
498
if (vm->vm_cr0_mask & vm->vm_cr0_read_shadow & 0x8)
500
BX_ERROR(("VMEXIT: CLTS"));
502
// all rest of the fields cleared to zero
503
Bit64u qualification = VMX_VMEXIT_CR_ACCESS_CLTS << 4;
505
VMexit(i, VMX_VMEXIT_CR_ACCESS, qualification);
508
if ((vm->vm_cr0_mask & 0x8) != 0 && (vm->vm_cr0_read_shadow & 0x8) == 0)
509
return 1; /* do not clear CR0.TS */
514
Bit32u BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_LMSW(bxInstruction_c *i, Bit32u msw)
516
if (! BX_CPU_THIS_PTR in_vmx_guest) return msw;
518
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
519
Bit32u mask = vm->vm_cr0_mask & 0xF; /* LMSW affects only low 4 bits */
522
if ((mask & msw & 0x1) != 0 && (vm->vm_cr0_read_shadow & 0x1) == 0)
525
if ((mask & vm->vm_cr0_read_shadow & 0xE) != (mask & msw & 0xE))
529
BX_ERROR(("VMEXIT: CR0 write by LMSW of value 0x%04x", msw));
531
Bit64u qualification = VMX_VMEXIT_CR_ACCESS_LMSW << 4;
532
qualification |= msw << 16;
534
qualification |= (1 << 6); // memory operand
535
VMwrite64(VMCS_GUEST_LINEAR_ADDR, BX_CPU_THIS_PTR get_laddr(i->seg(), RMAddr(i)));
538
VMexit(i, VMX_VMEXIT_CR_ACCESS, qualification);
541
// keep untouched all the bits set in CR0 mask
542
return (BX_CPU_THIS_PTR cr0.get32() & mask) | (msw & ~mask);
545
bx_address BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_CR0_Write(bxInstruction_c *i, bx_address val)
547
if (! BX_CPU_THIS_PTR in_vmx_guest) return val;
549
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
551
if ((vm->vm_cr0_mask & vm->vm_cr0_read_shadow) != (vm->vm_cr0_mask & val))
553
BX_ERROR(("VMEXIT: CR0 write"));
554
Bit64u qualification = i->rm() << 8;
555
VMexit(i, VMX_VMEXIT_CR_ACCESS, qualification);
558
// keep untouched all the bits set in CR0 mask
559
return (BX_CPU_THIS_PTR cr0.get32() & vm->vm_cr0_mask) | (val & ~vm->vm_cr0_mask);
562
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_CR3_Read(bxInstruction_c *i)
564
if (! BX_CPU_THIS_PTR in_vmx_guest) return;
566
if (VMEXIT(VMX_VM_EXEC_CTRL2_CR3_READ_VMEXIT)) {
567
BX_ERROR(("VMEXIT: CR3 read"));
569
Bit64u qualification = 3 | (VMX_VMEXIT_CR_ACCESS_CR_READ << 4);
570
qualification |= (i->rm() << 8);
572
VMexit(i, VMX_VMEXIT_CR_ACCESS, qualification);
576
void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_CR3_Write(bxInstruction_c *i, bx_address val)
578
if (! BX_CPU_THIS_PTR in_vmx_guest) return;
580
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
582
if (VMEXIT(VMX_VM_EXEC_CTRL2_CR3_WRITE_VMEXIT)) {
583
for (unsigned n=0; n < vm->vm_cr3_target_cnt; n++) {
584
if (vm->vm_cr3_target_value[n] == val) return;
587
BX_ERROR(("VMEXIT: CR3 write"));
588
Bit64u qualification = 3 | (i->rm() << 8);
589
VMexit(i, VMX_VMEXIT_CR_ACCESS, qualification);
593
bx_address BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_CR4_Write(bxInstruction_c *i, bx_address val)
595
if (! BX_CPU_THIS_PTR in_vmx_guest) return val;
597
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
599
if ((vm->vm_cr4_mask & vm->vm_cr4_read_shadow) != (vm->vm_cr4_mask & val))
601
BX_ERROR(("VMEXIT: CR4 write"));
602
Bit64u qualification = 4 | (i->rm() << 8);
603
VMexit(i, VMX_VMEXIT_CR_ACCESS, qualification);
606
// keep untouched all the bits set in CR4 mask
607
return (BX_CPU_THIS_PTR cr4.get32() & vm->vm_cr4_mask) | (val & ~vm->vm_cr4_mask);
610
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_CR8_Read(bxInstruction_c *i)
612
if (! BX_CPU_THIS_PTR in_vmx_guest) return;
614
if (VMEXIT(VMX_VM_EXEC_CTRL2_CR8_READ_VMEXIT)) {
615
BX_ERROR(("VMEXIT: CR8 read"));
617
Bit64u qualification = 8 | (VMX_VMEXIT_CR_ACCESS_CR_READ << 4);
618
qualification |= (i->rm() << 8);
620
VMexit(i, VMX_VMEXIT_CR_ACCESS, qualification);
624
void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMexit_CR8_Write(bxInstruction_c *i)
626
if (! BX_CPU_THIS_PTR in_vmx_guest) return;
628
if (VMEXIT(VMX_VM_EXEC_CTRL2_CR8_WRITE_VMEXIT)) {
629
BX_ERROR(("VMEXIT: CR8 write"));
630
Bit64u qualification = 8 | (i->rm() << 8);
631
VMexit(i, VMX_VMEXIT_CR_ACCESS, qualification);
636
// ----------------------------------------------------------------
637
// Exit qualification for DR access
638
// ----------------------------------------------------------------
639
// [.3:.0] | Number of DR register
640
// [.4:.4] | DR access type (0 - MOV to DR, 1 - MOV from DR)
641
// [.7:.5] | reserved
642
// [11:.8] | Source Operand Register
643
// [63:12] | reserved
646
void BX_CPP_AttrRegparmN(2) BX_CPU_C::VMexit_DR_Access(bxInstruction_c *i, unsigned read)
648
if (! BX_CPU_THIS_PTR in_vmx_guest) return;
650
if (VMEXIT(VMX_VM_EXEC_CTRL2_DRx_ACCESS_VMEXIT))
652
BX_ERROR(("VMEXIT: DR%d %s access", i->nnn(), read ? "READ" : "WRITE"));
654
Bit64u qualification = i->nnn() | (i->rm() << 8);
656
qualification |= (1 << 4);
658
VMexit(i, VMX_VMEXIT_DR_ACCESS, qualification);
662
#endif // BX_SUPPORT_VMX
added
removed
cpu/vmexit.cc
