2
* Nokia N-series internet tablets.
4
* Copyright (C) 2007 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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#include "qemu-common.h"
22
#include "sysemu/sysemu.h"
26
#include "ui/console.h"
35
#include "sysemu/blockdev.h"
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#include "exec/address-spaces.h"
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/* Nokia N8x0 support */
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struct omap_mpu_state_s *mpu;
43
struct rfbi_chip_s blizzard;
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#define N8X0_TUSB_ENABLE_GPIO 0
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#define N800_MMC2_WP_GPIO 8
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#define N800_UNKNOWN_GPIO0 9 /* out */
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#define N810_MMC2_VIOSD_GPIO 9
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#define N810_HEADSET_AMP_GPIO 10
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#define N800_CAM_TURN_GPIO 12
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#define N810_GPS_RESET_GPIO 12
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#define N800_BLIZZARD_POWERDOWN_GPIO 15
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#define N800_MMC1_WP_GPIO 23
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#define N810_MMC2_VSD_GPIO 23
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#define N8X0_ONENAND_GPIO 26
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#define N810_BLIZZARD_RESET_GPIO 30
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#define N800_UNKNOWN_GPIO2 53 /* out */
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#define N8X0_TUSB_INT_GPIO 58
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#define N8X0_BT_WKUP_GPIO 61
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#define N8X0_STI_GPIO 62
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#define N8X0_CBUS_SEL_GPIO 64
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#define N8X0_CBUS_DAT_GPIO 65
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#define N8X0_CBUS_CLK_GPIO 66
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#define N8X0_WLAN_IRQ_GPIO 87
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#define N8X0_BT_RESET_GPIO 92
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#define N8X0_TEA5761_CS_GPIO 93
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#define N800_UNKNOWN_GPIO 94
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#define N810_TSC_RESET_GPIO 94
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#define N800_CAM_ACT_GPIO 95
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#define N810_GPS_WAKEUP_GPIO 95
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#define N8X0_MMC_CS_GPIO 96
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#define N8X0_WLAN_PWR_GPIO 97
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#define N8X0_BT_HOST_WKUP_GPIO 98
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#define N810_SPEAKER_AMP_GPIO 101
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#define N810_KB_LOCK_GPIO 102
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#define N800_TSC_TS_GPIO 103
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#define N810_TSC_TS_GPIO 106
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#define N8X0_HEADPHONE_GPIO 107
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#define N8X0_RETU_GPIO 108
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#define N800_TSC_KP_IRQ_GPIO 109
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#define N810_KEYBOARD_GPIO 109
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#define N800_BAT_COVER_GPIO 110
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#define N810_SLIDE_GPIO 110
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#define N8X0_TAHVO_GPIO 111
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#define N800_UNKNOWN_GPIO4 112 /* out */
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#define N810_SLEEPX_LED_GPIO 112
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#define N800_TSC_RESET_GPIO 118 /* ? */
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#define N810_AIC33_RESET_GPIO 118
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#define N800_TSC_UNKNOWN_GPIO 119 /* out */
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#define N8X0_TMP105_GPIO 125
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#define XLDR_LL_UART 1
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/* Addresses on the I2C bus 0 */
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#define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
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#define N8X0_TCM825x_ADDR 0x29 /* Camera */
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#define N810_LP5521_ADDR 0x32 /* LEDs */
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#define N810_TSL2563_ADDR 0x3d /* Light sensor */
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#define N810_LM8323_ADDR 0x45 /* Keyboard */
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/* Addresses on the I2C bus 1 */
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#define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
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#define N8X0_MENELAUS_ADDR 0x72 /* Power management */
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/* Chipselects on GPMC NOR interface */
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#define N8X0_ONENAND_CS 0
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#define N8X0_USB_ASYNC_CS 1
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#define N8X0_USB_SYNC_CS 4
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#define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
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static void n800_mmc_cs_cb(void *opaque, int line, int level)
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/* TODO: this seems to actually be connected to the menelaus, to
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* which also both MMC slots connect. */
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omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
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printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
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static void n8x0_gpio_setup(struct n800_s *s)
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qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->mpu->mmc, 1);
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qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);
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qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO));
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#define MAEMO_CAL_HEADER(...) \
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'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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static const uint8_t n8x0_cal_wlan_mac[] = {
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MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
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0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
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0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
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0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
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0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
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static const uint8_t n8x0_cal_bt_id[] = {
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MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
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0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
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0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
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static void n8x0_nand_setup(struct n800_s *s)
168
s->nand = qdev_create(NULL, "onenand");
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qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
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/* Either 0x40 or 0x48 are OK for the device ID */
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qdev_prop_set_uint16(s->nand, "device_id", 0x48);
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qdev_prop_set_uint16(s->nand, "version_id", 0);
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qdev_prop_set_int32(s->nand, "shift", 1);
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dinfo = drive_get(IF_MTD, 0, 0);
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if (dinfo && dinfo->bdrv) {
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qdev_prop_set_drive_nofail(s->nand, "drive", dinfo->bdrv);
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qdev_init_nofail(s->nand);
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sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
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qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
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omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(s->nand), 0));
183
otp_region = onenand_raw_otp(s->nand);
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memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
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memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
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/* XXX: in theory should also update the OOB for both pages */
190
static qemu_irq n8x0_system_powerdown;
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static void n8x0_powerdown_req(Notifier *n, void *opaque)
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qemu_irq_raise(n8x0_system_powerdown);
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static Notifier n8x0_system_powerdown_notifier = {
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.notify = n8x0_powerdown_req
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static void n8x0_i2c_setup(struct n800_s *s)
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qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO);
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i2c_bus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
207
/* Attach a menelaus PM chip */
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dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR);
209
qdev_connect_gpio_out(dev, 3,
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qdev_get_gpio_in(s->mpu->ih[0],
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OMAP_INT_24XX_SYS_NIRQ));
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n8x0_system_powerdown = qdev_get_gpio_in(dev, 3);
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qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier);
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/* Attach a TMP105 PM chip (A0 wired to ground) */
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dev = i2c_create_slave(i2c, "tmp105", N8X0_TMP105_ADDR);
218
qdev_connect_gpio_out(dev, 0, tmp_irq);
221
/* Touchscreen and keypad controller */
222
static MouseTransformInfo n800_pointercal = {
225
.a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
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static MouseTransformInfo n810_pointercal = {
231
.a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
234
#define RETU_KEYCODE 61 /* F3 */
236
static void n800_key_event(void *opaque, int keycode)
238
struct n800_s *s = (struct n800_s *) opaque;
239
int code = s->keymap[keycode & 0x7f];
242
if ((keycode & 0x7f) == RETU_KEYCODE)
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retu_key_event(s->retu, !(keycode & 0x80));
247
tsc2301_key_event(s->tsc, code, !(keycode & 0x80));
250
static const int n800_keys[16] = {
264
64, /* FullScreen (F6) */
269
static void n800_tsc_kbd_setup(struct n800_s *s)
273
/* XXX: are the three pins inverted inside the chip between the
274
* tsc and the cpu (N4111)? */
275
s->tsc = spi_create_device(omap_mcspi_bus(s->mpu->mcspi, 0), "tsc2301", 0);
277
qdev_connect_gpio_out(s->tsc, 1, qdev_get_gpio_in(s->mpu->gpio,
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N800_TSC_KP_IRQ_GPIO));
279
qdev_connect_gpio_out(s->tsc, 2, qdev_get_gpio_in(s->mpu->gpio,
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for (i = 0; i < 0x80; i ++)
284
for (i = 0; i < 0x10; i ++)
285
if (n800_keys[i] >= 0)
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s->keymap[n800_keys[i]] = i;
288
qemu_add_kbd_event_handler(n800_key_event, s);
290
tsc2301_set_transform(s->tsc, &n800_pointercal);
293
static void n810_tsc_setup(struct n800_s *s)
295
s->tsc = spi_create_device(omap_mcspi_bus(s->mpu->mcspi, 0), "tsc2005", 0);
296
qdev_connect_gpio_out(s->tsc, 0, qdev_get_gpio_in(s->mpu->gpio,
298
tsc2005_set_transform(s->tsc, &n810_pointercal, 400, 4000);
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/* N810 Keyboard controller */
302
static void n810_key_event(void *opaque, int keycode)
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struct n800_s *s = (struct n800_s *) opaque;
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int code = s->keymap[keycode & 0x7f];
308
if ((keycode & 0x7f) == RETU_KEYCODE)
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retu_key_event(s->retu, !(keycode & 0x80));
313
lm832x_key_event(s->kbd, code, !(keycode & 0x80));
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static int n810_keys[0x80] = {
323
[0x05] = 14, /* Backspace */
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[0x12] = 62, /* Menu (F4) */
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[0x14] = 40, /* ' (Apostrophe) */
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[0x1c] = 42, /* Shift (Left shift) */
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[0x1f] = 65, /* Zoom+ (F7) */
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[0x22] = 39, /* ; (Semicolon) */
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[0x23] = 12, /* - (Minus) */
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[0x24] = 13, /* = (Equal) */
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[0x2b] = 56, /* Fn (Left Alt) */
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[0x2f] = 66, /* Zoom- (F8) */
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[0x32] = 29 | M, /* Right Ctrl */
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[0x34] = 57, /* Space */
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[0x35] = 51, /* , (Comma) */
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[0x37] = 72 | M, /* Up */
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[0x3c] = 82 | M, /* Compose (Insert) */
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[0x3f] = 64, /* FullScreen (F6) */
362
[0x44] = 52, /* . (Dot) */
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[0x46] = 77 | M, /* Right */
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[0x4f] = 63, /* Home (F5) */
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[0x53] = 80 | M, /* Down */
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[0x55] = 28, /* Enter */
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[0x5f] = 1, /* Cycle (ESC) */
371
[0x64] = 75 | M, /* Left */
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[0x75] = 28 | M, /* KP Enter (KP Enter) */
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[0x75] = 15, /* KP Enter (Tab) */
383
static void n810_kbd_setup(struct n800_s *s)
385
qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO);
388
for (i = 0; i < 0x80; i ++)
390
for (i = 0; i < 0x80; i ++)
391
if (n810_keys[i] > 0)
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s->keymap[n810_keys[i]] = i;
394
qemu_add_kbd_event_handler(n810_key_event, s);
396
/* Attach the LM8322 keyboard to the I2C bus,
397
* should happen in n8x0_i2c_setup and s->kbd be initialised here. */
398
s->kbd = i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]),
399
"lm8323", N810_LM8323_ADDR);
400
qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
403
/* LCD MIPI DBI-C controller (URAL) */
425
static void mipid_reset(DeviceState *qdev)
427
struct mipid_s *s = FROM_SPI_DEVICE(struct mipid_s,
428
SPI_DEVICE_FROM_QDEV(qdev));
430
fprintf(stderr, "%s: Display off\n", __FUNCTION__);
438
(1 << 7) | /* Register loading OK. */
439
(1 << 5) | /* The chip is attached. */
440
(1 << 4); /* Display glass still in one piece. */
450
static uint32_t mipid_txrx(SPIDevice *spidev, uint32_t cmd, int len)
452
struct mipid_s *s = FROM_SPI_DEVICE(struct mipid_s, spidev);
456
hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
458
if (s->p >= ARRAY_SIZE(s->resp))
461
ret = s->resp[s->p ++];
463
s->param[s->pm] = cmd;
471
case 0x01: /* SWRESET */
472
mipid_reset(&s->spi.qdev);
475
case 0x02: /* BSTROFF */
478
case 0x03: /* BSTRON */
482
case 0x04: /* RDDID */
484
s->resp[0] = (s->id >> 16) & 0xff;
485
s->resp[1] = (s->id >> 8) & 0xff;
486
s->resp[2] = (s->id >> 0) & 0xff;
489
case 0x06: /* RD_RED */
490
case 0x07: /* RD_GREEN */
491
/* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
492
* for the bootloader one needs to change this. */
493
case 0x08: /* RD_BLUE */
495
/* TODO: return first pixel components */
499
case 0x09: /* RDDST */
501
s->resp[0] = s->booster << 7;
502
s->resp[1] = (5 << 4) | (s->partial << 2) |
503
(s->sleep << 1) | s->normal;
504
s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
505
(s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
506
s->resp[3] = s->gamma << 6;
509
case 0x0a: /* RDDPM */
511
s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
512
(s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
514
case 0x0b: /* RDDMADCTR */
518
case 0x0c: /* RDDCOLMOD */
520
s->resp[0] = 5; /* 65K colours */
522
case 0x0d: /* RDDIM */
524
s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
526
case 0x0e: /* RDDSM */
528
s->resp[0] = s->te << 7;
530
case 0x0f: /* RDDSDR */
532
s->resp[0] = s->selfcheck;
535
case 0x10: /* SLPIN */
538
case 0x11: /* SLPOUT */
540
s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
543
case 0x12: /* PTLON */
548
case 0x13: /* NORON */
554
case 0x20: /* INVOFF */
557
case 0x21: /* INVON */
561
case 0x22: /* APOFF */
562
case 0x23: /* APON */
565
case 0x25: /* WRCNTR */
570
case 0x26: /* GAMSET */
572
s->gamma = ffs(s->param[0] & 0xf) - 1;
577
case 0x28: /* DISPOFF */
579
fprintf(stderr, "%s: Display off\n", __FUNCTION__);
581
case 0x29: /* DISPON */
583
fprintf(stderr, "%s: Display on\n", __FUNCTION__);
586
case 0x2a: /* CASET */
587
case 0x2b: /* RASET */
588
case 0x2c: /* RAMWR */
589
case 0x2d: /* RGBSET */
590
case 0x2e: /* RAMRD */
591
case 0x30: /* PTLAR */
592
case 0x33: /* SCRLAR */
595
case 0x34: /* TEOFF */
598
case 0x35: /* TEON */
605
case 0x36: /* MADCTR */
608
case 0x37: /* VSCSAD */
614
case 0x38: /* IDMOFF */
615
case 0x39: /* IDMON */
616
case 0x3a: /* COLMOD */
619
case 0xb0: /* CLKINT / DISCTL */
620
case 0xb1: /* CLKEXT */
625
case 0xb4: /* FRMSEL */
628
case 0xb5: /* FRM8SEL */
629
case 0xb6: /* TMPRNG / INIESC */
630
case 0xb7: /* TMPHIS / NOP2 */
631
case 0xb8: /* TMPREAD / MADCTL */
632
case 0xba: /* DISTCTR */
633
case 0xbb: /* EPVOL */
636
case 0xbd: /* Unknown */
642
case 0xc2: /* IFMOD */
647
case 0xc6: /* PWRCTL */
648
case 0xc7: /* PPWRCTL */
649
case 0xd0: /* EPWROUT */
650
case 0xd1: /* EPWRIN */
651
case 0xd4: /* RDEV */
652
case 0xd5: /* RDRR */
655
case 0xda: /* RDID1 */
657
s->resp[0] = (s->id >> 16) & 0xff;
659
case 0xdb: /* RDID2 */
661
s->resp[0] = (s->id >> 8) & 0xff;
663
case 0xdc: /* RDID3 */
665
s->resp[0] = (s->id >> 0) & 0xff;
670
fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
677
static int mipid_init(SPIDevice *spidev)
682
static Property mipid_properties[] = {
683
DEFINE_PROP_UINT32("id", struct mipid_s, id, 0),
684
DEFINE_PROP_END_OF_LIST()
687
static void mipid_class_init(ObjectClass *klass, void *data)
689
DeviceClass *dc = DEVICE_CLASS(klass);
690
SPIDeviceClass *k = SPI_DEVICE_CLASS(klass);
692
k->init = mipid_init;
693
k->txrx = mipid_txrx;
694
dc->reset = mipid_reset;
695
dc->props = mipid_properties;
698
static TypeInfo mipid_info = {
700
.parent = TYPE_SPI_DEVICE,
701
.instance_size = sizeof(struct mipid_s),
702
.class_init = mipid_class_init,
705
static void n8x0_spi_setup(struct n800_s *s)
707
s->mipid = spi_create_device_noinit(omap_mcspi_bus(s->mpu->mcspi, 0),
709
qdev_prop_set_uint32(s->mipid, "id", 0x838f03);
710
qdev_init_nofail(s->mipid);
713
/* This task is normally performed by the bootloader. If we're loading
714
* a kernel directly, we need to enable the Blizzard ourselves. */
715
static void n800_dss_init(struct rfbi_chip_s *chip)
719
chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
720
chip->write(chip->opaque, 1, 0x64);
721
chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
722
chip->write(chip->opaque, 1, 0x1e);
723
chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
724
chip->write(chip->opaque, 1, 0xe0);
725
chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
726
chip->write(chip->opaque, 1, 0x01);
727
chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
728
chip->write(chip->opaque, 1, 0x06);
729
chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
730
chip->write(chip->opaque, 1, 1); /* Enable bit */
732
chip->write(chip->opaque, 0, 0x6c);
733
chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
734
chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
735
chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
736
chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
737
chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
738
chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
739
chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
740
chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
741
chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
742
chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
743
chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
744
chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
745
chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
746
chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
747
chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
748
chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
749
chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
750
chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
752
fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
753
/* Display Memory Data Port */
754
chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
758
static void n8x0_dss_setup(struct n800_s *s)
760
s->blizzard.opaque = s1d13745_init(NULL);
761
s->blizzard.block = s1d13745_write_block;
762
s->blizzard.write = s1d13745_write;
763
s->blizzard.read = s1d13745_read;
765
omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard);
768
static void n8x0_cbus_setup(struct n800_s *s)
770
qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO);
771
qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO);
772
qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO);
774
CBus *cbus = cbus_init(dat_out);
776
qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
777
qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
778
qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
780
cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
781
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
784
static void n8x0_uart_setup(struct n800_s *s)
786
CharDriverState *radio = uart_hci_init(
787
qdev_get_gpio_in(s->mpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
789
qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO,
790
csrhci_pins_get(radio)[csrhci_pin_reset]);
791
qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO,
792
csrhci_pins_get(radio)[csrhci_pin_wakeup]);
794
omap_uart_attach(s->mpu->uart[BT_UART], radio);
797
static void n8x0_usb_setup(struct n800_s *s)
800
s->usb = qdev_create(NULL, "tusb6010");
801
dev = SYS_BUS_DEVICE(s->usb);
802
qdev_init_nofail(s->usb);
803
sysbus_connect_irq(dev, 0,
804
qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
805
/* Using the NOR interface */
806
omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS,
807
sysbus_mmio_get_region(dev, 0));
808
omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS,
809
sysbus_mmio_get_region(dev, 1));
810
qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO,
811
qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */
814
/* Setup done before the main bootloader starts by some early setup code
815
* - used when we want to run the main bootloader in emulation. This
816
* isn't documented. */
817
static uint32_t n800_pinout[104] = {
818
0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
819
0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
820
0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
821
0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
822
0x01241800, 0x18181818, 0x000000f0, 0x01300000,
823
0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
824
0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
825
0x007c0000, 0x00000000, 0x00000088, 0x00840000,
826
0x00000000, 0x00000094, 0x00980300, 0x0f180003,
827
0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
828
0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
829
0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
830
0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
831
0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
832
0x00000000, 0x00000038, 0x00340000, 0x00000000,
833
0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
834
0x005c0808, 0x08080808, 0x08080058, 0x00540808,
835
0x08080808, 0x0808006c, 0x00680808, 0x08080808,
836
0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
837
0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
838
0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
839
0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
840
0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
841
0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
842
0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
843
0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
846
static void n800_setup_nolo_tags(void *sram_base)
849
uint32_t *p = sram_base + 0x8000;
850
uint32_t *v = sram_base + 0xa000;
852
memset(p, 0, 0x3000);
854
strcpy((void *) (p + 0), "QEMU N800");
856
strcpy((void *) (p + 8), "F5");
858
stl_raw(p + 10, 0x04f70000);
859
strcpy((void *) (p + 9), "RX-34");
861
/* RAM size in MB? */
862
stl_raw(p + 12, 0x80);
864
/* Pointer to the list of tags */
865
stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
867
/* The NOLO tags start here */
868
p = sram_base + 0x9000;
869
#define ADD_TAG(tag, len) \
870
stw_raw((uint16_t *) p + 0, tag); \
871
stw_raw((uint16_t *) p + 1, len); p ++; \
872
stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
874
/* OMAP STI console? Pin out settings? */
875
ADD_TAG(0x6e01, 414);
876
for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
877
stl_raw(v ++, n800_pinout[i]);
879
/* Kernel memsize? */
883
/* NOLO serial console */
885
stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
888
/* CBUS settings (Retu/AVilma) */
890
stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
891
stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
892
stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
896
/* Nokia ASIC BB5 (Retu/Tahvo) */
898
stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
899
stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
904
stw_raw((uint16_t *) v + 0, 30); /* ??? */
905
stw_raw((uint16_t *) v + 1, 24); /* ??? */
911
stw_raw((uint16_t *) (v ++), 15); /* ??? */
914
/* I^2C (Menelaus) */
916
stl_raw(v ++, 0x00720000); /* ??? */
920
stw_raw((uint16_t *) v + 0, 94); /* ??? */
921
stw_raw((uint16_t *) v + 1, 23); /* ??? */
922
stw_raw((uint16_t *) v + 2, 0); /* ??? */
925
/* OMAP gpio switch info */
927
strcpy((void *) v, "bat_cover"); v += 3;
928
stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
929
stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
931
strcpy((void *) v, "cam_act"); v += 3;
932
stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
933
stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
935
strcpy((void *) v, "cam_turn"); v += 3;
936
stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
937
stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
939
strcpy((void *) v, "headphone"); v += 3;
940
stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
941
stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
946
stl_raw(v ++, 0x5c623d01); /* ??? */
947
stl_raw(v ++, 0x00000201); /* ??? */
948
stl_raw(v ++, 0x00000000); /* ??? */
950
/* CX3110x WLAN settings */
952
stl_raw(v ++, 0x00610025); /* ??? */
953
stl_raw(v ++, 0xffff0057); /* ??? */
955
/* MMC host settings */
957
stl_raw(v ++, 0xffff000f); /* ??? */
958
stl_raw(v ++, 0xffffffff); /* ??? */
959
stl_raw(v ++, 0x00000060); /* ??? */
961
/* OneNAND chip select */
963
stl_raw(v ++, 0x00000401); /* ??? */
964
stl_raw(v ++, 0x0002003a); /* ??? */
965
stl_raw(v ++, 0x00000002); /* ??? */
967
/* TEA5761 sensor settings */
969
stl_raw(v ++, 93); /* GPIO num ??? */
975
/* Kernel UART / console */
979
/* End of the list */
980
stl_raw(p ++, 0x00000000);
981
stl_raw(p ++, 0x00000000);
984
/* This task is normally performed by the bootloader. If we're loading
985
* a kernel directly, we need to set up GPMC mappings ourselves. */
986
static void n800_gpmc_init(struct n800_s *s)
989
(0xf << 8) | /* MASKADDRESS */
990
(1 << 6) | /* CSVALID */
991
(4 << 0); /* BASEADDRESS */
993
cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
994
(void *) &config7, sizeof(config7));
997
/* Setup sequence done by the bootloader */
998
static void n8x0_boot_init(void *opaque)
1000
struct n800_s *s = (struct n800_s *) opaque;
1004
#define omap_writel(addr, val) \
1006
cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
1008
omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
1009
omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
1010
omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
1011
omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
1012
omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
1013
omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
1014
omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
1015
omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
1016
omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
1017
omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
1018
omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
1019
omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
1020
omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
1021
omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
1022
omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
1023
omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
1024
omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
1025
omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
1026
omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
1027
omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
1028
omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
1029
omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
1030
omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
1031
omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1032
omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1033
omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1034
omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1035
omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1036
omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1037
omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1038
omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1039
omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1040
omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1041
omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1042
omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1043
(0x78 << 12) | (6 << 8));
1044
omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1050
n800_dss_init(&s->blizzard);
1053
s->mpu->cpu->env.GE = 0x5;
1055
/* If the machine has a slided keyboard, open it */
1057
qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO));
1060
#define OMAP_TAG_NOKIA_BT 0x4e01
1061
#define OMAP_TAG_WLAN_CX3110X 0x4e02
1062
#define OMAP_TAG_CBUS 0x4e03
1063
#define OMAP_TAG_EM_ASIC_BB5 0x4e04
1065
static struct omap_gpiosw_info_s {
1069
} n800_gpiosw_info[] = {
1071
"bat_cover", N800_BAT_COVER_GPIO,
1072
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1074
"cam_act", N800_CAM_ACT_GPIO,
1075
OMAP_GPIOSW_TYPE_ACTIVITY,
1077
"cam_turn", N800_CAM_TURN_GPIO,
1078
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1080
"headphone", N8X0_HEADPHONE_GPIO,
1081
OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1084
}, n810_gpiosw_info[] = {
1086
"gps_reset", N810_GPS_RESET_GPIO,
1087
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1089
"gps_wakeup", N810_GPS_WAKEUP_GPIO,
1090
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1092
"headphone", N8X0_HEADPHONE_GPIO,
1093
OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1095
"kb_lock", N810_KB_LOCK_GPIO,
1096
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1098
"sleepx_led", N810_SLEEPX_LED_GPIO,
1099
OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1101
"slide", N810_SLIDE_GPIO,
1102
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1107
static struct omap_partition_info_s {
1112
} n800_part_info[] = {
1113
{ 0x00000000, 0x00020000, 0x3, "bootloader" },
1114
{ 0x00020000, 0x00060000, 0x0, "config" },
1115
{ 0x00080000, 0x00200000, 0x0, "kernel" },
1116
{ 0x00280000, 0x00200000, 0x3, "initfs" },
1117
{ 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1120
}, n810_part_info[] = {
1121
{ 0x00000000, 0x00020000, 0x3, "bootloader" },
1122
{ 0x00020000, 0x00060000, 0x0, "config" },
1123
{ 0x00080000, 0x00220000, 0x0, "kernel" },
1124
{ 0x002a0000, 0x00400000, 0x0, "initfs" },
1125
{ 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1130
static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1132
static int n8x0_atag_setup(void *p, int model)
1137
struct omap_gpiosw_info_s *gpiosw;
1138
struct omap_partition_info_s *partition;
1143
stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1144
stw_raw(w ++, 4); /* u16 len */
1145
stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1149
stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1150
stw_raw(w ++, 4); /* u16 len */
1151
stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
1152
stw_raw(w ++, 115200); /* u32 console_speed */
1155
stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1156
stw_raw(w ++, 36); /* u16 len */
1157
strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1159
strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1161
stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1162
stw_raw(w ++, 24); /* u8 data_lines */
1164
stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1165
stw_raw(w ++, 8); /* u16 len */
1166
stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1167
stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1168
stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1171
stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1172
stw_raw(w ++, 4); /* u16 len */
1173
stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1174
stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1176
gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1177
for (; gpiosw->name; gpiosw ++) {
1178
stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1179
stw_raw(w ++, 20); /* u16 len */
1180
strcpy((void *) w, gpiosw->name); /* char name[12] */
1182
stw_raw(w ++, gpiosw->line); /* u16 gpio */
1183
stw_raw(w ++, gpiosw->type);
1188
stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1189
stw_raw(w ++, 12); /* u16 len */
1191
stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
1192
stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1193
stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1194
stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1195
stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1196
memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
1198
stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1201
stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1202
stw_raw(w ++, 8); /* u16 len */
1203
stw_raw(w ++, 0x25); /* u8 chip_type */
1204
stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1205
stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1206
stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1208
stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1209
stw_raw(w ++, 16); /* u16 len */
1211
stw_raw(w ++, 0x23f); /* unsigned flags */
1212
stw_raw(w ++, -1); /* s16 power_pin */
1213
stw_raw(w ++, -1); /* s16 switch_pin */
1214
stw_raw(w ++, -1); /* s16 wp_pin */
1215
stw_raw(w ++, 0x240); /* unsigned flags */
1216
stw_raw(w ++, 0xc000); /* s16 power_pin */
1217
stw_raw(w ++, 0x0248); /* s16 switch_pin */
1218
stw_raw(w ++, 0xc000); /* s16 wp_pin */
1220
stw_raw(w ++, 0xf); /* unsigned flags */
1221
stw_raw(w ++, -1); /* s16 power_pin */
1222
stw_raw(w ++, -1); /* s16 switch_pin */
1223
stw_raw(w ++, -1); /* s16 wp_pin */
1224
stw_raw(w ++, 0); /* unsigned flags */
1225
stw_raw(w ++, 0); /* s16 power_pin */
1226
stw_raw(w ++, 0); /* s16 switch_pin */
1227
stw_raw(w ++, 0); /* s16 wp_pin */
1230
stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1231
stw_raw(w ++, 4); /* u16 len */
1232
stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
1235
partition = (model == 810) ? n810_part_info : n800_part_info;
1236
for (; partition->name; partition ++) {
1237
stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1238
stw_raw(w ++, 28); /* u16 len */
1239
strcpy((void *) w, partition->name); /* char name[16] */
1240
l = (void *) (w + 8);
1241
stl_raw(l ++, partition->size); /* unsigned int size */
1242
stl_raw(l ++, partition->offset); /* unsigned int offset */
1243
stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1247
stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1248
stw_raw(w ++, 12); /* u16 len */
1250
strcpy((void *) w, "por"); /* char reason_str[12] */
1251
strcpy((void *) w, "charger"); /* char reason_str[12] */
1252
strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1253
strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1254
strcpy((void *) w, "mbus"); /* char reason_str[12] */
1255
strcpy((void *) w, "unknown"); /* char reason_str[12] */
1256
strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1257
strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1258
strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1259
strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1261
strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1265
tag = (model == 810) ? "RX-44" : "RX-34";
1266
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1267
stw_raw(w ++, 24); /* u16 len */
1268
strcpy((void *) w, "product"); /* char component[12] */
1270
strcpy((void *) w, tag); /* char version[12] */
1273
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1274
stw_raw(w ++, 24); /* u16 len */
1275
strcpy((void *) w, "hw-build"); /* char component[12] */
1277
strcpy((void *) w, "QEMU ");
1278
pstrcat((void *) w, 12, qemu_get_version()); /* char version[12] */
1281
tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1282
stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1283
stw_raw(w ++, 24); /* u16 len */
1284
strcpy((void *) w, "nolo"); /* char component[12] */
1286
strcpy((void *) w, tag); /* char version[12] */
1289
return (void *) w - p;
1292
static int n800_atag_setup(const struct arm_boot_info *info, void *p)
1294
return n8x0_atag_setup(p, 800);
1297
static int n810_atag_setup(const struct arm_boot_info *info, void *p)
1299
return n8x0_atag_setup(p, 810);
1302
static void n8x0_init(QEMUMachineInitArgs *args,
1303
struct arm_boot_info *binfo, int model)
1305
MemoryRegion *sysmem = get_system_memory();
1306
struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
1307
int sdram_size = binfo->ram_size;
1310
s->mpu = omap2420_mpu_init(sysmem, sdram_size, args->cpu_model);
1312
/* Setup peripherals
1314
* Believed external peripherals layout in the N810:
1319
* Conexant cx3110x (WLAN)
1320
* optional: pc2400m (WiMAX)
1322
* TLV320AIC33 (audio codec)
1323
* TCM825x (camera by Toshiba)
1324
* lp5521 (clever LEDs)
1325
* tsl2563 (light sensor, hwmon, model 7, rev. 0)
1326
* lm8323 (keypad, manf 00, rev 04)
1328
* tmp105 (temperature sensor, hwmon)
1330
* (somewhere on i2c - maybe N800-only)
1331
* tea5761 (FM tuner)
1334
* (some serial port)
1335
* csr41814 (Bluetooth)
1341
n800_tsc_kbd_setup(s);
1342
else if (model == 810) {
1350
if (usb_enabled(false)) {
1354
if (args->kernel_filename) {
1355
/* Or at the linux loader. */
1356
binfo->kernel_filename = args->kernel_filename;
1357
binfo->kernel_cmdline = args->kernel_cmdline;
1358
binfo->initrd_filename = args->initrd_filename;
1359
arm_load_kernel(s->mpu->cpu, binfo);
1361
qemu_register_reset(n8x0_boot_init, s);
1364
if (option_rom[0].name &&
1365
(args->boot_device[0] == 'n' || !args->kernel_filename)) {
1367
uint8_t nolo_tags[0x10000];
1368
/* No, wait, better start at the ROM. */
1369
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
1371
/* This is intended for loading the `secondary.bin' program from
1372
* Nokia images (the NOLO bootloader). The entry point seems
1373
* to be at OMAP2_Q2_BASE + 0x400000.
1375
* The `2nd.bin' files contain some kind of earlier boot code and
1376
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
1378
* The code above is for loading the `zImage' file from Nokia
1380
rom_size = load_image_targphys(option_rom[0].name,
1381
OMAP2_Q2_BASE + 0x400000,
1382
sdram_size - 0x400000);
1383
printf("%i bytes of image loaded\n", rom_size);
1385
n800_setup_nolo_tags(nolo_tags);
1386
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
1388
/* FIXME: We shouldn't really be doing this here. The LCD controller
1389
will set the size once configured, so this just sets an initial
1390
size until the guest activates the display. */
1391
ds = get_displaystate();
1392
ds->surface = qemu_resize_displaysurface(ds, 800, 480);
1396
static struct arm_boot_info n800_binfo = {
1397
.loader_start = OMAP2_Q2_BASE,
1398
/* Actually two chips of 0x4000000 bytes each */
1399
.ram_size = 0x08000000,
1401
.atag_board = n800_atag_setup,
1404
static struct arm_boot_info n810_binfo = {
1405
.loader_start = OMAP2_Q2_BASE,
1406
/* Actually two chips of 0x4000000 bytes each */
1407
.ram_size = 0x08000000,
1408
/* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1409
* used by some older versions of the bootloader and 5555 is used
1410
* instead (including versions that shipped with many devices). */
1412
.atag_board = n810_atag_setup,
1415
static void n800_init(QEMUMachineInitArgs *args)
1417
return n8x0_init(args, &n800_binfo, 800);
1420
static void n810_init(QEMUMachineInitArgs *args)
1422
return n8x0_init(args, &n810_binfo, 810);
1425
static QEMUMachine n800_machine = {
1427
.desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1429
DEFAULT_MACHINE_OPTIONS,
1432
static QEMUMachine n810_machine = {
1434
.desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1436
DEFAULT_MACHINE_OPTIONS,
1439
static void nseries_register_types(void)
1441
type_register_static(&mipid_info);
1444
static void nseries_machine_init(void)
1446
qemu_register_machine(&n800_machine);
1447
qemu_register_machine(&n810_machine);
1450
type_init(nseries_register_types);
1451
machine_init(nseries_machine_init);