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* zaphfc.h - Dahdi driver for HFC-S PCI A based ISDN BRI cards
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* Dahdi port by Jose A. Deniz <odicha@hotmail.com>
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* Copyright (C) 2009 Jose A. Deniz
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* Copyright (C) 2006 headissue GmbH; Jens Wilke
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* Copyright (C) 2004 Daniele Orlandi
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* Copyright (C) 2002, 2003, 2004, Junghanns.NET GmbH
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* Jens Wilke <jw_vzaphfc@headissue.com>
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* Orginal author of this code is
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* Daniele "Vihai" Orlandi <daniele@orlandi.com>
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* Major rewrite of the driver made by
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* Klaus-Peter Junghanns <kpj@junghanns.net>
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* This program is free software and may be modified and
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* distributed under the terms of the GNU Public License.
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#define hfc_DRIVER_NAME "vzaphfc"
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#define hfc_DRIVER_PREFIX hfc_DRIVER_NAME ": "
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#define hfc_DRIVER_DESCR "HFC-S PCI A ISDN"
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#define hfc_DRIVER_VERSION "1.42"
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#define hfc_DRIVER_STRING hfc_DRIVER_DESCR " (V" hfc_DRIVER_VERSION ")"
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#define hfc_MAX_BOARDS 32
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#define PCI_DMA_32BIT 0x00000000ffffffffULL
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#ifndef PCI_VENDOR_ID_SITECOM
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#define PCI_VENDOR_ID_SITECOM 0x182D
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#ifndef PCI_DEVICE_ID_SITECOM_3069
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#define PCI_DEVICE_ID_SITECOM_3069 0x3069
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#define hfc_RESET_DELAY 20
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#define hfc_CLKDEL_TE 0x0f /* CLKDEL in TE mode */
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#define hfc_CLKDEL_NT 0x6c /* CLKDEL in NT mode */
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/* PCI memory mapped I/O */
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#define hfc_PCI_MEM_SIZE 0x0100
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#define hfc_PCI_MWBA 0x80
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/* GCI/IOM bus monitor registers */
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#define hfc_MON1_D 0x28
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#define hfc_MON2_D 0x2C
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/* GCI/IOM bus timeslot registers */
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#define hfc_B1_SSL 0x80
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#define hfc_B2_SSL 0x84
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#define hfc_AUX1_SSL 0x88
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#define hfc_AUX2_SSL 0x8C
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#define hfc_B1_RSL 0x90
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#define hfc_B2_RSL 0x94
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#define hfc_AUX1_RSL 0x98
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#define hfc_AUX2_RSL 0x9C
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/* GCI/IOM bus data registers */
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#define hfc_AUX1_D 0xA8
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#define hfc_AUX2_D 0xAC
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/* GCI/IOM bus configuration registers */
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#define hfc_MST_EMOD 0xB4
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#define hfc_MST_MODE 0xB8
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#define hfc_CONNECT 0xBC
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/* Interrupt and status registers */
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#define hfc_FIFO_EN 0x44
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#define hfc_B_MODE 0x4C
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#define hfc_CHIP_ID 0x58
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#define hfc_INT_M1 0x68
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#define hfc_INT_M2 0x6C
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#define hfc_INT_S1 0x78
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#define hfc_INT_S2 0x7C
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#define hfc_STATUS 0x70
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/* S/T section registers */
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#define hfc_STATES 0xC0
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#define hfc_SCTRL 0xC4
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#define hfc_SCTRL_E 0xC8
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#define hfc_SCTRL_R 0xCC
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#define hfc_CLKDEL 0xDC
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#define hfc_B1_REC 0xF0
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#define hfc_B1_SEND 0xF0
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#define hfc_B2_REC 0xF4
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#define hfc_B2_SEND 0xF4
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#define hfc_D_REC 0xF8
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#define hfc_D_SEND 0xF8
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#define hfc_E_REC 0xFC
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/* Bits and values in various HFC PCI registers */
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/* bits in status register (READ) */
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#define hfc_STATUS_PCI_PROC 0x02
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#define hfc_STATUS_NBUSY 0x04
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#define hfc_STATUS_TIMER_ELAP 0x10
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#define hfc_STATUS_STATINT 0x20
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#define hfc_STATUS_FRAMEINT 0x40
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#define hfc_STATUS_ANYINT 0x80
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/* bits in CTMT (Write) */
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#define hfc_CTMT_TRANSB1 0x01
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#define hfc_CTMT_TRANSB2 0x02
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#define hfc_CTMT_TIMER_CLEAR 0x80
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#define hfc_CTMT_TIMER_MASK 0x1C
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#define hfc_CTMT_TIMER_3_125 (0x01 << 2)
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#define hfc_CTMT_TIMER_6_25 (0x02 << 2)
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#define hfc_CTMT_TIMER_12_5 (0x03 << 2)
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#define hfc_CTMT_TIMER_25 (0x04 << 2)
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#define hfc_CTMT_TIMER_50 (0x05 << 2)
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#define hfc_CTMT_TIMER_400 (0x06 << 2)
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#define hfc_CTMT_TIMER_800 (0x07 << 2)
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#define hfc_CTMT_AUTO_TIMER 0x20
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/* bits in CIRM (Write) */
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#define hfc_CIRM_AUX_MSK 0x07
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#define hfc_CIRM_RESET 0x08
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#define hfc_CIRM_B1_REV 0x40
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#define hfc_CIRM_B2_REV 0x80
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/* bits in INT_M1 and INT_S1 */
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#define hfc_INTS_B1TRANS 0x01
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#define hfc_INTS_B2TRANS 0x02
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#define hfc_INTS_DTRANS 0x04
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#define hfc_INTS_B1REC 0x08
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#define hfc_INTS_B2REC 0x10
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#define hfc_INTS_DREC 0x20
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#define hfc_INTS_L1STATE 0x40
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#define hfc_INTS_TIMER 0x80
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#define hfc_M2_PROC_TRANS 0x01
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#define hfc_M2_GCI_I_CHG 0x02
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#define hfc_M2_GCI_MON_REC 0x04
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#define hfc_M2_IRQ_ENABLE 0x08
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#define hfc_M2_PMESEL 0x80
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#define hfc_STATES_STATE_MASK 0x0F
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#define hfc_STATES_LOAD_STATE 0x10
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#define hfc_STATES_ACTIVATE 0x20
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#define hfc_STATES_DO_ACTION 0x40
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#define hfc_STATES_NT_G2_G3 0x80
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/* bits in HFCD_MST_MODE */
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#define hfc_MST_MODE_MASTER 0x01
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#define hfc_MST_MODE_SLAVE 0x00
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/* remaining bits are for codecs control */
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/* bits in HFCD_SCTRL */
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#define hfc_SCTRL_B1_ENA 0x01
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#define hfc_SCTRL_B2_ENA 0x02
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#define hfc_SCTRL_MODE_TE 0x00
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#define hfc_SCTRL_MODE_NT 0x04
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#define hfc_SCTRL_LOW_PRIO 0x08
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#define hfc_SCTRL_SQ_ENA 0x10
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#define hfc_SCTRL_TEST 0x20
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#define hfc_SCTRL_NONE_CAP 0x40
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#define hfc_SCTRL_PWR_DOWN 0x80
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/* bits in SCTRL_E */
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#define hfc_SCTRL_E_AUTO_AWAKE 0x01
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#define hfc_SCTRL_E_DBIT_1 0x04
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#define hfc_SCTRL_E_IGNORE_COL 0x08
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#define hfc_SCTRL_E_CHG_B1_B2 0x80
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/* bits in SCTRL_R */
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#define hfc_SCTRL_R_B1_ENA 0x01
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#define hfc_SCTRL_R_B2_ENA 0x02
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/* bits in FIFO_EN register */
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#define hfc_FIFOEN_B1TX 0x01
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#define hfc_FIFOEN_B1RX 0x02
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#define hfc_FIFOEN_B2TX 0x04
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#define hfc_FIFOEN_B2RX 0x08
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#define hfc_FIFOEN_DTX 0x10
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#define hfc_FIFOEN_DRX 0x20
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#define hfc_FIFOEN_B1 (hfc_FIFOEN_B1TX|hfc_FIFOEN_B1RX)
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#define hfc_FIFOEN_B2 (hfc_FIFOEN_B2TX|hfc_FIFOEN_B2RX)
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#define hfc_FIFOEN_D (hfc_FIFOEN_DTX|hfc_FIFOEN_DRX)
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/* bits in the CONNECT register */
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#define hfc_CONNECT_B1_HFC_from_ST 0x00
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#define hfc_CONNECT_B1_HFC_from_GCI 0x01
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#define hfc_CONNECT_B1_ST_from_HFC 0x00
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#define hfc_CONNECT_B1_ST_from_GCI 0x02
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#define hfc_CONNECT_B1_GCI_from_HFC 0x00
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#define hfc_CONNECT_B1_GCI_from_ST 0x04
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#define hfc_CONNECT_B2_HFC_from_ST 0x00
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#define hfc_CONNECT_B2_HFC_from_GCI 0x08
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#define hfc_CONNECT_B2_ST_from_HFC 0x00
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#define hfc_CONNECT_B2_ST_from_GCI 0x10
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#define hfc_CONNECT_B2_GCI_from_HFC 0x00
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#define hfc_CONNECT_B2_GCI_from_ST 0x20
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/* bits in the TRM register */
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#define hfc_TRM_TRANS_INT_00 0x00
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#define hfc_TRM_TRANS_INT_01 0x01
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#define hfc_TRM_TRANS_INT_10 0x02
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#define hfc_TRM_TRANS_INT_11 0x04
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#define hfc_TRM_ECHO 0x20
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#define hfc_TRM_B1_PLUS_B2 0x40
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#define hfc_TRM_IOM_TEST_LOOP 0x80
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/* bits in the __SSL and __RSL registers */
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#define hfc_SRSL_STIO 0x40
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#define hfc_SRSL_ENABLE 0x80
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#define hfc_SRCL_SLOT_MASK 0x1f
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/* FIFO memory definitions */
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#define hfc_FIFO_SIZE 0x8000
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#define hfc_UGLY_FRAMEBUF 0x2000
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#define hfc_TX_FIFO_PRELOAD (DAHDI_CHUNKSIZE + 2)
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#define hfc_RX_FIFO_PRELOAD 4
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#define hfc_HDLC_BUF_LEN 32
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/* arbitrary, just the max # of byts we will send to DAHDI per call */
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/* NOTE: FIFO pointers are not declared volatile because accesses to the
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* FIFOs are inherently safe.
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extern int debug_level;
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struct hfc_chan_simplex {
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struct hfc_chan_duplex *chan;
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u8 zaptel_buffer[DAHDI_CHUNKSIZE];
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u8 ugly_framebuf[hfc_UGLY_FRAMEBUF];
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int ugly_framebuf_size;
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u16 ugly_framebuf_off;
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void *z1_base, *z2_base;
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unsigned long long frames;
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unsigned long long bytes;
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unsigned long long fifo_full;
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unsigned long long crc;
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unsigned long long fifo_underrun;
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enum hfc_chan_status {
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struct hfc_chan_duplex {
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struct hfc_card *card;
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enum hfc_chan_status status;
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unsigned short protocol;
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struct hfc_chan_simplex rx;
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struct hfc_chan_simplex tx;
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typedef struct hfc_card {
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struct pci_dev *pcidev;
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struct dahdi_hfc *ztdev;
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struct proc_dir_entry *proc_dir;
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char proc_dir_name[32];
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struct proc_dir_entry *proc_info;
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struct proc_dir_entry *proc_fifos;
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struct proc_dir_entry *proc_bufs;
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unsigned long io_bus_mem;
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void __iomem *io_mem;
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dma_addr_t fifo_bus_mem;
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int sync_loss_reported;
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int ignore_first_timer_interrupt;
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struct hfc_chan_duplex chans[3];
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unsigned char *pci_io;
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void *fifomem; /* start of the shared mem */
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unsigned int pcidevfn;
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unsigned char cardno;
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struct hfc_card *next;
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typedef struct dahdi_hfc {
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unsigned int usecount;
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struct dahdi_span span;
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struct dahdi_chan chans[3];
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struct dahdi_chan *_chans[3];
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struct hfc_card *card;
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/* pointer to the signalling channel for this span */
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struct dahdi_chan *sigchan;
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/* nonzero means we're in the middle of sending an HDLC frame */
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/* hdlc_hard_xmit() increments, hdlc_tx_frame() decrements */
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atomic_t hdlc_pending;
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static inline u8 hfc_inb(struct hfc_card *card, int offset)
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return readb(card->io_mem + offset);
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static inline void hfc_outb(struct hfc_card *card, int offset, u8 value)
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writeb(value, card->io_mem + offset);
added
removed
drivers/dahdi/zaphfc/zaphfc.h
