61
nv50_xv_image_put(ScrnInfoPtr pScrn,
62
struct nouveau_bo *src, int src_offset, int src_offset2,
63
int id, int src_pitch, BoxPtr dstBox,
64
int x1, int y1, int x2, int y2,
65
uint16_t width, uint16_t height,
66
uint16_t src_w, uint16_t src_h,
67
uint16_t drw_w, uint16_t drw_h,
68
RegionPtr clipBoxes, PixmapPtr ppix,
61
nv50_xv_state_emit(PixmapPtr ppix, int id, struct nouveau_bo *src,
62
int packed_y, int uv, int src_w, int src_h)
64
ScrnInfoPtr pScrn = xf86Screens[ppix->drawable.pScreen->myNum];
71
65
NVPtr pNv = NVPTR(pScrn);
72
66
struct nouveau_channel *chan = pNv->chan;
73
67
struct nouveau_grobj *tesla = pNv->Nv3D;
78
if (!nv50_xv_check_image_put(ppix))
68
const unsigned shd_flags = NOUVEAU_BO_RD | NOUVEAU_BO_VRAM;
69
const unsigned tcb_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
71
WAIT_RING (chan, 256);
81
72
BEGIN_RING(chan, tesla, NV50TCL_RT_ADDRESS_HIGH(0), 5);
82
73
OUT_PIXMAPh(chan, ppix, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
83
74
OUT_PIXMAPl(chan, ppix, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
97
88
BEGIN_RING(chan, tesla, NV50TCL_BLEND_ENABLE(0), 1);
98
89
OUT_RING (chan, 0);
91
BEGIN_RING(chan, tesla, NV50TCL_TIC_ADDRESS_HIGH, 3);
92
OUT_RELOCh(chan, pNv->tesla_scratch, TIC_OFFSET, tcb_flags);
93
OUT_RELOCl(chan, pNv->tesla_scratch, TIC_OFFSET, tcb_flags);
94
OUT_RING (chan, 0x00000800);
95
BEGIN_RING(chan, tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
96
OUT_RELOCh(chan, pNv->tesla_scratch, TIC_OFFSET, tcb_flags);
97
OUT_RELOCl(chan, pNv->tesla_scratch, TIC_OFFSET, tcb_flags);
98
OUT_RING (chan, (CB_TIC << NV50TCL_CB_DEF_SET_BUFFER_SHIFT) | 0x4000);
100
99
BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
101
100
OUT_RING (chan, CB_TIC);
102
101
BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, 16);
106
105
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
107
106
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
108
107
NV50TIC_0_0_FMT_8);
109
OUT_RELOCl(chan, src,
110
src_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
108
OUT_RELOCl(chan, src, packed_y, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
111
109
OUT_RING (chan, 0xd0005000);
112
110
OUT_RING (chan, 0x00300000);
113
111
OUT_RING (chan, src_w);
114
112
OUT_RING (chan, (1 << NV50TIC_0_5_DEPTH_SHIFT) | src_h);
115
113
OUT_RING (chan, 0x03000000);
116
OUT_RELOCh(chan, src,
117
src_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
114
OUT_RELOCh(chan, src, packed_y, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
118
115
OUT_RING (chan, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
119
116
NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
120
117
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
121
118
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
122
119
NV50TIC_0_0_FMT_8_8);
123
OUT_RELOCl(chan, src,
124
src_offset2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
120
OUT_RELOCl(chan, src, uv, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
125
121
OUT_RING (chan, 0xd0005000);
126
122
OUT_RING (chan, 0x00300000);
127
123
OUT_RING (chan, src_w >> 1);
128
124
OUT_RING (chan, (1 << NV50TIC_0_5_DEPTH_SHIFT) | (src_h >> 1));
129
125
OUT_RING (chan, 0x03000000);
130
OUT_RELOCh(chan, src,
131
src_offset2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
126
OUT_RELOCh(chan, src, uv, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
133
128
OUT_RING (chan, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
134
129
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
135
130
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
136
131
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
137
132
NV50TIC_0_0_FMT_8_8);
138
OUT_RELOCl(chan, src,
139
src_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
133
OUT_RELOCl(chan, src, packed_y, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
140
134
OUT_RING (chan, 0xd0005000);
141
135
OUT_RING (chan, 0x00300000);
142
136
OUT_RING (chan, src_w);
143
137
OUT_RING (chan, (1 << NV50TIC_0_5_DEPTH_SHIFT) | src_h);
144
138
OUT_RING (chan, 0x03000000);
145
OUT_RELOCh(chan, src,
146
src_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
139
OUT_RELOCh(chan, src, packed_y, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
147
140
OUT_RING (chan, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
148
141
NV50TIC_0_0_MAPR_C1 | NV50TIC_0_0_TYPER_UNORM |
149
142
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
150
143
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
151
144
NV50TIC_0_0_FMT_8_8_8_8);
152
OUT_RELOCl(chan, src,
153
src_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
145
OUT_RELOCl(chan, src, packed_y, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
154
146
OUT_RING (chan, 0xd0005000);
155
147
OUT_RING (chan, 0x00300000);
156
148
OUT_RING (chan, (src_w >> 1));
157
149
OUT_RING (chan, (1 << NV50TIC_0_5_DEPTH_SHIFT) | src_h);
158
150
OUT_RING (chan, 0x03000000);
159
OUT_RELOCh(chan, src,
160
src_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
151
OUT_RELOCh(chan, src, packed_y, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
154
BEGIN_RING(chan, tesla, NV50TCL_TSC_ADDRESS_HIGH, 3);
155
OUT_RELOCh(chan, pNv->tesla_scratch, TSC_OFFSET, tcb_flags);
156
OUT_RELOCl(chan, pNv->tesla_scratch, TSC_OFFSET, tcb_flags);
157
OUT_RING (chan, 0x00000000);
158
BEGIN_RING(chan, tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
159
OUT_RELOCh(chan, pNv->tesla_scratch, TSC_OFFSET, tcb_flags);
160
OUT_RELOCl(chan, pNv->tesla_scratch, TSC_OFFSET, tcb_flags);
161
OUT_RING (chan, (CB_TSC << NV50TCL_CB_DEF_SET_BUFFER_SHIFT) | 0x4000);
163
162
BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
164
163
OUT_RING (chan, CB_TSC);
165
164
BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, 16);
188
187
OUT_RING (chan, 0x00000000);
189
188
OUT_RING (chan, 0x00000000);
190
BEGIN_RING(chan, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
191
OUT_RELOCh(chan, pNv->tesla_scratch, PVP_OFFSET, shd_flags);
192
OUT_RELOCl(chan, pNv->tesla_scratch, PVP_OFFSET, shd_flags);
193
BEGIN_RING(chan, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
194
OUT_RELOCh(chan, pNv->tesla_scratch, PFP_OFFSET, shd_flags);
195
OUT_RELOCl(chan, pNv->tesla_scratch, PFP_OFFSET, shd_flags);
191
196
BEGIN_RING(chan, tesla, NV50TCL_FP_START_ID, 1);
192
197
OUT_RING (chan, PFP_NV12);
199
204
BEGIN_RING(chan, tesla, 0x1458, 1);
200
205
OUT_RING (chan, 0x203);
210
nv50_xv_image_put(ScrnInfoPtr pScrn,
211
struct nouveau_bo *src, int packed_y, int uv,
212
int id, int src_pitch, BoxPtr dstBox,
213
int x1, int y1, int x2, int y2,
214
uint16_t width, uint16_t height,
215
uint16_t src_w, uint16_t src_h,
216
uint16_t drw_w, uint16_t drw_h,
217
RegionPtr clipBoxes, PixmapPtr ppix,
220
NVPtr pNv = NVPTR(pScrn);
221
struct nouveau_channel *chan = pNv->chan;
222
struct nouveau_grobj *tesla = pNv->Nv3D;
223
float X1, X2, Y1, Y2;
227
if (!nv50_xv_check_image_put(ppix))
229
nv50_xv_state_emit(ppix, id, src, packed_y, uv, src_w, src_h);
202
231
/* These are fixed point values in the 16.16 format. */
203
232
X1 = (float)(x1>>16)+(float)(x1&0xFFFF)/(float)0x10000;
204
233
Y1 = (float)(y1>>16)+(float)(y1&0xFFFF)/(float)0x10000;
205
234
X2 = (float)(x2>>16)+(float)(x2&0xFFFF)/(float)0x10000;
206
235
Y2 = (float)(y2>>16)+(float)(y2&0xFFFF)/(float)0x10000;
208
BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
209
OUT_RING (chan, NV50TCL_VERTEX_BEGIN_QUADS);
211
237
pbox = REGION_RECTS(clipBoxes);
212
238
nbox = REGION_NUM_RECTS(clipBoxes);
225
251
ty1 = ty1 / src_h;
226
252
ty2 = ty2 / src_h;
254
if (AVAIL_RING(chan) < 64) {
255
nv50_xv_state_emit(ppix, id, src, packed_y, uv,
259
BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
260
OUT_RING (chan, NV50TCL_VERTEX_BEGIN_QUADS);
228
261
VTX2s(pNv, tx1, ty1, tx1, ty1, sx1, sy1);
229
262
VTX2s(pNv, tx2, ty1, tx2, ty1, sx2, sy1);
230
263
VTX2s(pNv, tx2, ty2, tx2, ty2, sx2, sy2);
231
264
VTX2s(pNv, tx1, ty2, tx1, ty2, sx1, sy2);
265
BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
236
BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
239
271
FIRE_RING (chan);