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RIVA_HW_STATE *state = &pNv->ModeReg;
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NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
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struct pll_lims pll_lim;
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int NM1 = 0xbeef, NM2 = 0, log2P = 0, VClk = 0;
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bool using_two_pll_stages = false;
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/* nvidia uses 0x11f as bogus data when running in single stage mode */
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int NM1 = 0xbeef, NM2 = 0x11f, log2P = 0, VClk = 0;
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uint32_t g70_pll_special_bits = 0;
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bool nv4x_single_stage_pll_mode = false;
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uint8_t arbitration0;
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uint16_t arbitration1;
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if (get_pll_limits(pScrn, nv_crtc->head ? VPLL2 : VPLL1, &pll_lim))
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if (pNv->twoStagePLL || pNv->NVArch == 0x30 || pNv->NVArch == 0x35) {
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if (dot_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
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nv4x_single_stage_pll_mode = true;
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/* Turn the second set of divider and multiplier off */
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/* Bogus data, the same nvidia uses */
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VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
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VClk = getMNP_double(pScrn, &pll_lim, dot_clock, &NM1, &NM2, &log2P);
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/* for newer nv4x the blob uses only the first stage of the vpll below a
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* certain clock. for a certain nv4b this is 150MHz. since the max
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* output frequency of the first stage for this card is 300MHz, it is
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* assumed the threshold is given by vco1 maxfreq/2
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/* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
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* not 8, others unknown), the blob always uses both plls. no problem
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* has yet been observed in allowing the use a single stage pll on all
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* nv43 however. the behaviour of single stage use is untested on nv40
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if ((pNv->two_reg_pll || pNv->NVArch == 0x30 || pNv->NVArch == 0x35) &&
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(pNv->NVArch < 0x41 || dot_clock > (pll_lim.vco1.maxfreq / 2))) {
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using_two_pll_stages = true;
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VClk = getMNP_double(pScrn, &pll_lim, dot_clock, &NM1, &NM2, &log2P);
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239
VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
235
/* Are these all the (relevant) G70 cards? */
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if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
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/* This is a big guess, but should be reasonable until we can narrow it down. */
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/* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
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if (nv4x_single_stage_pll_mode)
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g70_pll_special_bits = 0x1;
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g70_pll_special_bits = 0x3;
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/* magic bits set by the blob (but not the bios), purpose unknown */
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if (pNv->NVArch == 0x46 || pNv->NVArch == 0x49 || pNv->NVArch == 0x4b)
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g70_pll_special_bits = (using_two_pll_stages ? 0xc : 0x4);
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if (pNv->NVArch == 0x30 || pNv->NVArch == 0x35)
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/* See nvregisters.xml for details. */
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regp->vpll_a = (NM2 & (0x18 << 8)) << 13 | (NM2 & (0x7 << 8)) << 11 | log2P << 16 | NV30_RAMDAC_ENABLE_VCO2 | (NM2 & 7) << 4 | NM1;
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regp->vpll_a = g70_pll_special_bits << 30 | log2P << 16 | NM1;
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regp->vpll_a = g70_pll_special_bits << 28 | log2P << 16 | NM1;
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250
regp->vpll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
252
if (nv4x_single_stage_pll_mode) {
253
if (nv_crtc->head == 0)
254
state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
256
state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
258
if (nv_crtc->head == 0)
259
state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
261
state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
264
/* The NV40 seems to have more similarities to NV3x than other NV4x */
265
if (pNv->NVArch < 0x41)
266
state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL |
267
NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
268
252
/* The blob uses this always, so let's do the same */
269
253
if (pNv->Architecture == NV_ARCH_40)
270
254
state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
272
if (nv_crtc->head == 1) {
273
if (!nv4x_single_stage_pll_mode)
274
state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
276
state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
277
state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
279
if (!nv4x_single_stage_pll_mode)
280
state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
282
state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
283
state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
256
/* again nv40 and some nv43 act more like nv3x as described above */
257
if (pNv->NVArch < 0x41)
258
state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL |
259
NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
261
state->pllsel |= (nv_crtc->head ? NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2 |
262
NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2 :
263
NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL |
264
NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2);
266
if (pNv->NVArch >= 0x40) {
267
if (using_two_pll_stages)
268
state->reg580 &= (nv_crtc->head ? ~NV_RAMDAC_580_VPLL2_ACTIVE :
269
~NV_RAMDAC_580_VPLL1_ACTIVE);
271
state->reg580 |= (nv_crtc->head ? NV_RAMDAC_580_VPLL2_ACTIVE :
272
NV_RAMDAC_580_VPLL1_ACTIVE);
286
if ((!pNv->twoStagePLL && pNv->NVArch != 0x30 && pNv->NVArch != 0x35) || nv4x_single_stage_pll_mode)
275
if (using_two_pll_stages)
276
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
287
278
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
289
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
291
280
if (pNv->Architecture < NV_ARCH_30)
292
281
nv4_10UpdateArbitrationSettings(pScrn, VClk, pScrn->bitsPerPixel, &arbitration0, &arbitration1);