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/* Copyright (c) 2002, Steinar Haugen
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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/* $Id: iom8535.h 2235 2011-03-17 04:13:14Z arcanum $ */
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/* avr/iom8535.h - definitions for ATmega8535 */
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#ifndef _AVR_IOM8535_H_
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#define _AVR_IOM8535_H_ 1
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/* This file should only be included from <avr/io.h>, never directly. */
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# error "Include <avr/io.h> instead of this file."
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# define _AVR_IOXXX_H_ "iom8535.h"
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# error "Attempt to include more than one <avr/ioXXX.h> file."
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/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
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#define TWBR _SFR_IO8(0x00)
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#define TWSR _SFR_IO8(0x01)
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#define TWAR _SFR_IO8(0x02)
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#define TWDR _SFR_IO8(0x03)
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/* ADC Data register */
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#define ADC _SFR_IO16(0x04)
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#define ADCW _SFR_IO16(0x04)
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#define ADCL _SFR_IO8(0x04)
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#define ADCH _SFR_IO8(0x05)
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/* ADC Control and Status Register */
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#define ADCSRA _SFR_IO8(0x06)
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#define ADMUX _SFR_IO8(0x07)
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/* Analog Comparator Control and Status Register */
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#define ACSR _SFR_IO8(0x08)
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/* USART Baud Rate Register */
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#define UBRRL _SFR_IO8(0x09)
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/* USART Control and Status Register B */
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#define UCSRB _SFR_IO8(0x0A)
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/* USART Control and Status Register A */
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#define UCSRA _SFR_IO8(0x0B)
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/* USART I/O Data Register */
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#define UDR _SFR_IO8(0x0C)
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/* SPI Control Register */
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#define SPCR _SFR_IO8(0x0D)
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/* SPI Status Register */
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#define SPSR _SFR_IO8(0x0E)
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/* SPI I/O Data Register */
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#define SPDR _SFR_IO8(0x0F)
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/* Input Pins, Port D */
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#define PIND _SFR_IO8(0x10)
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/* Data Direction Register, Port D */
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#define DDRD _SFR_IO8(0x11)
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/* Data Register, Port D */
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#define PORTD _SFR_IO8(0x12)
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/* Input Pins, Port C */
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#define PINC _SFR_IO8(0x13)
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/* Data Direction Register, Port C */
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#define DDRC _SFR_IO8(0x14)
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/* Data Register, Port C */
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#define PORTC _SFR_IO8(0x15)
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/* Input Pins, Port B */
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#define PINB _SFR_IO8(0x16)
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/* Data Direction Register, Port B */
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#define DDRB _SFR_IO8(0x17)
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/* Data Register, Port B */
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#define PORTB _SFR_IO8(0x18)
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/* Input Pins, Port A */
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#define PINA _SFR_IO8(0x19)
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/* Data Direction Register, Port A */
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#define DDRA _SFR_IO8(0x1A)
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/* Data Register, Port A */
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#define PORTA _SFR_IO8(0x1B)
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/* EEPROM Control Register */
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#define EECR _SFR_IO8(0x1C)
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/* EEPROM Data Register */
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#define EEDR _SFR_IO8(0x1D)
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/* EEPROM Address Register */
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#define EEAR _SFR_IO16(0x1E)
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#define EEARL _SFR_IO8(0x1E)
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#define EEARH _SFR_IO8(0x1F)
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/* USART Baud Rate Register HI */
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/* USART Control and Status Register C */
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#define UBRRH _SFR_IO8(0x20)
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/* Watchdog Timer Control Register */
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#define WDTCR _SFR_IO8(0x21)
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/* Asynchronous mode Status Register */
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#define ASSR _SFR_IO8(0x22)
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/* Timer/Counter2 Output Compare Register */
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#define OCR2 _SFR_IO8(0x23)
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/* Timer/Counter 2 */
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#define TCNT2 _SFR_IO8(0x24)
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/* Timer/Counter 2 Control Register */
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#define TCCR2 _SFR_IO8(0x25)
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/* T/C 1 Input Capture Register */
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#define ICR1 _SFR_IO16(0x26)
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#define ICR1L _SFR_IO8(0x26)
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#define ICR1H _SFR_IO8(0x27)
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/* Timer/Counter1 Output Compare Register B */
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#define OCR1B _SFR_IO16(0x28)
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#define OCR1BL _SFR_IO8(0x28)
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#define OCR1BH _SFR_IO8(0x29)
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/* Timer/Counter1 Output Compare Register A */
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#define OCR1A _SFR_IO16(0x2A)
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#define OCR1AL _SFR_IO8(0x2A)
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#define OCR1AH _SFR_IO8(0x2B)
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/* Timer/Counter 1 */
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#define TCNT1 _SFR_IO16(0x2C)
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#define TCNT1L _SFR_IO8(0x2C)
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#define TCNT1H _SFR_IO8(0x2D)
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/* Timer/Counter 1 Control and Status Register */
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#define TCCR1B _SFR_IO8(0x2E)
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/* Timer/Counter 1 Control Register */
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#define TCCR1A _SFR_IO8(0x2F)
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/* Special Function IO Register */
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#define SFIOR _SFR_IO8(0x30)
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/* Oscillator Calibration Register */
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#define OSCCAL _SFR_IO8(0x31)
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/* Timer/Counter 0 */
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#define TCNT0 _SFR_IO8(0x32)
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/* Timer/Counter 0 Control Register */
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#define TCCR0 _SFR_IO8(0x33)
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/* MCU Control and Status Register */
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#define MCUCSR _SFR_IO8(0x34)
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/* MCU Control Register */
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#define MCUCR _SFR_IO8(0x35)
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/* TWI Control Register */
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#define TWCR _SFR_IO8(0x36)
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/* Store Program Memory Control Register */
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#define SPMCR _SFR_IO8(0x37)
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/* Timer/Counter Interrupt Flag register */
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#define TIFR _SFR_IO8(0x38)
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/* Timer/Counter Interrupt MaSK register */
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#define TIMSK _SFR_IO8(0x39)
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/* General Interrupt Flag Register */
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#define GIFR _SFR_IO8(0x3A)
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/* General Interrupt MaSK register */
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#define GICR _SFR_IO8(0x3B)
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/* Timer/Counter 0 Output Compare Register */
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#define OCR0 _SFR_IO8(0x3C)
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/* Interrupt vectors */
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/* External Interrupt 0 */
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#define INT0_vect_num 1
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#define INT0_vect _VECTOR(1)
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#define SIG_INTERRUPT0 _VECTOR(1)
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/* External Interrupt 1 */
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#define INT1_vect_num 2
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#define INT1_vect _VECTOR(2)
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#define SIG_INTERRUPT1 _VECTOR(2)
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/* Timer/Counter2 Compare Match */
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#define TIMER2_COMP_vect_num 3
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#define TIMER2_COMP_vect _VECTOR(3)
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#define SIG_OUTPUT_COMPARE2 _VECTOR(3)
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/* Timer/Counter2 Overflow */
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#define TIMER2_OVF_vect_num 4
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#define TIMER2_OVF_vect _VECTOR(4)
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#define SIG_OVERFLOW2 _VECTOR(4)
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/* Timer/Counter1 Capture Event */
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#define TIMER1_CAPT_vect_num 5
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#define TIMER1_CAPT_vect _VECTOR(5)
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#define SIG_INPUT_CAPTURE1 _VECTOR(5)
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/* Timer/Counter1 Compare Match A */
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#define TIMER1_COMPA_vect_num 6
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#define TIMER1_COMPA_vect _VECTOR(6)
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#define SIG_OUTPUT_COMPARE1A _VECTOR(6)
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/* Timer/Counter1 Compare Match B */
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#define TIMER1_COMPB_vect_num 7
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#define TIMER1_COMPB_vect _VECTOR(7)
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#define SIG_OUTPUT_COMPARE1B _VECTOR(7)
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/* Timer/Counter1 Overflow */
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#define TIMER1_OVF_vect_num 8
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#define TIMER1_OVF_vect _VECTOR(8)
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#define SIG_OVERFLOW1 _VECTOR(8)
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/* Timer/Counter0 Overflow */
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#define TIMER0_OVF_vect_num 9
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#define TIMER0_OVF_vect _VECTOR(9)
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#define SIG_OVERFLOW0 _VECTOR(9)
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/* SPI Serial Transfer Complete */
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#define SPI_STC_vect_num 10
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#define SPI_STC_vect _VECTOR(10)
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#define SIG_SPI _VECTOR(10)
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/* USART, RX Complete */
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#define USART_RX_vect_num 11
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#define USART_RX_vect _VECTOR(11)
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#define SIG_UART_RECV _VECTOR(11)
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/* USART Data Register Empty */
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#define USART_UDRE_vect_num 12
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#define USART_UDRE_vect _VECTOR(12)
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#define SIG_UART_DATA _VECTOR(12)
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/* USART, TX Complete */
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#define USART_TX_vect_num 13
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#define USART_TX_vect _VECTOR(13)
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#define SIG_UART_TRANS _VECTOR(13)
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/* ADC Conversion Complete */
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#define ADC_vect_num 14
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#define ADC_vect _VECTOR(14)
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#define SIG_ADC _VECTOR(14)
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#define EE_RDY_vect_num 15
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#define EE_RDY_vect _VECTOR(15)
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#define SIG_EEPROM_READY _VECTOR(15)
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/* Analog Comparator */
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#define ANA_COMP_vect_num 16
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#define ANA_COMP_vect _VECTOR(16)
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#define SIG_COMPARATOR _VECTOR(16)
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/* Two-wire Serial Interface */
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#define TWI_vect_num 17
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#define TWI_vect _VECTOR(17)
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#define SIG_2WIRE_SERIAL _VECTOR(17)
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/* External Interrupt Request 2 */
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#define INT2_vect_num 18
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#define INT2_vect _VECTOR(18)
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#define SIG_INTERRUPT2 _VECTOR(18)
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/* TimerCounter0 Compare Match */
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#define TIMER0_COMP_vect_num 19
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#define TIMER0_COMP_vect _VECTOR(19)
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#define SIG_OUTPUT_COMPARE0 _VECTOR(19)
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/* Store Program Memory Read */
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#define SPM_RDY_vect_num 20
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#define SPM_RDY_vect _VECTOR(20)
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#define SIG_SPM_READY _VECTOR(20)
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#define _VECTORS_SIZE 42
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The Register Bit names are represented by their bit number (0-7).
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/* General Interrupt Control Register */
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/* General Interrupt Flag Register */
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/* Timer/Counter Interrupt MaSK register */
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/* Timer/Counter Interrupt Flag register */
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/* Store Program Memory Control Register */
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/* TWI Control Register */
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/* MCU Control Register */
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/* MCU Control and Status Register */
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/* Timer/Counter 0 Control Register */
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The ADHSM bit has been removed from all documentation,
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as being not needed at all since the comparator has proven
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to be fast enough even without feeding it more power.
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/* Special Function IO Register */
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/* Timer/Counter 1 Control Register */
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/* Timer/Counter 1 Control and Status Register */
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/* Timer/Counter 2 Control Register */
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/* Asynchronous mode Status Register */
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/* Watchdog Timer Control Register */
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/* USART Control and Status Register C */
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/* Data Register, Port A */
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/* Data Direction Register, Port A */
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/* Input Pins, Port A */
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/* Data Register, Port B */
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/* Data Direction Register, Port B */
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/* Input Pins, Port B */
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/* Data Register, Port C */
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/* Data Direction Register, Port C */
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/* Input Pins, Port C */
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/* Data Register, Port D */
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/* Data Direction Register, Port D */
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/* Input Pins, Port D */
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/* SPI Status Register */
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/* SPI Control Register */
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/* USART Control and Status Register A */
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/* USART Control and Status Register B */
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/* Analog Comparator Control and Status Register */
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/* ADC Multiplexer Selection Register */
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/* ADC Control and Status Register */
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/* TWI (Slave) Address Register */
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/* TWI Status Register */
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/* EEPROM Control Register */
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#define SPM_PAGESIZE 64
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#define RAMSTART (0x60)
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#define RAMEND 0x25F /* Last On-Chip SRAM Location */
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#define XRAMEND RAMEND
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#define FLASHEND 0x1FFF
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#define FUSE_MEMORY_SIZE 2
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#define FUSE_CKSEL0 (unsigned char)~_BV(0)
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#define FUSE_CKSEL1 (unsigned char)~_BV(1)
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#define FUSE_CKSEL2 (unsigned char)~_BV(2)
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#define FUSE_CKSEL3 (unsigned char)~_BV(3)
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#define FUSE_SUT0 (unsigned char)~_BV(4)
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#define FUSE_SUT1 (unsigned char)~_BV(5)
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#define FUSE_BODEN (unsigned char)~_BV(6)
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#define FUSE_BODLEVEL (unsigned char)~_BV(7)
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#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1)
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#define FUSE_BOOTRST (unsigned char)~_BV(0)
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#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
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#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
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#define FUSE_EESAVE (unsigned char)~_BV(3)
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#define FUSE_CKOPT (unsigned char)~_BV(4)
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#define FUSE_SPIEN (unsigned char)~_BV(5)
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#define FUSE_WDTON (unsigned char)~_BV(6)
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#define FUSE_S8535C (unsigned char)~_BV(7)
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#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
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#define __LOCK_BITS_EXIST
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#define __BOOT_LOCK_BITS_0_EXIST
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#define __BOOT_LOCK_BITS_1_EXIST
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#define SIGNATURE_0 0x1E
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#define SIGNATURE_1 0x93
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#define SIGNATURE_2 0x08
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/* Deprecated items */
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#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
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#pragma GCC system_header
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#pragma GCC poison SIG_INTERRUPT0
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#pragma GCC poison SIG_INTERRUPT1
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#pragma GCC poison SIG_OUTPUT_COMPARE2
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#pragma GCC poison SIG_OVERFLOW2
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#pragma GCC poison SIG_INPUT_CAPTURE1
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#pragma GCC poison SIG_OUTPUT_COMPARE1A
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#pragma GCC poison SIG_OUTPUT_COMPARE1B
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#pragma GCC poison SIG_OVERFLOW1
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#pragma GCC poison SIG_OVERFLOW0
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#pragma GCC poison SIG_SPI
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#pragma GCC poison SIG_UART_RECV
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#pragma GCC poison SIG_UART_DATA
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#pragma GCC poison SIG_UART_TRANS
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#pragma GCC poison SIG_ADC
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#pragma GCC poison SIG_EEPROM_READY
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#pragma GCC poison SIG_COMPARATOR
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#pragma GCC poison SIG_2WIRE_SERIAL
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#pragma GCC poison SIG_INTERRUPT2
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#pragma GCC poison SIG_OUTPUT_COMPARE0
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#pragma GCC poison SIG_SPM_READY
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#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
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#endif /* _AVR_IOM8535_H_ */
added
removed
include/avr/iom8535.h
