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/* Copyright (c) 2002, Marek Michalkiewicz
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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/* $Id: io2333.h 2225 2011-03-02 16:27:26Z arcanum $ */
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/* avr/io2333.h - definitions for AT90S2333 */
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#ifndef _AVR_IO2333_H_
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#define _AVR_IO2333_H_ 1
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/* This file should only be included from <avr/io.h>, never directly. */
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# error "Include <avr/io.h> instead of this file."
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# define _AVR_IOXXX_H_ "io2333.h"
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# error "Attempt to include more than one <avr/ioXXX.h> file."
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/* UART Baud Rate Register high */
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#define UBRRH _SFR_IO8(0x03)
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/* ADC Data register */
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#define ADC _SFR_IO16(0x04)
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#define ADCW _SFR_IO16(0x04)
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#define ADCL _SFR_IO8(0x04)
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#define ADCH _SFR_IO8(0x05)
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/* ADC Control and Status Register */
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#define ADCSR _SFR_IO8(0x06)
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#define ADMUX _SFR_IO8(0x07)
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/* Analog Comparator Control and Status Register */
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#define ACSR _SFR_IO8(0x08)
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/* UART Baud Rate Register */
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#define UBRR _SFR_IO8(0x09)
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/* UART Control/Status Registers */
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#define UCSRB _SFR_IO8(0x0A)
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#define UCSRA _SFR_IO8(0x0B)
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/* UART I/O Data Register */
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#define UDR _SFR_IO8(0x0C)
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/* SPI Control Register */
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#define SPCR _SFR_IO8(0x0D)
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/* SPI Status Register */
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#define SPSR _SFR_IO8(0x0E)
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/* SPI I/O Data Register */
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#define SPDR _SFR_IO8(0x0F)
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/* Input Pins, Port D */
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#define PIND _SFR_IO8(0x10)
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/* Data Direction Register, Port D */
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#define DDRD _SFR_IO8(0x11)
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/* Data Register, Port D */
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#define PORTD _SFR_IO8(0x12)
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/* Input Pins, Port C */
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#define PINC _SFR_IO8(0x13)
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/* Data Direction Register, Port C */
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#define DDRC _SFR_IO8(0x14)
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/* Data Register, Port C */
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#define PORTC _SFR_IO8(0x15)
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/* Input Pins, Port B */
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#define PINB _SFR_IO8(0x16)
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/* Data Direction Register, Port B */
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#define DDRB _SFR_IO8(0x17)
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/* Data Register, Port B */
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#define PORTB _SFR_IO8(0x18)
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/* EEPROM Control Register */
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#define EECR _SFR_IO8(0x1C)
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/* EEPROM Data Register */
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#define EEDR _SFR_IO8(0x1D)
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/* EEPROM Address Register */
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#define EEAR _SFR_IO8(0x1E)
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#define EEARL _SFR_IO8(0x1E)
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/* Watchdog Timer Control Register */
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#define WDTCR _SFR_IO8(0x21)
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/* T/C 1 Input Capture Register */
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#define ICR1 _SFR_IO16(0x26)
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#define ICR1L _SFR_IO8(0x26)
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#define ICR1H _SFR_IO8(0x27)
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/* Timer/Counter1 Output Compare Register A */
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#define OCR1 _SFR_IO16(0x2A)
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#define OCR1L _SFR_IO8(0x2A)
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#define OCR1H _SFR_IO8(0x2B)
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/* Timer/Counter 1 */
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#define TCNT1 _SFR_IO16(0x2C)
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#define TCNT1L _SFR_IO8(0x2C)
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#define TCNT1H _SFR_IO8(0x2D)
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/* Timer/Counter 1 Control and Status Register */
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#define TCCR1B _SFR_IO8(0x2E)
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/* Timer/Counter 1 Control Register */
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#define TCCR1A _SFR_IO8(0x2F)
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/* Timer/Counter 0 */
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#define TCNT0 _SFR_IO8(0x32)
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/* Timer/Counter 0 Control Register */
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#define TCCR0 _SFR_IO8(0x33)
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/* MCU general Status Register */
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#define MCUSR _SFR_IO8(0x34)
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/* MCU general Control Register */
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#define MCUCR _SFR_IO8(0x35)
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/* Timer/Counter Interrupt Flag register */
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#define TIFR _SFR_IO8(0x38)
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/* Timer/Counter Interrupt MaSK register */
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#define TIMSK _SFR_IO8(0x39)
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/* General Interrupt Flag Register */
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#define GIFR _SFR_IO8(0x3A)
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/* General Interrupt MaSK register */
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#define GIMSK _SFR_IO8(0x3B)
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/* Interrupt vectors */
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/* External Interrupt 0 */
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#define INT0_vect_num 1
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#define INT0_vect _VECTOR(1)
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#define SIG_INTERRUPT0 _VECTOR(1)
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/* External Interrupt 1 */
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#define INT1_vect_num 2
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#define INT1_vect _VECTOR(2)
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#define SIG_INTERRUPT1 _VECTOR(2)
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/* Timer/Counter Capture Event */
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#define TIMER1_CAPT_vect_num 3
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#define TIMER1_CAPT_vect _VECTOR(3)
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#define SIG_INPUT_CAPTURE1 _VECTOR(3)
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/* Timer/Counter1 Compare Match */
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#define TIMER1_COMP_vect_num 4
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#define TIMER1_COMP_vect _VECTOR(4)
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#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
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/* Timer/Counter1 Overflow */
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#define TIMER1_OVF_vect_num 5
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#define TIMER1_OVF_vect _VECTOR(5)
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#define SIG_OVERFLOW1 _VECTOR(5)
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/* Timer/Counter0 Overflow */
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#define TIMER0_OVF_vect_num 6
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#define TIMER0_OVF_vect _VECTOR(6)
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#define SIG_OVERFLOW0 _VECTOR(6)
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/* Serial Transfer Complete */
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#define SPI_STC_vect_num 7
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#define SPI_STC_vect _VECTOR(7)
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#define SIG_SPI _VECTOR(7)
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/* UART, Rx Complete */
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#define UART_RX_vect_num 8
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#define UART_RX_vect _VECTOR(8)
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#define SIG_UART_RECV _VECTOR(8)
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/* UART Data Register Empty */
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#define UART_UDRE_vect_num 9
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#define UART_UDRE_vect _VECTOR(9)
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#define SIG_UART_DATA _VECTOR(9)
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/* UART, Tx Complete */
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#define UART_TX_vect_num 10
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#define UART_TX_vect _VECTOR(10)
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#define SIG_UART_TRANS _VECTOR(10)
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/* ADC Conversion Complete */
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#define ADC_vect_num 11
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#define ADC_vect _VECTOR(11)
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#define SIG_ADC _VECTOR(11)
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#define EE_RDY_vect_num 12
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#define EE_RDY_vect _VECTOR(12)
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#define SIG_EEPROM_READY _VECTOR(12)
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/* Analog Comparator */
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#define ANA_COMP_vect_num 13
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#define ANA_COMP_vect _VECTOR(13)
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#define SIG_COMPARATOR _VECTOR(13)
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#define _VECTORS_SIZE 28
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The Register Bit names are represented by their bit number (0-7).
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/* MCU general Status Register */
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/* General Interrupt MaSK register */
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/* General Interrupt Flag Register */
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/* Timer/Counter Interrupt MaSK register */
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/* Timer/Counter Interrupt Flag register */
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/* MCU general Control Register */
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/* Timer/Counter 0 Control Register */
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/* Timer/Counter 1 Control Register */
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/* Timer/Counter 1 Control and Status Register */
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/* Watchdog Timer Control Register */
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/* SPI Control Register */
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/* SPI Status Register */
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/* UART Status Register */
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/* UART Control Register */
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/* Analog Comparator Control and Status Register */
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/* ADC Control and Status Register */
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/* Data Register, Port B */
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/* Data Direction Register, Port B */
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/* Input Pins, Port B */
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/* Data Register, Port C */
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/* Data Direction Register, Port C */
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/* Input Pins, Port C */
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/* Data Register, Port D */
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/* Data Direction Register, Port D */
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/* Input Pins, Port D */
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/* EEPROM Control Register */
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#define RAMEND 0xDF /*Last On-Chip SRAM location*/
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#define XRAMEND RAMEND
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#define FLASHEND 0x7FF
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#endif /* _AVR_IO2333_H_ */