39
39
[AFUNCDATA]= {Pseudo},
40
40
[APCDATA]= {Pseudo},
43
43
[ACHECKNIL]= {LeftRead},
44
[AVARDEF]= {Pseudo | RightWrite},
45
[AVARKILL]= {Pseudo | RightWrite},
45
47
// NOP is an internal no-op that also stands
46
48
// for USED and SET annotations, not the Intel opcode.
136
138
[AFMOVW]= {SizeW | LeftAddr | RightWrite},
137
139
[AFMOVV]= {SizeQ | LeftAddr | RightWrite},
139
[AFMOVDP]= {SizeD | LeftRead | RightAddr},
140
[AFMOVFP]= {SizeF | LeftRead | RightAddr},
141
[AFMOVLP]= {SizeL | LeftRead | RightAddr},
142
[AFMOVWP]= {SizeW | LeftRead | RightAddr},
143
[AFMOVVP]= {SizeQ | LeftRead | RightAddr},
141
// These instructions are marked as RightAddr
142
// so that the register optimizer does not try to replace the
143
// memory references with integer register references.
144
// But they do not use the previous value at the address, so
145
// we also mark them RightWrite.
146
[AFMOVDP]= {SizeD | LeftRead | RightWrite | RightAddr},
147
[AFMOVFP]= {SizeF | LeftRead | RightWrite | RightAddr},
148
[AFMOVLP]= {SizeL | LeftRead | RightWrite | RightAddr},
149
[AFMOVWP]= {SizeW | LeftRead | RightWrite | RightAddr},
150
[AFMOVVP]= {SizeQ | LeftRead | RightWrite | RightAddr},
145
152
[AFMULD]= {SizeD | LeftAddr | RightRdwr},
146
153
[AFMULDP]= {SizeD | LeftAddr | RightRdwr},
193
200
[AMOVSB]= {OK, DI|SI, DI|SI},
194
201
[AMOVSL]= {OK, DI|SI, DI|SI},
195
202
[AMOVSW]= {OK, DI|SI, DI|SI},
203
[ADUFFCOPY]= {OK, DI|SI, DI|SI|CX},
197
205
[AMOVSD]= {SizeD | LeftRead | RightWrite | Move},
198
206
[AMOVSS]= {SizeF | LeftRead | RightWrite | Move},
285
293
[ASTOSB]= {OK, AX|DI, DI},
286
294
[ASTOSL]= {OK, AX|DI, DI},
287
295
[ASTOSW]= {OK, AX|DI, DI},
296
[ADUFFZERO]= {OK, AX|DI, DI},
289
298
[ASUBB]= {SizeB | LeftRead | RightRdwr | SetCarry},
290
299
[ASUBL]= {SizeL | LeftRead | RightRdwr | SetCarry},