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Viewing changes to drivers/net/ethernet/broadcom/tg3.c

  • Committer: Package Import Robot
  • Author(s): Paolo Pisati, Paolo Pisati
  • Date: 2013-07-11 18:35:20 UTC
  • Revision ID: package-import@ubuntu.com-20130711183520-htnf1x4y5r11hndr
Tags: 3.5.0-229.42
https://launchpad.net/bugs/1199276
* Release Tracking Bug
  - LP: #1199276

[ Paolo Pisati ]

* [Config] CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set

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Lines of Context:
drivers/net/ethernet/broadcom/tg3.c
689
689
                status = tg3_ape_read32(tp, gnt + off);
690
690
                if (status == bit)
691
691
                        break;
 
692
                if (pci_channel_offline(tp->pdev))
 
693
                        break;
 
694
 
692
695
                udelay(10);
693
696
        }
694
697
 
1466
1469
        for (i = 0; i < delay_cnt; i++) {
1467
1470
                if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1468
1471
                        break;
 
1472
                if (pci_channel_offline(tp->pdev))
 
1473
                        break;
 
1474
 
1469
1475
                udelay(8);
1470
1476
        }
1471
1477
}
1631
1637
        int i;
1632
1638
        u32 val;
1633
1639
 
 
1640
        if (tg3_flag(tp, NO_FWARE_REPORTED))
 
1641
                return 0;
 
1642
 
1634
1643
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1635
1644
                /* Wait up to 20ms for init done. */
1636
1645
                for (i = 0; i < 200; i++) {
1637
1646
                        if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1638
1647
                                return 0;
 
1648
                        if (pci_channel_offline(tp->pdev))
 
1649
                                return -ENODEV;
 
1650
 
1639
1651
                        udelay(100);
1640
1652
                }
1641
1653
                return -ENODEV;
1646
1658
                tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1647
1659
                if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1648
1660
                        break;
 
1661
                if (pci_channel_offline(tp->pdev)) {
 
1662
                        if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
 
1663
                                tg3_flag_set(tp, NO_FWARE_REPORTED);
 
1664
                                netdev_info(tp->dev, "No firmware running\n");
 
1665
                        }
 
1666
 
 
1667
                        break;
 
1668
                }
 
1669
 
1649
1670
                udelay(10);
1650
1671
        }
1651
1672
 
3302
3323
                        tw32(offset + CPU_MODE,  CPU_MODE_HALT);
3303
3324
                        if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3304
3325
                                break;
 
3326
                        if (pci_channel_offline(tp->pdev))
 
3327
                                return -EBUSY;
3305
3328
                }
3306
3329
 
3307
3330
                tw32(offset + CPU_STATE, 0xffffffff);
3313
3336
                        tw32(offset + CPU_MODE,  CPU_MODE_HALT);
3314
3337
                        if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3315
3338
                                break;
 
3339
                        if (pci_channel_offline(tp->pdev))
 
3340
                                return -EBUSY;
3316
3341
                }
3317
3342
        }
3318
3343
 
7720
7745
        tw32_f(ofs, val);
7721
7746
 
7722
7747
        for (i = 0; i < MAX_WAIT_CNT; i++) {
 
7748
                if (pci_channel_offline(tp->pdev)) {
 
7749
                        dev_err(&tp->pdev->dev,
 
7750
                                "tg3_stop_block device offline, "
 
7751
                                "ofs=%lx enable_bit=%x\n",
 
7752
                                ofs, enable_bit);
 
7753
                        return -ENODEV;
 
7754
                }
 
7755
 
7723
7756
                udelay(100);
7724
7757
                val = tr32(ofs);
7725
7758
                if ((val & enable_bit) == 0)
7743
7776
 
7744
7777
        tg3_disable_ints(tp);
7745
7778
 
 
7779
        if (pci_channel_offline(tp->pdev)) {
 
7780
                tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
 
7781
                tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
 
7782
                err = -ENODEV;
 
7783
                goto err_no_dev;
 
7784
        }
 
7785
 
7746
7786
        tp->rx_mode &= ~RX_MODE_ENABLE;
7747
7787
        tw32_f(MAC_RX_MODE, tp->rx_mode);
7748
7788
        udelay(10);
7791
7831
        err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
7792
7832
        err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
7793
7833
 
 
7834
err_no_dev:
7794
7835
        for (i = 0; i < tp->irq_cnt; i++) {
7795
7836
                struct tg3_napi *tnapi = &tp->napi[i];
7796
7837
                if (tnapi->hw_status)
8572
8613
        }
8573
8614
}
8574
8615
 
 
8616
static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
 
8617
{
 
8618
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
 
8619
                return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
 
8620
        else
 
8621
                return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
 
8622
}
 
8623
 
8575
8624
/* tp->lock is held. */
8576
8625
static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8577
8626
{
9208
9257
        tw32_f(RDMAC_MODE, rdmac_mode);
9209
9258
        udelay(40);
9210
9259
 
 
9260
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
 
9261
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
 
9262
                for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
 
9263
                        if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
 
9264
                                break;
 
9265
                }
 
9266
                if (i < TG3_NUM_RDMA_CHANNELS) {
 
9267
                        val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
 
9268
                        val |= tg3_lso_rd_dma_workaround_bit(tp);
 
9269
                        tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
 
9270
                        tg3_flag_set(tp, 5719_5720_RDMA_BUG);
 
9271
                }
 
9272
        }
 
9273
 
9211
9274
        tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
9212
9275
        if (!tg3_flag(tp, 5705_PLUS))
9213
9276
                tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9429
9492
 */
9430
9493
static int tg3_init_hw(struct tg3 *tp, int reset_phy)
9431
9494
{
 
9495
        /* Chip may have been just powered on. If so, the boot code may still
 
9496
         * be running initialization. Wait for it to finish to avoid races in
 
9497
         * accessing the hardware.
 
9498
         */
 
9499
        tg3_enable_register_access(tp);
 
9500
        tg3_poll_fw(tp);
 
9501
 
9432
9502
        tg3_switch_clocks(tp);
9433
9503
 
9434
9504
        tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9463
9533
        TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
9464
9534
        TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
9465
9535
        TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
 
9536
        if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
 
9537
                     (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
 
9538
                      sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
 
9539
                u32 val;
 
9540
 
 
9541
                val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
 
9542
                val &= ~tg3_lso_rd_dma_workaround_bit(tp);
 
9543
                tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
 
9544
                tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
 
9545
        }
9466
9546
 
9467
9547
        TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
9468
9548
        TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);