1
/******************************************************************************
2
* Copyright (c) 2004, 2008 IBM Corporation
4
* This program and the accompanying materials
5
* are made available under the terms of the BSD License
6
* which accompanies this distribution, and is available at
7
* http://www.opensource.org/licenses/bsd-license.php
10
* IBM Corporation - initial implementation
11
*****************************************************************************/
13
# SLOF for JS20/JS21 -- ROM boot code.
14
# Initial entry point, copy code from flash to cache, memory setup.
15
# Also sets up serial console and optimizes some settings.
22
#include <southbridge.h>
27
/* put rombase in sprg1 ***********************/
33
.long relTag - __start
39
mtsprg 1, r3 /* romfs base */
52
mtsprg 1, r3 /* romfs base */
58
/* FIXME: Also need 0280, 0380, 0f20, etc. */
60
.irp i, 0x0100,0x0180,0x0200,0x0280,0x0300,0x0380,0x0400,0x0500,0x0600,0x0700, \
61
0x0800,0x0900,0x0a00,0x0b00,0x0c00,0x0d00,0x0e00,0x0f00, \
62
0x1000,0x1100,0x1200,0x1300,0x1400,0x1500,0x1600,0x1700, \
63
0x1800,0x1900,0x1a00,0x1b00,0x1c00,0x1d00,0x1e00,0x1f00, \
64
0x2000,0x2100,0x2200,0x2300,0x2400,0x2500,0x2600,0x2700, \
65
0x2800,0x2900,0x2a00,0x2b00,0x2c00,0x2d00,0x2e00
68
/* enable this if you get exceptions before the console works */
69
/* this will allow using the hardware debugger to see where */
70
/* it traps, and with what register values etc. */
79
ld r0, (\i + 0x160)(0)
92
. = XVECT_M_HANDLER - 0x100
94
. = XVECT_S_HANDLER - 0x100
102
# optimize HID register settings
106
# read semaphore, run as slave if not the first to do so
107
li 3,0 ; oris 3,3,0xf800 ; lwz 3,0x60(3) ; andi. 3,3,1 ; beq slave
109
# setup flash, serial
115
li 3,13 ; bl putc ; li 3,10 ; bl putc ; li 3,'S' ; bl putc
118
#do we run from ram ?
119
mfsprg r3, 1 /* rombase */
120
cmpdi r3,0 /* rombase is 0 when running from RAM */
124
# wait a bit, start scripts are slow... need to get all cores running!
125
lis 3,0x4000 ; mtctr 3 ; bdnz $
127
# copy 4MB from 0 to temp memory
128
lis 4,0x8 ; mtctr 4 ; lis 4,0x200 ; li 3,0 ; addi 4,4,-8 ; addi 3,3,-8
129
0: ldu 5,8(3) ; stdu 5,8(4) ; bdnz 0b
135
lis 3,0x20 ; addi 3,3,0x200-8 ;
139
addi 4,4,copy_to_cache@l
143
# make all data accesses cache-inhibited
148
# make all data accesses cacheable
153
# write a character to the serial port
155
# always write to serial1
156
0: lbz 0,5(13) ; andi. 0,0,0x20 ; beq 0b ; stb 3,0(13) ; eieio
158
# read ID register: only if it is a PC87427 (JS21) also use serial2
159
li 4,0 ; oris 4,4,0xf400
160
li 5,0x20 ; stb 5,0x2e(4) ; lbz 5,0x2f(4); cmpdi 5,0xf2 ; bne 1f
163
0: lbz 0,5(4) ; andi. 0,0,0x20 ; beq 0b ; stb 3,0(4) ; eieio
167
# transfer from running from flash to running from cache
169
# find and set address to start running from cache, set msr value
170
mflr 3 ; rldicl 3,3,0,44
173
mfmsr 3 ; ori 3,3,0x1000 ; mtsrr1 3 # enable MCE, as well
175
# set cacheable insn fetches, jump to cache
176
mfspr 3,HID1 ; rldicl 3,3,32,0 ; oris 3,3,0x0020 ; rldicl 3,3,32,0
177
sync ; mtspr HID1,3 ; mtspr HID1,3 ; rfid ; b .
183
# zero the whole cache
184
# also, invalidate the insn cache, to clear parity errors
185
# 128kB @ 0MB (boot code and vectors from 0x0 up to 0x20000)
186
li 4,0x400 ; mtctr 4 ; li 5,0x0 ; bl clr_ci_bit
187
0: dcbz 0,5 ; sync ; icbi 0,5 ; sync ; isync ; addi 5,5,0x80 ; bdnz 0b
189
# 0x2000 to 0x100000/0x80000 (smaller on 970/970FX)
190
li 4,0x1C00 ; mfpvr 0 ; srdi 0,0,16 ; cmpdi 0,0x0044 ; bge 0f ; li 4,0xC00
192
mtctr 4 ; li 5,0x2000
193
0: dcbz 0,5 ; sync ; isync ; addi 5,5,0x80 ; bdnz 0b ; bl set_ci_bit
196
bcl 20,31,$+4 ; mflr 31 ; rldicr 31,31,0,43
198
# copy 1kB from 0x4000
199
li 4,0x80 ; mtctr 4 ;
202
0: ldu 4,8(3) ; bl clr_ci_bit ; stdu 4,8(5) ; bl set_ci_bit ; bdnz 0b
203
# now start executing from cache -- insn cache is huge speed boost
209
# copy 128kB of flash to cache
210
li 4,0x800 ; mtctr 4 ; li 5,0x200-64 ; addi 3,31,0x200-64 ;
211
0: ldu 16,64(3) ; ld 17,8(3) ; ld 18,16(3) ; ld 19,24(3)
212
ld 20,32(3) ; ld 21,40(3) ; ld 22,48(3) ; ld 23,56(3)
214
stdu 16,64(5) ; std 17,8(5) ; std 18,16(5) ; std 19,24(5)
215
std 20,32(5) ; std 21,40(5) ; std 22,48(5) ; std 23,56(5)
216
icbi 0,5 ; bl set_ci_bit ; bdnz 0b ; isync
226
// at 0xf8000000 we decide if it is u3 or u4
227
li 4,0 ; oris 4,4,0xf800 ; lwz 3,0(4) ; srdi 3,3,4 ; cmpdi 3,3 ; bne 0f
236
# setup nvram logging only when not running from RAM
237
mfsprg r3, 1 /* rombase */
238
cmpdi r3, 0 /* rombase is 0 when running from RAM */
241
// at 0xf8000000 we decide if it is u3 or u4
246
cmpdi r3, 3 /* 3 means js20; no nvram logging on js20 */
254
# data is cacheable by default from now on
258
/* give live sign *****************************/
260
.ascii TERM_CTRL_RESET
261
.ascii TERM_CTRL_CRSOFF
262
.ascii " **********************************************************************"
264
.ascii TERM_CTRL_BRIGHT
266
.ascii " Starting\r\n"
267
.ascii TERM_CTRL_RESET
268
.ascii " Build Date = ", __DATE__, " ", __TIME__
270
.ascii " FW Version = " , RELEASE
290
li 3,0 ; oris 3,3,0xf800 ; lwz 28,0x50(3)
293
# create our slave loop address
294
sldi 3,28,24 ; oris 3,3,0x3000
296
# invalidate the insn cache, to clear parity errors
297
# clear the L2 cache as well, to get ECC right
298
li 4,0x2000 ; mfpvr 0 ; srdi 0,0,16 ; cmpdi 0,0x0044 ; bge 0f ; li 4,0x1000
299
0: mtctr 4 ; mr 5,3 ; bl clr_ci_bit
301
0: dcbz 0,5 ; sync ; icbi 0,5 ; sync ; isync ; addi 5,5,0x80 ; bdnz 0b
304
# write a "b $" insn in there
305
lis 4,0x4800 ; stw 4,0(3)
311
li 13,0 ; oris 13,13,0xf400
314
li 3,'O' ; add 3,3,28 ; bl putc
323
# allow the flash chip to be accessed faster
324
# initialize the 16550-compatible uart on serial port 1 of the sio
328
li 3,0 ; oris 3,3,0xf400
331
li 3,0 ; oris 3,3,0xf400
333
# put x-bus in turbo mode
334
li 4,0xf1 ; stb 4,0x400(3) ; eieio
338
li 4,7 ; stb 4,0x2e(3) ; eieio ; li 4,3 ; stb 4,0x2f(3) ; eieio
340
# set base address to 3f8
341
li 4,0x60 ; stb 4,0x2e(3) ; eieio ; li 4,3 ; stb 4,0x2f(3) ; eieio
344
li 4,0x30 ; stb 4,0x2e(3) ; eieio ; li 4,1 ; stb 4,0x2f(3) ; eieio
346
# read ID register: only if it is a PC87427, enable serial2
347
li 4,0x20 ; stb 4,0x2e(3) ; eieio ; lbz 4,0x2f(3) ; cmpdi 4,0xf2 ; bne 0f
350
li 4,7 ; stb 4,0x2e(3) ; eieio ; li 4,2 ; stb 4,0x2f(3) ; eieio
352
# set base address to 2f8
353
li 4,0x60 ; stb 4,0x2e(3) ; eieio ; li 4,2 ; stb 4,0x2f(3) ; eieio
356
li 4,0x30 ; stb 4,0x2e(3) ; eieio ; li 4,1 ; stb 4,0x2f(3) ; eieio
361
# disable interrupts, fifo off
362
li 4,0 ; stb 4,1(3) ; eieio ; stb 4,2(3) ; eieio
365
li 4,0x80 ; stb 4,3(3) ; eieio
366
li 4,115200/19200 ; stb 4,0(3) ; eieio ; li 4,0 ; stb 4,1(3) ; eieio
368
# set 8-N-1, set RTS and DTR
369
li 4,3 ; stb 4,3(3) ; eieio ; stb 4,4(3) ; eieio
378
# disable interrupts, fifo off
379
li 4,0 ; stb 4,1(3) ; eieio ; stb 4,2(3) ; eieio
382
li 4,0x80 ; stb 4,3(3) ; eieio
383
li 4,115200/19200 ; stb 4,0(3) ; eieio ; li 4,0 ; stb 4,1(3) ; eieio
385
# set 8-N-1, set RTS and DTR
386
li 4,3 ; stb 4,3(3) ; eieio ; stb 4,4(3) ; eieio
390
# save UART base for putc routine
398
# set the HID registers of the 970 for optimally executing from flash
401
/* clear all the HV cruft */
407
/* enable dpm, disable attn insn, enable external mce
408
* first, try external time base; if clock doesn't run, switch to
410
li r0, 1 /* do the setup for external timebase */
411
rldicl r0, r0, 44, 0 /* bit 19 has to be set */
412
oris r0, r0, 0x8000 /* Enable external machine check */
413
/* interrupts (preferred state */
419
mftb r3 /* read the timebase */
420
li r1, 0x4000 /* wait long enough for the external */
421
mtctr r1 /* timebase (14MHz) to tick a bit */
422
bdnz $ /* 0x4000 seems to be enough (for now) */
423
mftb r4 /* read the timebase a second time */
424
cmpld r3, r4 /* see if it changed */
426
/* timebase did not change, do the setup for internal */
434
/* enable insn prefetch, speculative table walks */
438
mfsprg r3, 1 /* read rombase */
439
cmpdi r3, 0 /* check if running from ram */
441
/* running from ram */
442
/* Enable instruction fetch cacheability control */
450
/* enable cache parity */
458
/* exception offset at 0 */
464
C_ENTRY(proceedInterrupt)
466
ld r3,exception_stack_frame@got(r2)
469
.irp i, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, \
470
17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
472
ld r\i, 0x30+\i*8 (r1)
485
ld 0,XVECT_M_HANDLER(0)
488
ld r0,0x30(r1); # restore vector number
494
mtctr r1 # save old stack pointer
497
.irp i, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, \
498
17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
500
std r\i, 0x30+\i*8 (r1)
503
std r0,0x30(r1); # save vector number
506
std r14,0x38(r1); # save old r1
522
ld r3,exception_stack_frame@got(r2)
542
.irp i, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, \
543
17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
545
ld r\i, 0x30+\i*8 (r1)
557
/* Set exception handler for given exception vector.
558
r3: exception vector offset
559
r4: exception handler
561
.globl .set_exception
566
.globl .set_exception_asm
568
.globl set_exception_asm
570
std r4, 0x60(r3) # fixme diff 1f - 0b
575
li 4,0x2000 ; oris 4,4,0xf800
577
# MemTimingParam -- CAS lat 2.5 / 4 (read-to-read / read-to-write)
578
lis 3,0x49e1 ; ori 3,3,0xa000 ; stw 3,0x50(4)
580
# MRSRegCntl -- CAS lat 2.5
581
li 3,0x6a ; stw 3,0xf0(4)
583
# MemBusConfig -- 128 bit bus
584
lis 3,0x8500 ; stw 3,0x190(4)
586
# CKDelAdj -- clock delay 75
587
lis 3,0x12c3 ; ori 3,3,0x30cc ; stw 3,0x520(4)
589
# IOModeCntl -- no termination on differential and 3-state drivers
590
lis 3,0x0350 ; stw 3,0x530(4)
592
li 3,18 ; mtctr 3 ; addi 5,4,0x5f0
593
0: # DQSDelAdj -- read delay offset -10
594
lis 3,0x3d8f ; ori 3,3,0x6000 ; stwu 3,0x10(5)
596
# DQSDataDelAdj -- write delay offset -32, write data delay offset +15
597
lis 3,0x380e ; ori 3,3,0x003c ; stwu 3,0x10(5)
600
# MemProgCntl -- set all
601
lis 3,0xc000 ; stw 3,0xe0(4)
608
# read dimm SPDs, program memory size and type
612
li 15,0 ; oris 15,15,0xf800 ; li 17,0
613
li 3,0xa0 ; li 4,3 ; li 5,3 ; bl i2c_read
614
mr 16,4 ; cmpdi 3,0 ; beq 0f ; li 16,0
615
0: li 3,0xa2 ; li 4,3 ; li 5,3 ; bl i2c_read
616
cmpd 16,4 ; bne 0f ; cmpdi 3,0 ; beq 1f
618
1: #li 3,0xd ; bl print_byte ; li 3,0xa ; bl print_byte
619
#mr 3,16 ; bl print_hex
621
#li 3,0x20 ; bl print_byte
622
sldi 3,16,7 ; add 3,3,16 ; rlwinm 3,3,10,0,6 ; subis 3,3,0x3c00
623
stw 3,0x21c0(15) ; andi. 0,16,2 ; beq 0f ; stw 3,0x21e0(15)
625
sldi 3,16,8 ; add 3,3,16 ; rldicl 3,3,48,56 ; li 0,8 ; slw 3,0,3
626
# slw, not sld, so that empty/bad banks translate into size 0
627
stw 17,0x21d0(15) ; bl add17173 ; stw 17,0x21f0(15)
628
andi. 0,16,2 ; beq 0f ; bl add17173
631
li 3,0xa4 ; li 4,3 ; li 5,3 ; bl i2c_read
632
mr 16,4 ; cmpdi 3,0 ; beq 0f ; li 16,0
633
0: li 3,0xa6 ; li 4,3 ; li 5,3 ; bl i2c_read
634
cmpd 16,4 ; bne 0f ; cmpdi 3,0 ; beq 1f
636
1: #li 3,0xd ; bl print_byte ; li 3,0xa ; bl print_byte
637
#mr 3,16 ; bl print_hex
639
#li 3,0x20 ; bl print_byte
640
sldi 3,16,7 ; add 3,3,16 ; rlwinm 3,3,10,0,6 ; subis 3,3,0x3c00
641
stw 3,0x2200(15) ; andi. 0,16,2 ; beq 0f ; stw 3,0x2220(15)
643
sldi 3,16,8 ; add 3,3,16 ; rldicl 3,3,48,56 ; li 0,8 ; slw 3,0,3
644
stw 17,0x2210(15) ; bl add17173 ; stw 17,0x2230(15)
645
andi. 0,16,2 ; beq 0f ; bl add17173
647
#mr 3,17 ; bl print_hex
648
stw 17,0x2250(15) ; stw 17,0x2270(15)
649
stw 17,0x2290(15) ; stw 17,0x22b0(15)
657
# print GPR3 as 8-digit hex. uses GPR18,19
659
mflr 18 ; mr 19,3 ; li 3,8 ; mtctr 3
660
1: rlwinm 3,19,4,28,31 ; sldi 19,19,4
661
cmpdi 3,0xa ; blt 0f ; addi 3,3,0x27
662
0: addi 3,3,0x30 ; bl putc
663
bdnz 1b ; mtlr 18 ; blr
666
# i2c stuff uses GPR20..GPR24
668
# terminate any i2c transaction, at any point during that transaction
670
0: lwz 3,0x30(20) ; stw 3,0x30(20) ; andi. 3,3,4 ; beq 0b
671
mr 3,21 ; mr 4,22 ; mtlr 24 ; eieio ; blr
673
# do a combined-mode read
674
# in: GPR3 = addr, GPR4 = subaddr, GPR5 = len
675
# out: GPR3 = error, GPR4 = result (right-aligned, msb)
678
li 20,0x1000 ; oris 20,20,0xf800 # uni-n i2c base
679
mr 21,3 ; mr 22,4 ; mr 23,5 # save params
680
li 4,0xc ; stw 4,0(20) # set mode (combined)
681
ori 4,21,1 ; stw 4,0x50(20) # set addr, read
682
stw 22,0x60(20) # set subaddr
683
li 4,2 ; stw 4,0x10(20) ; eieio # start address phase
685
li 22,0 # result accumulator
686
0: lwz 3,0x30(20) ; andi. 3,3,2 ; beq 0b # wait until sent
687
lwz 3,0x20(20) ; andi. 3,3,2 ; beq i2c_stop # check result
688
li 4,1 ; cmpdi 23,1 ; bne 0f ; li 4,0
689
0: stw 4,0x10(20) # AAK for next byte (or not)
690
li 4,2 ; stw 4,0x30(20) ; eieio # ack address phase
692
lwz 3,0x30(20) ; andi. 3,3,1 ; beq 1f # if byte recv'd:
693
subi 23,23,1 ; sldi 22,22,8 # shift byte accum
694
lwz 3,0x70(20) ; rlwimi 22,3,0,24,31 # get byte
695
cmpdi 23,0 ; bne 0f ; li 21,0 ; b i2c_stop # all done
696
0: li 4,1 ; cmpdi 23,1 ; bne 0f ; li 4,0
697
0: stw 4,0x10(20) # AAK for next byte (or not)
698
li 4,1 ; stw 4,0x30(20) ; eieio # ack data phase
699
1: lwz 3,0x30(20) ; andi. 3,3,4 ; beq i2c_read_loop
700
li 4,0 ; stw 4,0x10(20) ; eieio ; b i2c_stop # stop bit received
702
add17173: # add GPR3 into GPR17; if passing 2GB (0x10000000), add another 2GB.
703
lis 0,0x1000 ; cmpld 17,0 ; add 17,17,3 ; bgtlr
704
cmpld 17,0 ; blelr ; add 17,17,0 ; blr
707
LOAD64(r3, SB_NVRAM_adr)
added
removed
board-js2x/llfw/startup.S
