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//*************************************************************************
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// Copyright 2003-2013 by Wilson Snyder. This program is free software; you can
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// Copyright 2003-2014 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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id/*new-modport*/ '(' modportPortsDeclList ')' { $$ = new AstModport($2,*$1,$3); }
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modportPortsDeclList<modportvarrefp>:
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modportPortsDeclList<nodep>:
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modportPortsDecl { $$ = $1; }
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| modportPortsDeclList ',' modportPortsDecl { $$ = $1->addNextNull($3)->castModportVarRef(); }
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| modportPortsDeclList ',' modportPortsDecl { $$ = $1->addNextNull($3); }
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// IEEE: modport_ports_declaration + modport_simple_ports_declaration
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// + (modport_tf_ports_declaration+import_export) + modport_clocking_declaration
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// We've expanded the lists each take to instead just have standalone ID ports.
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// We track the type as with the V2k series of defines, then create as each ID is seen.
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modportPortsDecl<modportvarrefp>:
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modportPortsDecl<nodep>:
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// // IEEE: modport_simple_ports_declaration
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port_direction modportSimplePort { $$ = new AstModportVarRef($<fl>1,*$2,GRAMMARP->m_varIO); }
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// // IEEE: modport_clocking_declaration
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//UNSUP yCLOCKING idAny/*clocking_identifier*/ { }
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//UNSUP yIMPORT modport_tf_port { }
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//UNSUP yEXPORT modport_tf_port { }
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| yCLOCKING idAny/*clocking_identifier*/ { $1->v3error("Unsupported: Modport clocking"); }
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// // IEEE: yIMPORT modport_tf_port
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// // IEEE: yEXPORT modport_tf_port
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// // modport_tf_port expanded here
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| yIMPORT id/*tf_identifier*/ { $$ = new AstModportFTaskRef($<fl>1,*$2,false); }
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| yEXPORT id/*tf_identifier*/ { $$ = new AstModportFTaskRef($<fl>1,*$2,true); }
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| yIMPORT method_prototype { $1->v3error("Unsupported: Modport import with prototype"); }
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| yEXPORT method_prototype { $1->v3error("Unsupported: Modport export with prototype"); }
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// Continuations of above after a comma.
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// // IEEE: modport_simple_ports_declaration
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| modportSimplePort { $$ = new AstModportVarRef($<fl>1,*$1,AstVarType::INOUT); }
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netSig<varp>: // IEEE: net_decl_assignment - one element from list_of_port_identifiers
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netId sigAttrListE { $$ = VARDONEA($<fl>1,*$1, NULL, $2); }
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| netId sigAttrListE '=' expr { $$ = VARDONEA($<fl>1,*$1, NULL, $2); $$->addNext(new AstAssignW($3,new AstVarRef($3,$$->name(),true),$4)); }
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| netId rangeList sigAttrListE { $$ = VARDONEA($<fl>1,*$1, $2, $3); }
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| netId variable_dimensionList sigAttrListE { $$ = VARDONEA($<fl>1,*$1, $2, $3); }
added
removed
src/verilog.y
