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// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Iztok Jeras.
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module t (/*AUTOARG*/);
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logic [3:0] array_simp [1:0] [3:0]; // big endian array
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array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
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if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop;
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// verilator lint_off WIDTH
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array_simp[0] = '{ 3 ,2 ,1, 0 };
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// verilator lint_on WIDTH
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if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop;
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// Doesn't seem to work for unpacked arrays in other simulators
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//array_simp[0] = '{ 1:4'd3, default:13 };
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//if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop;
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array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
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if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
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array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_1234) $stop;
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// Doesn't seem to work for unpacked arrays in other simulators
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//array_simp <= '{2{ '{4{ 4'd3, 4'd2, 4'd1, 4'd0 }} }};
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$write("*-* All Finished *-*\n");