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* Copyright (c) 2001-2004 Jakub Jermar
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include <arch/types.h>
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#include <arch/interrupt.h>
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#include <arch/context.h>
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#include <arch/mm/page.h>
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#include <arch/boot/boot.h>
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#include <interrupt.h>
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* Early ia32 configuration functions and data structures.
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* We have no use for segmentation so we set up flat mode. In this
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* mode, we use, for each privilege level, two segments spanning the
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* whole memory. One is for code and one is for data.
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* One is for GS register which holds pointer to the TLS thread
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* structure in it's base.
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descriptor_t gdt[GDT_ITEMS] = {
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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/* KTEXT descriptor */
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{ 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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/* KDATA descriptor */
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{ 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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/* UTEXT descriptor */
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{ 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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/* UDATA descriptor */
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{ 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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/* TSS descriptor - set up will be completed later */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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/* VESA Init descriptor */
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{ 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
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static idescriptor_t idt[IDT_ITEMS];
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/* gdtr is changed by kmp before next CPU is initialized */
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ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };
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ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
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void gdt_setbase(descriptor_t *d, uintptr_t base)
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d->base_0_15 = base & 0xffff;
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d->base_16_23 = ((base) >> 16) & 0xff;
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d->base_24_31 = ((base) >> 24) & 0xff;
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void gdt_setlimit(descriptor_t *d, uint32_t limit)
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d->limit_0_15 = limit & 0xffff;
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d->limit_16_19 = (limit >> 16) & 0xf;
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void idt_setoffset(idescriptor_t *d, uintptr_t offset)
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* Offset is a linear address.
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d->offset_0_15 = offset & 0xffff;
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d->offset_16_31 = offset >> 16;
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void tss_initialize(tss_t *t)
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memsetb(t, sizeof(tss_t), 0);
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* This function takes care of proper setup of IDT and IDTR.
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for (i = 0; i < IDT_ITEMS; i++) {
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d->selector = gdtselector(KTEXT_DES);
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d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */
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if (i == VECTOR_SYSCALL) {
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* The syscall interrupt gate must be calleable from
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d->access |= DPL_USER;
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idt_setoffset(d, ((uintptr_t) interrupt_handlers) +
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i * interrupt_handler_size);
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/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
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static void clean_IOPL_NT_flags(void)
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"and $0xffff8fff, %%eax\n"
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/* Clean AM(18) flag in CR0 register */
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static void clean_AM_flag(void)
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"and $0xfffbffff, %%eax\n"
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descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
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* Update addresses in GDT and IDT to their virtual counterparts.
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idtr.limit = sizeof(idt);
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idtr.base = (uintptr_t) idt;
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* Each CPU has its private GDT and TSS.
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* All CPUs share one IDT.
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if (config.cpu_active == 1) {
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* NOTE: bootstrap CPU has statically allocated TSS, because
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* the heap hasn't been initialized so far.
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tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
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panic("Cannot allocate TSS.");
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tss_initialize(tss_p);
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gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
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gdt_p[TSS_DES].special = 1;
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gdt_p[TSS_DES].granularity = 0;
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gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
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gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
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* As of this moment, the current CPU has its own GDT pointing
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* to its own TSS. We just need to load the TR register.
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tr_load(gdtselector(TSS_DES));
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clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */
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clean_AM_flag(); /* Disable alignment check */
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void set_tls_desc(uintptr_t tls)
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gdtr_store(&cpugdtr);
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gdt_p = (descriptor_t *) cpugdtr.base;
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gdt_setbase(&gdt_p[TLS_DES], tls);
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/* Reload gdt register to update GS in CPU */