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// Copyright (c) 2012 The Chromium Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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// This file is an internal atomic implementation, use base/atomicops.h instead.
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// LinuxKernelCmpxchg and Barrier_AtomicIncrement are from Google Gears.
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#ifndef BASE_ATOMICOPS_INTERNALS_MIPS_GCC_H_
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#define BASE_ATOMICOPS_INTERNALS_MIPS_GCC_H_
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// Atomically execute:
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// if (*ptr == old_value)
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// I.e., replace "*ptr" with "new_value" if "*ptr" used to be "old_value".
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// Always return the old value of "*ptr"
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// This routine implies no memory barriers.
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inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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__asm__ __volatile__(".set push\n"
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"ll %0, %5\n" // prev = *ptr
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"bne %0, %3, 2f\n" // if (prev != old_value) goto 2
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"move %2, %4\n" // tmp = new_value
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"sc %2, %1\n" // *ptr = tmp (with atomic check)
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"beqz %2, 1b\n" // start again on atomic error
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"nop\n" // delay slot nop
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: "=&r" (prev), "=m" (*ptr), "=&r" (tmp)
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: "Ir" (old_value), "r" (new_value), "m" (*ptr)
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// Atomically store new_value into *ptr, returning the previous value held in
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// *ptr. This routine implies no memory barriers.
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inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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__asm__ __volatile__(".set push\n"
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"ll %1, %2\n" // old = *ptr
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"move %0, %3\n" // temp = new_value
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"sc %0, %2\n" // *ptr = temp (with atomic check)
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"beqz %0, 1b\n" // start again on atomic error
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"nop\n" // delay slot nop
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: "=&r" (temp), "=&r" (old), "=m" (*ptr)
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: "r" (new_value), "m" (*ptr)
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// Atomically increment *ptr by "increment". Returns the new value of
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// *ptr with the increment applied. This routine implies no memory barriers.
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inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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__asm__ __volatile__(".set push\n"
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"ll %0, %2\n" // temp = *ptr
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"addu %1, %0, %3\n" // temp2 = temp + increment
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"sc %1, %2\n" // *ptr = temp2 (with atomic check)
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"beqz %1, 1b\n" // start again on atomic error
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"addu %1, %0, %3\n" // temp2 = temp + increment
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: "=&r" (temp), "=&r" (temp2), "=m" (*ptr)
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: "Ir" (increment), "m" (*ptr)
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// temp2 now holds the final value.
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inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 res = NoBarrier_AtomicIncrement(ptr, increment);
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// "Acquire" operations
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// ensure that no later memory access can be reordered ahead of the operation.
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// "Release" operations ensure that no previous memory access can be reordered
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// after the operation. "Barrier" operations have both "Acquire" and "Release"
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// semantics. A MemoryBarrier() has "Barrier" semantics, but does no memory
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inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 new_value) {
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Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 new_value) {
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return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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inline void MemoryBarrier() {
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__asm__ __volatile__("sync" : : : "memory");
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
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inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
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inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
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Atomic32 value = *ptr;
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inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
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} // namespace base::subtle
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#endif // BASE_ATOMICOPS_INTERNALS_MIPS_GCC_H_