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Viewing changes to pci/oxygen/cs4398.h

  • Committer: Canonistack server
  • Date: 2015-01-22 13:04:34 UTC
  • Revision ID: david.henningsson@canonical.com-20150122130434-q48cfdp8ovzgqhe7
Test run of 623 machines: 3 failing with 3 errors and 0 warnings.

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Lines of Context:
pci/oxygen/cs4398.h
 
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/* register 1 */
 
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#define CS4398_REV_MASK         0x07
 
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#define CS4398_PART_MASK        0xf8
 
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#define CS4398_PART_CS4398      0x70
 
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/* register 2 */
 
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#define CS4398_FM_MASK          0x03
 
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#define CS4398_FM_SINGLE        0x00
 
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#define CS4398_FM_DOUBLE        0x01
 
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#define CS4398_FM_QUAD          0x02
 
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#define CS4398_FM_DSD           0x03
 
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#define CS4398_DEM_MASK         0x0c
 
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#define CS4398_DEM_NONE         0x00
 
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#define CS4398_DEM_44100        0x04
 
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#define CS4398_DEM_48000        0x08
 
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#define CS4398_DEM_32000        0x0c
 
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#define CS4398_DIF_MASK         0x70
 
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#define CS4398_DIF_LJUST        0x00
 
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#define CS4398_DIF_I2S          0x10
 
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#define CS4398_DIF_RJUST_16     0x20
 
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#define CS4398_DIF_RJUST_24     0x30
 
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#define CS4398_DIF_RJUST_20     0x40
 
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#define CS4398_DIF_RJUST_18     0x50
 
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#define CS4398_DSD_SRC          0x80
 
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/* register 3 */
 
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#define CS4398_ATAPI_MASK       0x1f
 
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#define CS4398_ATAPI_B_MUTE     0x00
 
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#define CS4398_ATAPI_B_R        0x01
 
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#define CS4398_ATAPI_B_L        0x02
 
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#define CS4398_ATAPI_B_LR       0x03
 
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#define CS4398_ATAPI_A_MUTE     0x00
 
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#define CS4398_ATAPI_A_R        0x04
 
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#define CS4398_ATAPI_A_L        0x08
 
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#define CS4398_ATAPI_A_LR       0x0c
 
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#define CS4398_ATAPI_MIX_LR_VOL 0x10
 
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#define CS4398_INVERT_B         0x20
 
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#define CS4398_INVERT_A         0x40
 
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#define CS4398_VOL_B_EQ_A       0x80
 
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/* register 4 */
 
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#define CS4398_MUTEP_MASK       0x03
 
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#define CS4398_MUTEP_AUTO       0x00
 
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#define CS4398_MUTEP_LOW        0x02
 
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#define CS4398_MUTEP_HIGH       0x03
 
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#define CS4398_MUTE_B           0x08
 
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#define CS4398_MUTE_A           0x10
 
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#define CS4398_MUTEC_A_EQ_B     0x20
 
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#define CS4398_DAMUTE           0x40
 
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#define CS4398_PAMUTE           0x80
 
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/* register 5 */
 
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#define CS4398_VOL_A_MASK       0xff
 
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/* register 6 */
 
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#define CS4398_VOL_B_MASK       0xff
 
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/* register 7 */
 
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#define CS4398_DIR_DSD          0x01
 
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#define CS4398_FILT_SEL         0x04
 
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#define CS4398_RMP_DN           0x10
 
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#define CS4398_RMP_UP           0x20
 
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#define CS4398_ZERO_CROSS       0x40
 
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#define CS4398_SOFT_RAMP        0x80
 
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/* register 8 */
 
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#define CS4398_MCLKDIV3         0x08
 
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#define CS4398_MCLKDIV2         0x10
 
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#define CS4398_FREEZE           0x20
 
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#define CS4398_CPEN             0x40
 
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#define CS4398_PDN              0x80
 
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/* register 9 */
 
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#define CS4398_DSD_PM_EN        0x01
 
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#define CS4398_DSD_PM_MODE      0x02
 
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#define CS4398_INVALID_DSD      0x04
 
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#define CS4398_STATIC_DSD       0x08