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// Copyright (c) 1994-2006 Sun Microsystems Inc.
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// All Rights Reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// - Redistribution in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// - Neither the name of Sun Microsystems or the names of contributors may
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// be used to endorse or promote products derived from this software without
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// specific prior written permission.
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// The original source code covered by the above license above has been
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// modified significantly by Google Inc.
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// Copyright 2012 the V8 project authors. All rights reserved.
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// A lightweight X64 Assembler.
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#ifndef V8_X64_ASSEMBLER_X64_H_
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#define V8_X64_ASSEMBLER_X64_H_
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#include "serialize.h"
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// Test whether a 64-bit value is in a specific range.
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inline bool is_uint32(int64_t x) {
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static const uint64_t kMaxUInt32 = V8_UINT64_C(0xffffffff);
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return static_cast<uint64_t>(x) <= kMaxUInt32;
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inline bool is_int32(int64_t x) {
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static const int64_t kMinInt32 = -V8_INT64_C(0x80000000);
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return is_uint32(x - kMinInt32);
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inline bool uint_is_int32(uint64_t x) {
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static const uint64_t kMaxInt32 = V8_UINT64_C(0x7fffffff);
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return x <= kMaxInt32;
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inline bool is_uint32(uint64_t x) {
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static const uint64_t kMaxUInt32 = V8_UINT64_C(0xffffffff);
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return x <= kMaxUInt32;
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// 1) We would prefer to use an enum, but enum values are assignment-
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// compatible with int, which has caused code-generation bugs.
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// 2) We would prefer to use a class instead of a struct but we don't like
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// the register initialization to depend on the particular initialization
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// order (which appears to be different on OS X, Linux, and Windows for the
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// installed versions of C++ we tried). Using a struct permits C-style
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// "initialization". Also, the Register objects cannot be const as this
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// forces initialization stubs in MSVC, making us dependent on initialization
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// 3) By not using an enum, we are possibly preventing the compiler from
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// doing certain constant folds, which may significantly reduce the
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// code generated for some assembly instructions (because they boil down
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// to a few constants). If this is a problem, we could change the code
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// such that we use an enum in optimized mode, and the struct in debug
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// mode. This way we get the compile-time error checking in debug mode
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// and best performance in optimized code.
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// The non-allocatable registers are:
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// rsp - stack pointer
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// rbp - frame pointer
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// rsi - context register
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// r10 - fixed scratch register
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// r12 - smi constant register
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// r13 - root register
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static const int kNumRegisters = 16;
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static const int kNumAllocatableRegisters = 10;
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static int ToAllocationIndex(Register reg) {
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return kAllocationIndexByRegisterCode[reg.code()];
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static Register FromAllocationIndex(int index) {
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ASSERT(index >= 0 && index < kNumAllocatableRegisters);
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Register result = { kRegisterCodeByAllocationIndex[index] };
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static const char* AllocationIndexToString(int index) {
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ASSERT(index >= 0 && index < kNumAllocatableRegisters);
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const char* const names[] = {
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static Register from_code(int code) {
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Register r = { code };
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bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
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bool is(Register reg) const { return code_ == reg.code_; }
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// rax, rbx, rcx and rdx are byte registers, the rest are not.
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bool is_byte_register() const { return code_ <= 3; }
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// Return the high bit of the register code as a 0 or 1. Used often
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// when constructing the REX prefix byte.
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int high_bit() const {
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// Return the 3 low bits of the register code. Used when encoding registers
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// in modR/M, SIB, and opcode bytes.
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int low_bits() const {
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// Unfortunately we can't make this private in a struct when initializing
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static const int kRegisterCodeByAllocationIndex[kNumAllocatableRegisters];
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static const int kAllocationIndexByRegisterCode[kNumRegisters];
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const int kRegister_rax_Code = 0;
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const int kRegister_rcx_Code = 1;
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const int kRegister_rdx_Code = 2;
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const int kRegister_rbx_Code = 3;
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const int kRegister_rsp_Code = 4;
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const int kRegister_rbp_Code = 5;
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const int kRegister_rsi_Code = 6;
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const int kRegister_rdi_Code = 7;
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const int kRegister_r8_Code = 8;
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const int kRegister_r9_Code = 9;
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const int kRegister_r10_Code = 10;
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const int kRegister_r11_Code = 11;
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const int kRegister_r12_Code = 12;
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const int kRegister_r13_Code = 13;
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const int kRegister_r14_Code = 14;
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const int kRegister_r15_Code = 15;
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const int kRegister_no_reg_Code = -1;
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const Register rax = { kRegister_rax_Code };
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const Register rcx = { kRegister_rcx_Code };
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const Register rdx = { kRegister_rdx_Code };
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const Register rbx = { kRegister_rbx_Code };
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const Register rsp = { kRegister_rsp_Code };
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const Register rbp = { kRegister_rbp_Code };
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const Register rsi = { kRegister_rsi_Code };
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const Register rdi = { kRegister_rdi_Code };
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const Register r8 = { kRegister_r8_Code };
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const Register r9 = { kRegister_r9_Code };
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const Register r10 = { kRegister_r10_Code };
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const Register r11 = { kRegister_r11_Code };
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const Register r12 = { kRegister_r12_Code };
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const Register r13 = { kRegister_r13_Code };
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const Register r14 = { kRegister_r14_Code };
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const Register r15 = { kRegister_r15_Code };
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const Register no_reg = { kRegister_no_reg_Code };
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static const int kNumRegisters = 16;
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static const int kNumAllocatableRegisters = 15;
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static int ToAllocationIndex(XMMRegister reg) {
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ASSERT(reg.code() != 0);
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return reg.code() - 1;
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static XMMRegister FromAllocationIndex(int index) {
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ASSERT(0 <= index && index < kNumAllocatableRegisters);
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XMMRegister result = { index + 1 };
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static const char* AllocationIndexToString(int index) {
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ASSERT(index >= 0 && index < kNumAllocatableRegisters);
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const char* const names[] = {
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static XMMRegister from_code(int code) {
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ASSERT(code < kNumRegisters);
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XMMRegister r = { code };
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bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
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bool is(XMMRegister reg) const { return code_ == reg.code_; }
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// Return the high bit of the register code as a 0 or 1. Used often
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// when constructing the REX prefix byte.
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int high_bit() const {
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// Return the 3 low bits of the register code. Used when encoding registers
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// in modR/M, SIB, and opcode bytes.
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int low_bits() const {
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const XMMRegister xmm0 = { 0 };
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const XMMRegister xmm1 = { 1 };
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const XMMRegister xmm2 = { 2 };
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const XMMRegister xmm3 = { 3 };
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const XMMRegister xmm4 = { 4 };
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const XMMRegister xmm5 = { 5 };
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const XMMRegister xmm6 = { 6 };
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const XMMRegister xmm7 = { 7 };
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const XMMRegister xmm8 = { 8 };
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const XMMRegister xmm9 = { 9 };
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const XMMRegister xmm10 = { 10 };
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const XMMRegister xmm11 = { 11 };
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const XMMRegister xmm12 = { 12 };
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const XMMRegister xmm13 = { 13 };
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const XMMRegister xmm14 = { 14 };
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const XMMRegister xmm15 = { 15 };
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typedef XMMRegister DoubleRegister;
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// any value < 0 is considered no_condition
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// Fake conditions that are handled by the
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// opcodes using them.
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not_carry = above_equal,
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not_zero = not_equal,
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last_condition = greater
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// Returns the equivalent of !cc.
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// Negation of the default no_condition (-1) results in a non-default
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// no_condition value (-2). As long as tests for no_condition check
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// for condition < 0, this will work as expected.
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inline Condition NegateCondition(Condition cc) {
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return static_cast<Condition>(cc ^ 1);
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// Corresponds to transposing the operands of a comparison.
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inline Condition ReverseCondition(Condition cc) {
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return greater_equal;
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// -----------------------------------------------------------------------------
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// Machine instruction Immediates
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class Immediate BASE_EMBEDDED {
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explicit Immediate(int32_t value) : value_(value) {}
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friend class Assembler;
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// -----------------------------------------------------------------------------
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// Machine instruction Operands
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times_int_size = times_4,
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times_pointer_size = times_8
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class Operand BASE_EMBEDDED {
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Operand(Register base, int32_t disp);
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// [base + index*scale + disp/r]
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Operand(Register base,
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// [index*scale + disp/r]
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Operand(Register index,
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// Offset from existing memory operand.
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// Offset is added to existing displacement as 32-bit signed values and
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// this must not overflow.
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Operand(const Operand& base, int32_t offset);
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// Checks whether either base or index register is the given register.
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// Does not check the "reg" part of the Operand.
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bool AddressUsesRegister(Register reg) const;
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// Queries related to the size of the generated instruction.
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// Whether the generated instruction will have a REX prefix.
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bool requires_rex() const { return rex_ != 0; }
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// Size of the ModR/M, SIB and displacement parts of the generated
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int operand_size() const { return len_; }
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// The number of bytes of buf_ in use.
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// Set the ModR/M byte without an encoded 'reg' register. The
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// register is encoded later as part of the emit_operand operation.
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// set_modrm can be called before or after set_sib and set_disp*.
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inline void set_modrm(int mod, Register rm);
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// Set the SIB byte if one is needed. Sets the length to 2 rather than 1.
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inline void set_sib(ScaleFactor scale, Register index, Register base);
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// Adds operand displacement fields (offsets added to the memory address).
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// Needs to be called after set_sib, not before it.
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inline void set_disp8(int disp);
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inline void set_disp32(int disp);
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friend class Assembler;
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// CpuFeatures keeps track of which features are supported by the target CPU.
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// Supported features must be enabled by a Scope before use.
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// if (CpuFeatures::IsSupported(SSE3)) {
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// CpuFeatures::Scope fscope(SSE3);
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// // Generate SSE3 floating point code.
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// // Generate standard x87 or SSE2 floating point code.
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class CpuFeatures : public AllStatic {
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// Detect features of the target CPU. Set safe defaults if the serializer
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// is enabled (snapshots must be portable).
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// Check whether a feature is supported by the target CPU.
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static bool IsSupported(CpuFeature f) {
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ASSERT(initialized_);
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if (f == SSE2 && !FLAG_enable_sse2) return false;
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if (f == SSE3 && !FLAG_enable_sse3) return false;
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if (f == SSE4_1 && !FLAG_enable_sse4_1) return false;
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if (f == CMOV && !FLAG_enable_cmov) return false;
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if (f == RDTSC && !FLAG_enable_rdtsc) return false;
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if (f == SAHF && !FLAG_enable_sahf) return false;
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return (supported_ & (V8_UINT64_C(1) << f)) != 0;
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// Check whether a feature is currently enabled.
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static bool IsEnabled(CpuFeature f) {
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ASSERT(initialized_);
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Isolate* isolate = Isolate::UncheckedCurrent();
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if (isolate == NULL) {
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// When no isolate is available, work as if we're running in
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return IsSupported(f);
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uint64_t enabled = isolate->enabled_cpu_features();
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return (enabled & (V8_UINT64_C(1) << f)) != 0;
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// Enable a specified feature within a scope.
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class Scope BASE_EMBEDDED {
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explicit Scope(CpuFeature f) {
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uint64_t mask = V8_UINT64_C(1) << f;
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ASSERT(CpuFeatures::IsSupported(f));
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ASSERT(!Serializer::enabled() ||
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(CpuFeatures::found_by_runtime_probing_ & mask) == 0);
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isolate_ = Isolate::UncheckedCurrent();
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if (isolate_ != NULL) {
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old_enabled_ = isolate_->enabled_cpu_features();
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isolate_->set_enabled_cpu_features(old_enabled_ | mask);
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ASSERT_EQ(Isolate::UncheckedCurrent(), isolate_);
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if (isolate_ != NULL) {
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isolate_->set_enabled_cpu_features(old_enabled_);
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uint64_t old_enabled_;
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explicit Scope(CpuFeature f) {}
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// Safe defaults include SSE2 and CMOV for X64. It is always available, if
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// anyone checks, but they shouldn't need to check.
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// The required user mode extensions in X64 are (from AMD64 ABI Table A.1):
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// fpu, tsc, cx8, cmov, mmx, sse, sse2, fxsr, syscall
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static const uint64_t kDefaultCpuFeatures = (1 << SSE2 | 1 << CMOV);
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static bool initialized_;
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static uint64_t supported_;
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static uint64_t found_by_runtime_probing_;
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DISALLOW_COPY_AND_ASSIGN(CpuFeatures);
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class Assembler : public AssemblerBase {
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// We check before assembling an instruction that there is sufficient
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// space to write an instruction and its relocation information.
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// The relocation writer's position must be kGap bytes above the end of
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// the generated instructions. This leaves enough space for the
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// longest possible x64 instruction, 15 bytes, and the longest possible
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// relocation information encoding, RelocInfoWriter::kMaxLength == 16.
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// (There is a 15 byte limit on x64 instruction length that rules out some
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// otherwise valid instructions.)
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// This allows for a single, fast space check per instruction.
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static const int kGap = 32;
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// Create an assembler. Instructions and relocation information are emitted
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// into a buffer, with the instructions starting from the beginning and the
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// relocation information starting from the end of the buffer. See CodeDesc
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// for a detailed comment on the layout (globals.h).
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// If the provided buffer is NULL, the assembler allocates and grows its own
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// buffer, and buffer_size determines the initial buffer size. The buffer is
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// owned by the assembler and deallocated upon destruction of the assembler.
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// If the provided buffer is not NULL, the assembler uses the provided buffer
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// for code generation and assumes its size to be buffer_size. If the buffer
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// is too small, a fatal error occurs. No deallocation of the buffer is done
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// upon destruction of the assembler.
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Assembler(Isolate* isolate, void* buffer, int buffer_size);
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// Overrides the default provided by FLAG_debug_code.
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void set_emit_debug_code(bool value) { emit_debug_code_ = value; }
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// Avoids using instructions that vary in size in unpredictable ways between
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// the snapshot and the running VM. This is needed by the full compiler so
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// that it can recompile code with debug support and fix the PC.
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void set_predictable_code_size(bool value) { predictable_code_size_ = value; }
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// GetCode emits any pending (non-emitted) code and fills the descriptor
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// desc. GetCode() is idempotent; it returns the same result if no other
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// Assembler functions are invoked in between GetCode() calls.
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void GetCode(CodeDesc* desc);
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// Read/Modify the code target in the relative branch/call instruction at pc.
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// On the x64 architecture, we use relative jumps with a 32-bit displacement
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// to jump to other Code objects in the Code space in the heap.
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// Jumps to C functions are done indirectly through a 64-bit register holding
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// the absolute address of the target.
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// These functions convert between absolute Addresses of Code objects and
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// the relative displacements stored in the code.
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static inline Address target_address_at(Address pc);
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static inline void set_target_address_at(Address pc, Address target);
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// This sets the branch destination (which is in the instruction on x64).
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// This is for calls and branches within generated code.
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inline static void deserialization_set_special_target_at(
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Address instruction_payload, Address target) {
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set_target_address_at(instruction_payload, target);
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// This sets the branch destination (which is a load instruction on x64).
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// This is for calls and branches to runtime code.
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inline static void set_external_target_at(Address instruction_payload,
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*reinterpret_cast<Address*>(instruction_payload) = target;
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inline Handle<Object> code_target_object_handle_at(Address pc);
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// Number of bytes taken up by the branch target in the code.
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static const int kSpecialTargetSize = 4; // Use 32-bit displacement.
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// Distance between the address of the code target in the call instruction
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// and the return address pushed on the stack.
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static const int kCallTargetAddressOffset = 4; // Use 32-bit displacement.
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// Distance between the start of the JS return sequence and where the
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// 32-bit displacement of a near call would be, relative to the pushed
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// return address. TODO: Use return sequence length instead.
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// Should equal Debug::kX64JSReturnSequenceLength - kCallTargetAddressOffset;
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static const int kPatchReturnSequenceAddressOffset = 13 - 4;
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// Distance between start of patched debug break slot and where the
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// 32-bit displacement of a near call would be, relative to the pushed
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// return address. TODO: Use return sequence length instead.
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// Should equal Debug::kX64JSReturnSequenceLength - kCallTargetAddressOffset;
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static const int kPatchDebugBreakSlotAddressOffset = 13 - 4;
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// TODO(X64): Rename this, removing the "Real", after changing the above.
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static const int kRealPatchReturnSequenceAddressOffset = 2;
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// Some x64 JS code is padded with int3 to make it large
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// enough to hold an instruction when the debugger patches it.
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static const int kJumpInstructionLength = 13;
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static const int kCallInstructionLength = 13;
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static const int kJSReturnSequenceLength = 13;
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static const int kShortCallInstructionLength = 5;
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// The debug break slot must be able to contain a call instruction.
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static const int kDebugBreakSlotLength = kCallInstructionLength;
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// One byte opcode for test eax,0xXXXXXXXX.
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static const byte kTestEaxByte = 0xA9;
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// One byte opcode for test al, 0xXX.
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static const byte kTestAlByte = 0xA8;
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// One byte opcode for nop.
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static const byte kNopByte = 0x90;
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// One byte prefix for a short conditional jump.
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static const byte kJccShortPrefix = 0x70;
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static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
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static const byte kJcShortOpcode = kJccShortPrefix | carry;
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static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
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static const byte kJzShortOpcode = kJccShortPrefix | zero;
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// ---------------------------------------------------------------------------
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// Function names correspond one-to-one to x64 instruction mnemonics.
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// Unless specified otherwise, instructions operate on 64-bit operands.
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// If we need versions of an assembly instruction that operate on different
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// width arguments, we add a single-letter suffix specifying the width.
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// This is done for the following instructions: mov, cmp, inc, dec,
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// add, sub, and test.
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// There are no versions of these instructions without the suffix.
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// - Instructions on 8-bit (byte) operands/registers have a trailing 'b'.
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// - Instructions on 16-bit (word) operands/registers have a trailing 'w'.
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// - Instructions on 32-bit (doubleword) operands/registers use 'l'.
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// - Instructions on 64-bit (quadword) operands/registers use 'q'.
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// Some mnemonics, such as "and", are the same as C++ keywords.
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// Naming conflicts with C++ keywords are resolved by adding a trailing '_'.
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// Insert the smallest number of nop instructions
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// possible to align the pc offset to a multiple
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// of m, where m must be a power of 2.
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void Nop(int bytes = 1);
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// Aligns code to something that's optimal for a jump target for the platform.
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void CodeTargetAlign();
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void push(Immediate value);
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// Push a 32 bit integer, and guarantee that it is actually pushed as a
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// 32 bit value, the normal push will optimize the 8 bit case.
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void push_imm32(int32_t imm32);
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void push(Register src);
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void push(const Operand& src);
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void pop(Register dst);
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void pop(const Operand& dst);
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void enter(Immediate size);
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void movb(Register dst, const Operand& src);
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void movb(Register dst, Immediate imm);
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void movb(const Operand& dst, Register src);
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// Move the low 16 bits of a 64-bit register value to a 16-bit
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void movw(const Operand& dst, Register src);
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void movl(Register dst, Register src);
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void movl(Register dst, const Operand& src);
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void movl(const Operand& dst, Register src);
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void movl(const Operand& dst, Immediate imm);
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// Load a 32-bit immediate value, zero-extended to 64 bits.
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void movl(Register dst, Immediate imm32);
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// Move 64 bit register value to 64-bit memory location.
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void movq(const Operand& dst, Register src);
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// Move 64 bit memory location to 64-bit register value.
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void movq(Register dst, const Operand& src);
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void movq(Register dst, Register src);
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// Sign extends immediate 32-bit value to 64 bits.
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void movq(Register dst, Immediate x);
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// Move the offset of the label location relative to the current
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// position (after the move) to the destination.
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void movl(const Operand& dst, Label* src);
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// Move sign extended immediate to memory location.
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void movq(const Operand& dst, Immediate value);
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// Instructions to load a 64-bit immediate into a register.
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// All 64-bit immediates must have a relocation mode.
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void movq(Register dst, void* ptr, RelocInfo::Mode rmode);
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void movq(Register dst, int64_t value, RelocInfo::Mode rmode);
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void movq(Register dst, const char* s, RelocInfo::Mode rmode);
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// Moves the address of the external reference into the register.
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void movq(Register dst, ExternalReference ext);
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void movq(Register dst, Handle<Object> handle, RelocInfo::Mode rmode);
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void movsxbq(Register dst, const Operand& src);
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void movsxwq(Register dst, const Operand& src);
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void movsxlq(Register dst, Register src);
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void movsxlq(Register dst, const Operand& src);
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void movzxbq(Register dst, const Operand& src);
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void movzxbl(Register dst, const Operand& src);
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void movzxwq(Register dst, const Operand& src);
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void movzxwl(Register dst, const Operand& src);
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// Instruction to load from an immediate 64-bit pointer into RAX.
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void load_rax(void* ptr, RelocInfo::Mode rmode);
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void load_rax(ExternalReference ext);
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// Conditional moves.
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void cmovq(Condition cc, Register dst, Register src);
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void cmovq(Condition cc, Register dst, const Operand& src);
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void cmovl(Condition cc, Register dst, Register src);
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void cmovl(Condition cc, Register dst, const Operand& src);
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// Exchange two registers
751
void xchg(Register dst, Register src);
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void addl(Register dst, Register src) {
755
arithmetic_op_32(0x03, dst, src);
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void addl(Register dst, Immediate src) {
759
immediate_arithmetic_op_32(0x0, dst, src);
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void addl(Register dst, const Operand& src) {
763
arithmetic_op_32(0x03, dst, src);
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void addl(const Operand& dst, Immediate src) {
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immediate_arithmetic_op_32(0x0, dst, src);
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void addl(const Operand& dst, Register src) {
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arithmetic_op_32(0x01, src, dst);
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void addq(Register dst, Register src) {
775
arithmetic_op(0x03, dst, src);
778
void addq(Register dst, const Operand& src) {
779
arithmetic_op(0x03, dst, src);
782
void addq(const Operand& dst, Register src) {
783
arithmetic_op(0x01, src, dst);
786
void addq(Register dst, Immediate src) {
787
immediate_arithmetic_op(0x0, dst, src);
790
void addq(const Operand& dst, Immediate src) {
791
immediate_arithmetic_op(0x0, dst, src);
794
void sbbl(Register dst, Register src) {
795
arithmetic_op_32(0x1b, dst, src);
798
void sbbq(Register dst, Register src) {
799
arithmetic_op(0x1b, dst, src);
802
void cmpb(Register dst, Immediate src) {
803
immediate_arithmetic_op_8(0x7, dst, src);
806
void cmpb_al(Immediate src);
808
void cmpb(Register dst, Register src) {
809
arithmetic_op(0x3A, dst, src);
812
void cmpb(Register dst, const Operand& src) {
813
arithmetic_op(0x3A, dst, src);
816
void cmpb(const Operand& dst, Register src) {
817
arithmetic_op(0x38, src, dst);
820
void cmpb(const Operand& dst, Immediate src) {
821
immediate_arithmetic_op_8(0x7, dst, src);
824
void cmpw(const Operand& dst, Immediate src) {
825
immediate_arithmetic_op_16(0x7, dst, src);
828
void cmpw(Register dst, Immediate src) {
829
immediate_arithmetic_op_16(0x7, dst, src);
832
void cmpw(Register dst, const Operand& src) {
833
arithmetic_op_16(0x3B, dst, src);
836
void cmpw(Register dst, Register src) {
837
arithmetic_op_16(0x3B, dst, src);
840
void cmpw(const Operand& dst, Register src) {
841
arithmetic_op_16(0x39, src, dst);
844
void cmpl(Register dst, Register src) {
845
arithmetic_op_32(0x3B, dst, src);
848
void cmpl(Register dst, const Operand& src) {
849
arithmetic_op_32(0x3B, dst, src);
852
void cmpl(const Operand& dst, Register src) {
853
arithmetic_op_32(0x39, src, dst);
856
void cmpl(Register dst, Immediate src) {
857
immediate_arithmetic_op_32(0x7, dst, src);
860
void cmpl(const Operand& dst, Immediate src) {
861
immediate_arithmetic_op_32(0x7, dst, src);
864
void cmpq(Register dst, Register src) {
865
arithmetic_op(0x3B, dst, src);
868
void cmpq(Register dst, const Operand& src) {
869
arithmetic_op(0x3B, dst, src);
872
void cmpq(const Operand& dst, Register src) {
873
arithmetic_op(0x39, src, dst);
876
void cmpq(Register dst, Immediate src) {
877
immediate_arithmetic_op(0x7, dst, src);
880
void cmpq(const Operand& dst, Immediate src) {
881
immediate_arithmetic_op(0x7, dst, src);
884
void and_(Register dst, Register src) {
885
arithmetic_op(0x23, dst, src);
888
void and_(Register dst, const Operand& src) {
889
arithmetic_op(0x23, dst, src);
892
void and_(const Operand& dst, Register src) {
893
arithmetic_op(0x21, src, dst);
896
void and_(Register dst, Immediate src) {
897
immediate_arithmetic_op(0x4, dst, src);
900
void and_(const Operand& dst, Immediate src) {
901
immediate_arithmetic_op(0x4, dst, src);
904
void andl(Register dst, Immediate src) {
905
immediate_arithmetic_op_32(0x4, dst, src);
908
void andl(Register dst, Register src) {
909
arithmetic_op_32(0x23, dst, src);
912
void andl(Register dst, const Operand& src) {
913
arithmetic_op_32(0x23, dst, src);
916
void andb(Register dst, Immediate src) {
917
immediate_arithmetic_op_8(0x4, dst, src);
920
void decq(Register dst);
921
void decq(const Operand& dst);
922
void decl(Register dst);
923
void decl(const Operand& dst);
924
void decb(Register dst);
925
void decb(const Operand& dst);
927
// Sign-extends rax into rdx:rax.
929
// Sign-extends eax into edx:eax.
932
// Divide rdx:rax by src. Quotient in rax, remainder in rdx.
933
void idivq(Register src);
934
// Divide edx:eax by lower 32 bits of src. Quotient in eax, rem. in edx.
935
void idivl(Register src);
937
// Signed multiply instructions.
938
void imul(Register src); // rdx:rax = rax * src.
939
void imul(Register dst, Register src); // dst = dst * src.
940
void imul(Register dst, const Operand& src); // dst = dst * src.
941
void imul(Register dst, Register src, Immediate imm); // dst = src * imm.
942
// Signed 32-bit multiply instructions.
943
void imull(Register dst, Register src); // dst = dst * src.
944
void imull(Register dst, const Operand& src); // dst = dst * src.
945
void imull(Register dst, Register src, Immediate imm); // dst = src * imm.
947
void incq(Register dst);
948
void incq(const Operand& dst);
949
void incl(Register dst);
950
void incl(const Operand& dst);
952
void lea(Register dst, const Operand& src);
953
void leal(Register dst, const Operand& src);
955
// Multiply rax by src, put the result in rdx:rax.
956
void mul(Register src);
958
void neg(Register dst);
959
void neg(const Operand& dst);
960
void negl(Register dst);
962
void not_(Register dst);
963
void not_(const Operand& dst);
964
void notl(Register dst);
966
void or_(Register dst, Register src) {
967
arithmetic_op(0x0B, dst, src);
970
void orl(Register dst, Register src) {
971
arithmetic_op_32(0x0B, dst, src);
974
void or_(Register dst, const Operand& src) {
975
arithmetic_op(0x0B, dst, src);
978
void orl(Register dst, const Operand& src) {
979
arithmetic_op_32(0x0B, dst, src);
982
void or_(const Operand& dst, Register src) {
983
arithmetic_op(0x09, src, dst);
986
void or_(Register dst, Immediate src) {
987
immediate_arithmetic_op(0x1, dst, src);
990
void orl(Register dst, Immediate src) {
991
immediate_arithmetic_op_32(0x1, dst, src);
994
void or_(const Operand& dst, Immediate src) {
995
immediate_arithmetic_op(0x1, dst, src);
998
void orl(const Operand& dst, Immediate src) {
999
immediate_arithmetic_op_32(0x1, dst, src);
1003
void rcl(Register dst, Immediate imm8) {
1004
shift(dst, imm8, 0x2);
1007
void rol(Register dst, Immediate imm8) {
1008
shift(dst, imm8, 0x0);
1011
void rcr(Register dst, Immediate imm8) {
1012
shift(dst, imm8, 0x3);
1015
void ror(Register dst, Immediate imm8) {
1016
shift(dst, imm8, 0x1);
1019
// Shifts dst:src left by cl bits, affecting only dst.
1020
void shld(Register dst, Register src);
1022
// Shifts src:dst right by cl bits, affecting only dst.
1023
void shrd(Register dst, Register src);
1025
// Shifts dst right, duplicating sign bit, by shift_amount bits.
1026
// Shifting by 1 is handled efficiently.
1027
void sar(Register dst, Immediate shift_amount) {
1028
shift(dst, shift_amount, 0x7);
1031
// Shifts dst right, duplicating sign bit, by shift_amount bits.
1032
// Shifting by 1 is handled efficiently.
1033
void sarl(Register dst, Immediate shift_amount) {
1034
shift_32(dst, shift_amount, 0x7);
1037
// Shifts dst right, duplicating sign bit, by cl % 64 bits.
1038
void sar_cl(Register dst) {
1042
// Shifts dst right, duplicating sign bit, by cl % 64 bits.
1043
void sarl_cl(Register dst) {
1047
void shl(Register dst, Immediate shift_amount) {
1048
shift(dst, shift_amount, 0x4);
1051
void shl_cl(Register dst) {
1055
void shll_cl(Register dst) {
1059
void shll(Register dst, Immediate shift_amount) {
1060
shift_32(dst, shift_amount, 0x4);
1063
void shr(Register dst, Immediate shift_amount) {
1064
shift(dst, shift_amount, 0x5);
1067
void shr_cl(Register dst) {
1071
void shrl_cl(Register dst) {
1075
void shrl(Register dst, Immediate shift_amount) {
1076
shift_32(dst, shift_amount, 0x5);
1079
void store_rax(void* dst, RelocInfo::Mode mode);
1080
void store_rax(ExternalReference ref);
1082
void subq(Register dst, Register src) {
1083
arithmetic_op(0x2B, dst, src);
1086
void subq(Register dst, const Operand& src) {
1087
arithmetic_op(0x2B, dst, src);
1090
void subq(const Operand& dst, Register src) {
1091
arithmetic_op(0x29, src, dst);
1094
void subq(Register dst, Immediate src) {
1095
immediate_arithmetic_op(0x5, dst, src);
1098
void subq(const Operand& dst, Immediate src) {
1099
immediate_arithmetic_op(0x5, dst, src);
1102
void subl(Register dst, Register src) {
1103
arithmetic_op_32(0x2B, dst, src);
1106
void subl(Register dst, const Operand& src) {
1107
arithmetic_op_32(0x2B, dst, src);
1110
void subl(const Operand& dst, Immediate src) {
1111
immediate_arithmetic_op_32(0x5, dst, src);
1114
void subl(Register dst, Immediate src) {
1115
immediate_arithmetic_op_32(0x5, dst, src);
1118
void subb(Register dst, Immediate src) {
1119
immediate_arithmetic_op_8(0x5, dst, src);
1122
void testb(Register dst, Register src);
1123
void testb(Register reg, Immediate mask);
1124
void testb(const Operand& op, Immediate mask);
1125
void testb(const Operand& op, Register reg);
1126
void testl(Register dst, Register src);
1127
void testl(Register reg, Immediate mask);
1128
void testl(const Operand& op, Immediate mask);
1129
void testq(const Operand& op, Register reg);
1130
void testq(Register dst, Register src);
1131
void testq(Register dst, Immediate mask);
1133
void xor_(Register dst, Register src) {
1134
if (dst.code() == src.code()) {
1135
arithmetic_op_32(0x33, dst, src);
1137
arithmetic_op(0x33, dst, src);
1141
void xorl(Register dst, Register src) {
1142
arithmetic_op_32(0x33, dst, src);
1145
void xorl(Register dst, const Operand& src) {
1146
arithmetic_op_32(0x33, dst, src);
1149
void xorl(Register dst, Immediate src) {
1150
immediate_arithmetic_op_32(0x6, dst, src);
1153
void xorl(const Operand& dst, Immediate src) {
1154
immediate_arithmetic_op_32(0x6, dst, src);
1157
void xor_(Register dst, const Operand& src) {
1158
arithmetic_op(0x33, dst, src);
1161
void xor_(const Operand& dst, Register src) {
1162
arithmetic_op(0x31, src, dst);
1165
void xor_(Register dst, Immediate src) {
1166
immediate_arithmetic_op(0x6, dst, src);
1169
void xor_(const Operand& dst, Immediate src) {
1170
immediate_arithmetic_op(0x6, dst, src);
1174
void bt(const Operand& dst, Register src);
1175
void bts(const Operand& dst, Register src);
1185
void ret(int imm16);
1186
void setcc(Condition cc, Register reg);
1188
// Label operations & relative jumps (PPUM Appendix D)
1190
// Takes a branch opcode (cc) and a label (L) and generates
1191
// either a backward branch or a forward branch and links it
1192
// to the label fixup chain. Usage:
1194
// Label L; // unbound label
1195
// j(cc, &L); // forward branch to unbound label
1196
// bind(&L); // bind label to the current pc
1197
// j(cc, &L); // backward branch to bound label
1198
// bind(&L); // illegal: a label may be bound only once
1200
// Note: The same Label can be used for forward and backward branches
1201
// but it may be bound only once.
1203
void bind(Label* L); // binds an unbound label L to the current code position
1206
// Call near relative 32-bit displacement, relative to next instruction.
1207
void call(Label* L);
1208
void call(Handle<Code> target,
1209
RelocInfo::Mode rmode = RelocInfo::CODE_TARGET,
1210
unsigned ast_id = kNoASTId);
1212
// Calls directly to the given address using a relative offset.
1213
// Should only ever be used in Code objects for calls within the
1214
// same Code object. Should not be used when generating new code (use labels),
1215
// but only when patching existing code.
1216
void call(Address target);
1218
// Call near absolute indirect, address in register
1219
void call(Register adr);
1221
// Call near indirect
1222
void call(const Operand& operand);
1225
// Jump short or near relative.
1226
// Use a 32-bit signed displacement.
1227
// Unconditional jump to L
1228
void jmp(Label* L, Label::Distance distance = Label::kFar);
1229
void jmp(Handle<Code> target, RelocInfo::Mode rmode);
1231
// Jump near absolute indirect (r64)
1232
void jmp(Register adr);
1234
// Jump near absolute indirect (m64)
1235
void jmp(const Operand& src);
1237
// Conditional jumps
1238
void j(Condition cc,
1240
Label::Distance distance = Label::kFar);
1241
void j(Condition cc, Handle<Code> target, RelocInfo::Mode rmode);
1243
// Floating-point operations
1251
void fld_s(const Operand& adr);
1252
void fld_d(const Operand& adr);
1254
void fstp_s(const Operand& adr);
1255
void fstp_d(const Operand& adr);
1256
void fstp(int index);
1258
void fild_s(const Operand& adr);
1259
void fild_d(const Operand& adr);
1261
void fist_s(const Operand& adr);
1263
void fistp_s(const Operand& adr);
1264
void fistp_d(const Operand& adr);
1266
void fisttp_s(const Operand& adr);
1267
void fisttp_d(const Operand& adr);
1277
void fisub_s(const Operand& adr);
1279
void faddp(int i = 1);
1280
void fsubp(int i = 1);
1281
void fsubrp(int i = 1);
1282
void fmulp(int i = 1);
1283
void fdivp(int i = 1);
1287
void fxch(int i = 1);
1289
void ffree(int i = 0);
1314
// SSE2 instructions
1315
void movd(XMMRegister dst, Register src);
1316
void movd(Register dst, XMMRegister src);
1317
void movq(XMMRegister dst, Register src);
1318
void movq(Register dst, XMMRegister src);
1319
void movq(XMMRegister dst, XMMRegister src);
1320
void extractps(Register dst, XMMRegister src, byte imm8);
1322
// Don't use this unless it's important to keep the
1323
// top half of the destination register unchanged.
1324
// Used movaps when moving double values and movq for integer
1325
// values in xmm registers.
1326
void movsd(XMMRegister dst, XMMRegister src);
1328
void movsd(const Operand& dst, XMMRegister src);
1329
void movsd(XMMRegister dst, const Operand& src);
1331
void movdqa(const Operand& dst, XMMRegister src);
1332
void movdqa(XMMRegister dst, const Operand& src);
1334
void movapd(XMMRegister dst, XMMRegister src);
1335
void movaps(XMMRegister dst, XMMRegister src);
1337
void movss(XMMRegister dst, const Operand& src);
1338
void movss(const Operand& dst, XMMRegister src);
1340
void cvttss2si(Register dst, const Operand& src);
1341
void cvttss2si(Register dst, XMMRegister src);
1342
void cvttsd2si(Register dst, const Operand& src);
1343
void cvttsd2si(Register dst, XMMRegister src);
1344
void cvttsd2siq(Register dst, XMMRegister src);
1346
void cvtlsi2sd(XMMRegister dst, const Operand& src);
1347
void cvtlsi2sd(XMMRegister dst, Register src);
1348
void cvtqsi2sd(XMMRegister dst, const Operand& src);
1349
void cvtqsi2sd(XMMRegister dst, Register src);
1351
void cvtlsi2ss(XMMRegister dst, Register src);
1353
void cvtss2sd(XMMRegister dst, XMMRegister src);
1354
void cvtss2sd(XMMRegister dst, const Operand& src);
1355
void cvtsd2ss(XMMRegister dst, XMMRegister src);
1357
void cvtsd2si(Register dst, XMMRegister src);
1358
void cvtsd2siq(Register dst, XMMRegister src);
1360
void addsd(XMMRegister dst, XMMRegister src);
1361
void subsd(XMMRegister dst, XMMRegister src);
1362
void mulsd(XMMRegister dst, XMMRegister src);
1363
void divsd(XMMRegister dst, XMMRegister src);
1365
void andpd(XMMRegister dst, XMMRegister src);
1366
void orpd(XMMRegister dst, XMMRegister src);
1367
void xorpd(XMMRegister dst, XMMRegister src);
1368
void xorps(XMMRegister dst, XMMRegister src);
1369
void sqrtsd(XMMRegister dst, XMMRegister src);
1371
void ucomisd(XMMRegister dst, XMMRegister src);
1372
void ucomisd(XMMRegister dst, const Operand& src);
1375
kRoundToNearest = 0x0,
1381
void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
1383
void movmskpd(Register dst, XMMRegister src);
1385
// The first argument is the reg field, the second argument is the r/m field.
1386
void emit_sse_operand(XMMRegister dst, XMMRegister src);
1387
void emit_sse_operand(XMMRegister reg, const Operand& adr);
1388
void emit_sse_operand(XMMRegister dst, Register src);
1389
void emit_sse_operand(Register dst, XMMRegister src);
1394
// Check the code size generated from label to here.
1395
int SizeOfCodeGeneratedSince(Label* label) {
1396
return pc_offset() - label->pos();
1399
// Mark address of the ExitJSFrame code.
1400
void RecordJSReturn();
1402
// Mark address of a debug break slot.
1403
void RecordDebugBreakSlot();
1405
// Record a comment relocation entry that can be used by a disassembler.
1406
// Use --code-comments to enable.
1407
void RecordComment(const char* msg, bool force = false);
1409
// Writes a single word of data in the code stream.
1410
// Used for inline tables, e.g., jump-tables.
1411
void db(uint8_t data);
1412
void dd(uint32_t data);
1414
int pc_offset() const { return static_cast<int>(pc_ - buffer_); }
1416
PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1418
// Check if there is less than kGap bytes available in the buffer.
1419
// If this is the case, we need to grow the buffer before emitting
1420
// an instruction or relocation information.
1421
inline bool buffer_overflow() const {
1422
return pc_ >= reloc_info_writer.pos() - kGap;
1425
// Get the number of bytes available in the buffer.
1426
inline int available_space() const {
1427
return static_cast<int>(reloc_info_writer.pos() - pc_);
1430
static bool IsNop(Address addr);
1432
// Avoid overflows for displacements etc.
1433
static const int kMaximalBufferSize = 512*MB;
1434
static const int kMinimalBufferSize = 4*KB;
1436
byte byte_at(int pos) { return buffer_[pos]; }
1437
void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
1440
bool emit_debug_code() const { return emit_debug_code_; }
1441
bool predictable_code_size() const { return predictable_code_size_; }
1444
byte* addr_at(int pos) { return buffer_ + pos; }
1445
uint32_t long_at(int pos) {
1446
return *reinterpret_cast<uint32_t*>(addr_at(pos));
1448
void long_at_put(int pos, uint32_t x) {
1449
*reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1455
void emit(byte x) { *pc_++ = x; }
1456
inline void emitl(uint32_t x);
1457
inline void emitq(uint64_t x, RelocInfo::Mode rmode);
1458
inline void emitw(uint16_t x);
1459
inline void emit_code_target(Handle<Code> target,
1460
RelocInfo::Mode rmode,
1461
unsigned ast_id = kNoASTId);
1462
void emit(Immediate x) { emitl(x.value_); }
1464
// Emits a REX prefix that encodes a 64-bit operand size and
1465
// the top bit of both register codes.
1466
// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1468
inline void emit_rex_64(XMMRegister reg, Register rm_reg);
1469
inline void emit_rex_64(Register reg, XMMRegister rm_reg);
1470
inline void emit_rex_64(Register reg, Register rm_reg);
1472
// Emits a REX prefix that encodes a 64-bit operand size and
1473
// the top bit of the destination, index, and base register codes.
1474
// The high bit of reg is used for REX.R, the high bit of op's base
1475
// register is used for REX.B, and the high bit of op's index register
1476
// is used for REX.X. REX.W is set.
1477
inline void emit_rex_64(Register reg, const Operand& op);
1478
inline void emit_rex_64(XMMRegister reg, const Operand& op);
1480
// Emits a REX prefix that encodes a 64-bit operand size and
1481
// the top bit of the register code.
1482
// The high bit of register is used for REX.B.
1483
// REX.W is set and REX.R and REX.X are clear.
1484
inline void emit_rex_64(Register rm_reg);
1486
// Emits a REX prefix that encodes a 64-bit operand size and
1487
// the top bit of the index and base register codes.
1488
// The high bit of op's base register is used for REX.B, and the high
1489
// bit of op's index register is used for REX.X.
1490
// REX.W is set and REX.R clear.
1491
inline void emit_rex_64(const Operand& op);
1493
// Emit a REX prefix that only sets REX.W to choose a 64-bit operand size.
1494
void emit_rex_64() { emit(0x48); }
1496
// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1498
inline void emit_rex_32(Register reg, Register rm_reg);
1500
// The high bit of reg is used for REX.R, the high bit of op's base
1501
// register is used for REX.B, and the high bit of op's index register
1502
// is used for REX.X. REX.W is cleared.
1503
inline void emit_rex_32(Register reg, const Operand& op);
1505
// High bit of rm_reg goes to REX.B.
1506
// REX.W, REX.R and REX.X are clear.
1507
inline void emit_rex_32(Register rm_reg);
1509
// High bit of base goes to REX.B and high bit of index to REX.X.
1510
// REX.W and REX.R are clear.
1511
inline void emit_rex_32(const Operand& op);
1513
// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1514
// REX.W is cleared. If no REX bits are set, no byte is emitted.
1515
inline void emit_optional_rex_32(Register reg, Register rm_reg);
1517
// The high bit of reg is used for REX.R, the high bit of op's base
1518
// register is used for REX.B, and the high bit of op's index register
1519
// is used for REX.X. REX.W is cleared. If no REX bits are set, nothing
1521
inline void emit_optional_rex_32(Register reg, const Operand& op);
1523
// As for emit_optional_rex_32(Register, Register), except that
1524
// the registers are XMM registers.
1525
inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base);
1527
// As for emit_optional_rex_32(Register, Register), except that
1528
// one of the registers is an XMM registers.
1529
inline void emit_optional_rex_32(XMMRegister reg, Register base);
1531
// As for emit_optional_rex_32(Register, Register), except that
1532
// one of the registers is an XMM registers.
1533
inline void emit_optional_rex_32(Register reg, XMMRegister base);
1535
// As for emit_optional_rex_32(Register, const Operand&), except that
1536
// the register is an XMM register.
1537
inline void emit_optional_rex_32(XMMRegister reg, const Operand& op);
1539
// Optionally do as emit_rex_32(Register) if the register number has
1540
// the high bit set.
1541
inline void emit_optional_rex_32(Register rm_reg);
1543
// Optionally do as emit_rex_32(const Operand&) if the operand register
1544
// numbers have a high bit set.
1545
inline void emit_optional_rex_32(const Operand& op);
1548
// Emit the ModR/M byte, and optionally the SIB byte and
1549
// 1- or 4-byte offset for a memory operand. Also encodes
1550
// the second operand of the operation, a register or operation
1551
// subcode, into the reg field of the ModR/M byte.
1552
void emit_operand(Register reg, const Operand& adr) {
1553
emit_operand(reg.low_bits(), adr);
1556
// Emit the ModR/M byte, and optionally the SIB byte and
1557
// 1- or 4-byte offset for a memory operand. Also used to encode
1558
// a three-bit opcode extension into the ModR/M byte.
1559
void emit_operand(int rm, const Operand& adr);
1561
// Emit a ModR/M byte with registers coded in the reg and rm_reg fields.
1562
void emit_modrm(Register reg, Register rm_reg) {
1563
emit(0xC0 | reg.low_bits() << 3 | rm_reg.low_bits());
1566
// Emit a ModR/M byte with an operation subcode in the reg field and
1567
// a register in the rm_reg field.
1568
void emit_modrm(int code, Register rm_reg) {
1569
ASSERT(is_uint3(code));
1570
emit(0xC0 | code << 3 | rm_reg.low_bits());
1573
// Emit the code-object-relative offset of the label's position
1574
inline void emit_code_relative_offset(Label* label);
1576
// Emit machine code for one of the operations ADD, ADC, SUB, SBC,
1577
// AND, OR, XOR, or CMP. The encodings of these operations are all
1578
// similar, differing just in the opcode or in the reg field of the
1580
void arithmetic_op_16(byte opcode, Register reg, Register rm_reg);
1581
void arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg);
1582
void arithmetic_op_32(byte opcode, Register reg, Register rm_reg);
1583
void arithmetic_op_32(byte opcode, Register reg, const Operand& rm_reg);
1584
void arithmetic_op(byte opcode, Register reg, Register rm_reg);
1585
void arithmetic_op(byte opcode, Register reg, const Operand& rm_reg);
1586
void immediate_arithmetic_op(byte subcode, Register dst, Immediate src);
1587
void immediate_arithmetic_op(byte subcode, const Operand& dst, Immediate src);
1588
// Operate on a byte in memory or register.
1589
void immediate_arithmetic_op_8(byte subcode,
1592
void immediate_arithmetic_op_8(byte subcode,
1595
// Operate on a word in memory or register.
1596
void immediate_arithmetic_op_16(byte subcode,
1599
void immediate_arithmetic_op_16(byte subcode,
1602
// Operate on a 32-bit word in memory or register.
1603
void immediate_arithmetic_op_32(byte subcode,
1606
void immediate_arithmetic_op_32(byte subcode,
1610
// Emit machine code for a shift operation.
1611
void shift(Register dst, Immediate shift_amount, int subcode);
1612
void shift_32(Register dst, Immediate shift_amount, int subcode);
1613
// Shift dst by cl % 64 bits.
1614
void shift(Register dst, int subcode);
1615
void shift_32(Register dst, int subcode);
1617
void emit_farith(int b1, int b2, int i);
1620
// void print(Label* L);
1621
void bind_to(Label* L, int pos);
1623
// record reloc info for current pc_
1624
void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1626
friend class CodePatcher;
1627
friend class EnsureSpace;
1628
friend class RegExpMacroAssemblerX64;
1631
// The buffer into which code and relocation info are generated.
1634
// True if the assembler owns the buffer, false if buffer is external.
1638
byte* pc_; // the program counter; moves forward
1639
RelocInfoWriter reloc_info_writer;
1641
List< Handle<Code> > code_targets_;
1643
PositionsRecorder positions_recorder_;
1645
bool emit_debug_code_;
1646
bool predictable_code_size_;
1648
friend class PositionsRecorder;
1652
// Helper class that ensures that there is enough space for generating
1653
// instructions and relocation information. The constructor makes
1654
// sure that there is enough space and (in debug mode) the destructor
1655
// checks that we did not generate too much.
1656
class EnsureSpace BASE_EMBEDDED {
1658
explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1659
if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
1661
space_before_ = assembler_->available_space();
1667
int bytes_generated = space_before_ - assembler_->available_space();
1668
ASSERT(bytes_generated < assembler_->kGap);
1673
Assembler* assembler_;
1679
} } // namespace v8::internal
1681
#endif // V8_X64_ASSEMBLER_X64_H_
added
removed
src/third_party/v8/src/x64/assembler-x64.h
