2
*-----------------------------------------------------------------------------
5
*-----------------------------------------------------------------------------
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* Copyright © 2002-2010, Intel Corporation.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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* This program is distributed in the hope it will be useful, but WITHOUT
13
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17
* You should have received a copy of the GNU General Public License along with
18
* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*-----------------------------------------------------------------------------
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* This is the implementation file for the register module's main API's called
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* by external devices.
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*-----------------------------------------------------------------------------
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#define MODULE_NAME hal.state
37
#include <igd_errno.h>
48
#include <plb/context.h>
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#include "../cmn/reg_dispatch.h"
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* @addtogroup state_group
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#define PLANE_LATCH_COUNT 4
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static reg_buffer_t *reg_alloc_tnc(igd_context_t *context,
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unsigned long flags, void *_platform_context);
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static void reg_free_tnc(igd_context_t *context, reg_buffer_t *reg_buffer,
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void *_platform_context);
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static int reg_save_tnc(igd_context_t *context, reg_buffer_t *reg_buffer,
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void *_platform_context);
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static int reg_restore_tnc(igd_context_t *context, reg_buffer_t *reg_buffer,
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void *_platform_context);
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/* GR registers being saved */
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static unsigned char gr_regs_tnc[] = {
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0x00, 0x01, 0x02, 0x03, 0x04,
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0x05, 0x06, 0x07, 0x08,
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#define GR_REG_COUNT sizeof(gr_regs_tnc)
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/* SR registers being saved */
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static unsigned char sr_regs_tnc[] = {
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0x00, 0x01, 0x02, 0x03, 0x04,
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#define SR_REG_COUNT sizeof(sr_regs_tnc)
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/* AR registers being saved */
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static unsigned char ar_regs_tnc[] = {
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0x00, 0x01, 0x02, 0x03, 0x04,
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0x05, 0x06, 0x07, 0x08, 0x09,
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0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
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0x0f, 0x10, 0x11, 0x12, 0x13,
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#define AR_REG_COUNT sizeof(ar_regs_tnc)
100
/* CR registers being saved */
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static unsigned char cr_regs_tnc[] = {
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0x00, 0x01, 0x02, 0x03, 0x04,
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0x05, 0x06, 0x07, 0x08, 0x09,
104
0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
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0x0f, 0x10, 0x11, 0x12, 0x13,
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0x14, 0x15, 0x16, 0x17, 0x18,
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#define CR_REG_COUNT sizeof(cr_regs_tnc)
112
/* MMIO states register to be saved */
113
static unsigned long mmio_regs_tnc[] = {
115
/* Fence Registers */
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FENCE0, FENCE1, FENCE2, FENCE3, FENCE4, FENCE5, FENCE6, FENCE7, // Fence
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FENCE8, FENCE9, FENCE10, FENCE11, FENCE12, FENCE13, FENCE14, FENCE15,
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/* Memory Arbitration */
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FW_BLC_SELF, MI_ARB_STATE, G_DEBUG,
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VGA0_DIVISOR, VGA1_DIVISOR, VGA_PD,
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FPA0, FPA1, FPB0, FPB1, P2D_CG_DIS,
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DPLLACNTR, DPLLBCNTR,
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/* SDVO Port Enable */
138
LVDS_PNL_PWR_CTL, PP_ON_DELAYS, PP_OFF_DELAYS, PP_DIVISOR,
141
PFIT_CONTROL, PFIT_PGM_RATIOS,
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/* Backlight Control */
144
BLC_PWM_CTL2, BLC_PWM_CTL, BLM_HIST_CTL,
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/* LVDS Port Enable */
150
PIPEA_STAT, PIPEA_DISP_ARB_CTRL, HTOTAL_A, HBLANK_A, HSYNC_A, VTOTAL_A,
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VBLANK_A, VSYNC_A, PIPEASRC, BCLRPAT_A,
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PIPEB_STAT, HTOTAL_B, HBLANK_B, HSYNC_B, VTOTAL_B,
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VBLANK_B, VSYNC_B, PIPEBSRC, BCLRPAT_B,
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PIPEA_CONF, PIPEB_CONF,
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DSPASTRIDE, DSPAKEYVAL, DSPAKEYMASK,
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DSPBSTRIDE, DSPBKEYVAL, DSPBKEYMASK,
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DSPCSTRIDE, DSPCPOS, DSPCSIZE, DSPCKEYMASK,
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DSPCKEYMINVAL, DSPCKEYMAXVAL, DCLRC0, DCLRC1, DPYC_GAMC5,
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DPYC_GAMC4, DPYC_GAMC3, DPYC_GAMC2, DPYC_GAMC1, DPYC_GAMC0,
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DSPCCNTR, DSPCLINOFF,
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DSPBCNTR, DSPBLINOFF,
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DSPACNTR, DSPALINOFF,
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/* Enable VGA Plane */
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/* Software Flags A */
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SWF00, SWF01, SWF02, SWF03, SWF04, SWF05, SWF06, SWF07,
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SWF08, SWF09, SWF0A, SWF0B, SWF0C, SWF0D, SWF0E, SWF0F,
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/* Software Flags B */
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SWF10, SWF11, SWF12, SWF13, SWF14, SWF15, SWF16, SWF17,
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SWF18, SWF19, SWF1A, SWF1B, SWF1C, SWF1D, SWF1E, SWF1F,
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CURSOR_A_BASE, CURSOR_A_POS, CURSOR_A_PAL0, CURSOR_A_PAL1,
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CURSOR_A_PAL2, CURSOR_A_PAL3,
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CURSOR_B_BASE, CURSOR_B_POS, CURSOR_B_PAL0, CURSOR_B_PAL1,
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CURSOR_B_PAL2, CURSOR_B_PAL3,
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/* Interrupt and hardware status */
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HWS_PGA, HWSTAM, SCPD0, IER, IMR, EIR, EMR,
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#define MMIO_REG_COUNT(x) (sizeof(mmio_regs_tnc)/4)
207
/* MMIO states register to be saved */
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static unsigned long mmio_regs_sdvo_tnc[] = {
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/* SDVO Port Enable */
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PIPEB_STAT, HTOTAL_B, HBLANK_B, HSYNC_B, VTOTAL_B,
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VBLANK_B, VSYNC_B, PIPEBSRC, BCLRPAT_B, PROG_STALL,
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CDVO_SLEW_RATE, CDVO_STRENGTH, CDVO_RCOMP_UPDATE,
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DPLL_ANACORE_CTRL, DPLL_MISC, DPLL_MONITOR, DPLL_MONITOR2,
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DPLL_TEST_COMPARATOR,
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/* Interrupt and hardware status */
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#define MMIO_REG_SDVO_COUNT(x) (sizeof(mmio_regs_sdvo_tnc)/4)
243
typedef struct _reg_platform_context_tnc {
244
unsigned long *mmio_regs;
245
unsigned long *mmio_regs_sdvo;
251
} reg_platform_context_tnc_t;
253
typedef struct _vga_state_tnc {
254
unsigned char fcr; // Feature Control register
255
unsigned char msr; // Miscellaneous Output register
256
unsigned char sr_index; // Sequencer index register
257
unsigned char cr_index; // CRT Controller index register
258
unsigned char ar_index; // Attribute Controller index register
259
unsigned char gr_index; // Graphics Controller index register
260
unsigned char ar[AR_REG_COUNT]; // Attribute Contr regs (AR00-AR14)
261
unsigned char sr[SR_REG_COUNT]; // Sequencer registers (SR01-SR04)
262
unsigned char cr[CR_REG_COUNT]; // CRT Controller regs (CR00-CR18)
263
unsigned char gr[GR_REG_COUNT]; // Graphics Contr regs
264
unsigned char plane_latches[PLANE_LATCH_COUNT];
267
#define DAC_DATA_COUNT 256 /* 256 sets of (R, G, B) data */
268
typedef struct _dac_state_tnc {
269
unsigned long palette_a[DAC_DATA_COUNT]; /* Pipe A palette data */
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unsigned long palette_b[DAC_DATA_COUNT]; /* Pipe B palette data */
271
unsigned char mode; // DAC state register
272
unsigned char index; // DAC index register
273
unsigned char mask; // 0x3C6, Palette Pixel Mask Register
276
/* Structure to store the 3D registers during power management
277
* These are 3D specific registers, but named as D3D because
278
* variabl names cannot start with a number*/
279
typedef struct _d3d_state_tnc {
280
unsigned long cin_ctl;
281
unsigned long bin_scene;
282
unsigned long bmp_buffer;
283
unsigned long bmp_get;
284
unsigned long bmp_put;
287
typedef struct _reg_buffer_tnc {
288
unsigned long *mmio_state;
289
unsigned long *mmio_state_sdvo;
290
//unsigned long mem_mode; /* Reg 0x20CC */
291
//unsigned long instpm; /* Reg 0x20C0 */
292
unsigned long gtt[128*1024]; /* PLB is 128 */
293
unsigned long sgx_phyaddr;
295
vga_state_tnc_t vga_state;
296
dac_state_tnc_t dac_state;
297
d3d_state_tnc_t d3d_state;
299
unsigned long clk_gating_ctl;
302
static reg_platform_context_tnc_t reg_platform_context_tnc = {
312
reg_dispatch_t reg_dispatch_tnc = {
317
®_platform_context_tnc
320
/******************************************************************************
322
*****************************************************************************/
323
static int reg_save_gtt_tnc(igd_context_t *context, unsigned char *mmio,
324
reg_buffer_tnc_t *reg_args);
325
static int reg_restore_gtt_tnc(igd_context_t *context,
326
reg_buffer_tnc_t *reg_args);
329
* This procedure simply waits for the next vertical syncing (vertical retrace)
330
* period. If the display is already in a vertical syncing period, this
331
* procedure exits unlike "util_Wait_VSync_Start()" function that waits for
332
* the beginning of the next vertical sync period.
334
* Note: A timeout is included to prevent an endless loop.
338
* @return FALSE if timed out
339
* @return TRUE otherwise
341
int reg_wait_vsync_tnc(igd_context_t *context)
346
mmio = context->device_context.virt_mmadr;
348
if ((EMGD_READ32(mmio + VP00) & BIT31)) {
352
while ((i++ < 0x100000) && /* Check for timeout */
353
((EMGD_READ8(mmio + STATUS_REG_01) & BIT3) == 0x00)) {
364
* Saves the current VGA register state of the video chipset into the
365
* given state buffer.
367
* This function first saves the 4 plane latches, and then it saves
368
* the SR, GR, AR, CR registers.
370
* @param context the current device context
371
* @param vga_buffer this is where the VGA register state is saved
372
* @param ar_regs AR registers to save
373
* @param cr_regs CR registers to save
374
* @param sr_regs SR registers to save
375
* @param gr_regs GR registers to save
379
static int reg_save_vga_tnc(
380
igd_context_t *context,
381
vga_state_tnc_t *vga_buffer,
382
unsigned char *ar_regs,
383
unsigned char *cr_regs,
384
unsigned char *sr_regs,
385
unsigned char *gr_regs)
390
mmio = context->device_context.virt_mmadr;
392
/* First, save a few registers that will be modified to read the latches.
393
* We need to use GR04 to go through all the latches. Therefore, we must
394
* first save GR04 before continuing. However, GR04 will only behave the
395
* way we want it to if we are not in Odd/Even mode and not in Chain 4
396
* mode. Therefore, we have to make sure GR05 (GFX mode reg),
397
* and SR04 (Mem Mode reg) are set properly.
398
* According to B-spec, we are not supposed to program GR06 via MMIO.
400
READ_VGA(mmio, GR_PORT, GR04, vga_buffer->gr[0x04]);
401
READ_VGA(mmio, SR_PORT, SR04, vga_buffer->sr[0x04]); /* Memory Mode */
402
READ_VGA(mmio, GR_PORT, GR05, vga_buffer->gr[0x05]); /* GFX Mode Reg */
403
READ_VGA(mmio, GR_PORT, GR06, vga_buffer->gr[0x06]); /* Misc Reg */
405
WRITE_VGA(mmio, SR_PORT, SR04, 0x06);
406
WRITE_VGA(mmio, GR_PORT, GR05, 0x00);
407
WRITE_VGA(mmio, GR_PORT, GR06, 0x05);
409
/* Save Memory Latch Data latches */
410
for (i=0; i<PLANE_LATCH_COUNT; i++) {
411
WRITE_VGA(mmio, GR_PORT, GR04, (unsigned char)i);
412
READ_VGA(mmio, CR_PORT, CR22, vga_buffer->plane_latches[i]);
415
/* Restore the modified regs */
416
WRITE_VGA(mmio, GR_PORT, GR06, vga_buffer->gr[0x06]);
417
WRITE_VGA(mmio, GR_PORT, GR05, vga_buffer->gr[0x05]);
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WRITE_VGA(mmio, GR_PORT, GR04, vga_buffer->gr[0x04]);
419
WRITE_VGA(mmio, SR_PORT, SR04, vga_buffer->sr[0x04]);
422
/* Save Feature Controller register. */
423
vga_buffer->fcr = EMGD_READ8(mmio + FEATURE_CONT_REG_READ);
425
/* Save Miscellaneous Output Register. */
426
vga_buffer->msr = EMGD_READ8(mmio + MSR_READ_PORT);
428
/* Save index registers. */
429
vga_buffer->sr_index = EMGD_READ8(mmio + SR_PORT);
430
vga_buffer->cr_index = EMGD_READ8(mmio + CR_PORT);
431
vga_buffer->gr_index = EMGD_READ8(mmio + GR_PORT);
435
* Save the AR index register and last write status. Not sure that
436
* this is really necessary so skip it for now.
438
READ_VGA(mmio, CR_PORT, CR24, isARData); // Next write to AR index reg
441
// Save AR index and last write status
442
vga_buffer->ar_index = EMGD_READ8(mmio + AR_PORT) | isARData;
445
/* Save CRT Controller registers. */
446
for (i=0; cr_regs[i] != 0xff; i++) {
447
READ_VGA(mmio, CR_PORT, cr_regs[i], vga_buffer->cr[i]);
450
/* Save Attribute Controller registers. */
451
for (i=0; ar_regs[i] != 0xff; i++) {
452
reg_wait_vsync_tnc(context);
453
READ_AR(mmio, (unsigned char)i, vga_buffer->ar[i]);
456
/* Save Graphics Controller registers. */
457
for (i=0; gr_regs[i] != 0xff; i++) {
458
READ_VGA(mmio, GR_PORT, gr_regs[i], vga_buffer->gr[i]);
461
/* Save Sequencer registers. */
462
for (i=0; sr_regs[i] != 0xff; i++) {
463
READ_VGA(mmio, SR_PORT, sr_regs[i], vga_buffer->sr[i]);
470
* Restore the VGA Register state from the specifed state buffer.
472
* @param context the current device context
473
* @param vga_buffer this is where the VGA register state is saved
474
* @param ar_regs AR registers to save
475
* @param cr_regs CR registers to save
476
* @param sr_regs SR registers to save
477
* @param gr_regs GR registers to save
481
static int reg_restore_vga_tnc(
482
igd_context_t *context,
483
vga_state_tnc_t *vga_buffer,
484
unsigned char *ar_regs,
485
unsigned char *cr_regs,
486
unsigned char *sr_regs,
487
unsigned char *gr_regs)
491
unsigned long bit_mask;
492
mmio = context->device_context.virt_mmadr;
494
/* Restore the plane latches.
496
* BP: I don't understand what this block is doing and it doesn't
497
* seem necessary. Should check this against the spec and figure
498
* out what it really does.
501
/* Memory Mode Register */
502
WRITE_VGA(mmio, SR_PORT, SR04, 0x06);
503
/* GR05, Graphics Mode Register */
504
WRITE_VGA(mmio, GR_PORT, GR05, 0x00);
505
/* GR06, Micsellaneous Register */
506
WRITE_VGA(mmio, GR_PORT, GR06, 0x05);
507
/* GR08, Bit Mask Register */
508
WRITE_VGA(mmio, GR_PORT, GR08, 0xFF);
510
for (i=0, bit_mask=1; i<PLANE_LATCH_COUNT; i++, bit_mask<<= 1) {
511
/* Set plane select register */
512
WRITE_VGA(mmio, GR_PORT, GR04, i);
513
/* Plane/Map mask register */
514
WRITE_VGA(mmio, SR_PORT, SR02, bit_mask);
517
for (i=0, bit_mask=1; i<PLANE_LATCH_COUNT; i++, bit_mask<<= 1) {
518
/* Plane/Map mask register again?? */
519
WRITE_VGA(mmio, SR_PORT, SR02, bit_mask);
522
/* Restore standard VGA registers.
523
* 2) Sequence registers
526
* 4) Graphics registers
527
* 5) Attribute registers
528
* 6) VGA Feature register
529
* 7) Index restisters
533
WRITE_VGA(mmio, SR_PORT, SR00, 01); /* Do sync reset */
535
for (i=0; sr_regs[i] != 0xff; i++) {
536
WRITE_VGA(mmio, SR_PORT, sr_regs[i], vga_buffer->sr[i]);
540
EMGD_WRITE8(vga_buffer->msr, mmio + MSR_PORT);
541
WRITE_VGA(mmio, SR_PORT, SR00, 0x03); /* Set to normal operation */
544
WRITE_VGA(mmio, CR_PORT, CR11, vga_buffer->cr[0x11] & 0x7F);
545
for (i=0; cr_regs[i] != 0xff; i++) {
546
WRITE_VGA(mmio, CR_PORT, cr_regs[i], vga_buffer->cr[i]);
549
for (i=0; gr_regs[i] != 0xff; i++) {
550
WRITE_VGA(mmio, GR_PORT, gr_regs[i], vga_buffer->gr[i]);
553
for (i=0; ar_regs[i] != 0xff; i++) {
554
WRITE_AR(mmio, ar_regs[i], vga_buffer->ar[i]);
557
EMGD_WRITE8(vga_buffer->fcr, mmio + FEATURE_CONT_REG);
559
/* Restore index registers. Is this necessary? */
560
EMGD_WRITE8(vga_buffer->sr_index, mmio + SR_PORT);
561
EMGD_WRITE8(vga_buffer->cr_index, mmio + CR_PORT);
562
EMGD_WRITE8(vga_buffer->gr_index, mmio + GR_PORT);
565
WRITE_VGA(mmio, CR_PORT, CR11, vga_buffer->cr[0x11] | 0x80);
571
* Saves the DAC registers and lookup table.
575
* @param platform_context
579
static int reg_save_dac_tnc(
580
igd_context_t *context,
581
dac_state_tnc_t *dac_state,
582
reg_platform_context_tnc_t *platform_context)
587
mmio = context->device_context.virt_mmadr;
589
/* Save DACMASK register */
590
dac_state->mask = EMGD_READ8(mmio + DAC_PEL_MASK);
592
/* Save DAC State register */
593
dac_state->mode = EMGD_READ8(mmio + DAC_STATE);
595
/* Save DAC Index register */
596
dac_state->index = EMGD_READ8(mmio + DAC_WRITE_INDEX);
600
* Start from first DAC location
602
EMGD_WRITE8(0, mmio + DAC_WRITE_INDEX);
604
/* Save Pipe A Palette */
605
/* Or if Pipe A is used for VGA */
606
if (((EMGD_READ32(mmio + PIPEA_CONF) & PIPE_ENABLE) &&
607
(EMGD_READ32(mmio + PIPEASRC))) ||
608
((!(EMGD_READ32(mmio + 0x71400) & 0x80000000)) &&
609
(!(EMGD_READ32(mmio + 0x71400) & 0x20000000)))) {
610
for (i=0; i<DAC_DATA_COUNT; i++) {
611
dac_state->palette_a[i] = EMGD_READ32(mmio + i*4 + DPALETTE_A);
615
if (platform_context->pipes == 2) {
616
/* If Pipe B is enabled, save Pipe B Palette */
617
/* Or if Pipe B is used for VGA */
618
if (((EMGD_READ32(mmio + PIPEB_CONF) & PIPE_ENABLE) &&
619
(EMGD_READ32(mmio + PIPEBSRC))) ||
620
((! (EMGD_READ32(mmio + 0x71400) & 0x80000000)) &&
621
((EMGD_READ32(mmio + 0x71400) & 0x20000000)))) {
623
for (i=0; i<DAC_DATA_COUNT; i++) {
624
dac_state->palette_b[i] = EMGD_READ32(mmio + i*4 + DPALETTE_B);
633
* Restore previously saved DAC palette from the specifed state buffer.
637
* @param platform_context
641
static int reg_restore_dac_tnc(
642
igd_context_t *context,
643
dac_state_tnc_t *dac_state,
644
reg_platform_context_tnc_t *platform_context)
650
mmio = context->device_context.virt_mmadr;
652
/* If Pipe A is enabled, restore Palette */
653
/* Or if Pipe A is used for VGA */
654
if (((EMGD_READ32(mmio + PIPEA_CONF) & PIPE_ENABLE) &&
655
(EMGD_READ32(mmio + PIPEASRC))) ||
656
((! (EMGD_READ32(mmio + 0x71400) & 0x80000000)) &&
657
(! (EMGD_READ32(mmio + 0x71400) & 0x20000000)))) {
661
* Start from first DAC location
663
EMGD_WRITE8(0, mmio + DAC_WRITE_INDEX);
665
/* Restore Pipe A Palette */
666
for (i=0; i<DAC_DATA_COUNT; i++) {
667
EMGD_WRITE32(dac_state->palette_a[i], mmio + i*4 + DPALETTE_A);
671
/* If this is a single pipe device. */
672
if (platform_context->pipes == 2) {
673
/* If Pipe B is enabled, restore Palette */
674
/* Or if Pipe B is used for VGA */
675
if (((EMGD_READ32(mmio + PIPEB_CONF) & PIPE_ENABLE) &&
676
(EMGD_READ32(mmio + PIPEBSRC))) ||
677
((! (EMGD_READ32(mmio + 0x71400) & 0x80000000)) &&
678
((EMGD_READ32(mmio + 0x71400) & 0x20000000)))) {
680
for (i=0; i<DAC_DATA_COUNT; i++) {
681
EMGD_WRITE32(dac_state->palette_b[i], mmio + i*4 + DPALETTE_B);
686
/* Restore DACMASK register */
687
EMGD_WRITE8(dac_state->mask, mmio + DAC_PEL_MASK);
689
/* Restore DAC Index register */
690
if (dac_state->mode & 1) { /* Last write was to "write index register" */
691
EMGD_WRITE8(dac_state->index, mmio + DAC_WRITE_INDEX);
692
} else { /* Last index write was to "read index register" */
693
EMGD_WRITE8(dac_state->index - 1, mmio + DAC_READ_INDEX);
695
/* Dummy read to set DACSTATE register and to increment read index to
698
temp = EMGD_READ8(mmio + DAC_DATA_REG);
705
* Initializes memory to store register values
707
* @param context pointer to igd_context
708
* @param flags indicate which register type to save
709
* @param _platform_context
711
* @return pointer to structure which will eventually be saved data defining
713
* @return NULL on failure
715
static reg_buffer_t *reg_alloc_tnc(igd_context_t *context,
717
void *_platform_context)
719
reg_buffer_tnc_t* reg_args;
720
reg_buffer_t *reg_buffer;
722
EMGD_DEBUG("Entry - reg_alloc");
724
reg_buffer = (reg_buffer_t*)OS_ALLOC(sizeof(reg_buffer_t));
725
if (reg_buffer == NULL) {
729
reg_args = (reg_buffer_tnc_t*)OS_ALLOC(sizeof(reg_buffer_tnc_t));
730
if (reg_args == NULL) {
734
reg_buffer->mode_buffer = NULL;
735
reg_buffer->platform_buffer = reg_args;
737
OS_MEMSET(reg_args, 0, sizeof(reg_buffer_tnc_t));
738
reg_buffer->flags = flags;
740
reg_args->mmio_state = (void *)OS_ALLOC(sizeof(mmio_regs_tnc));
741
reg_args->mmio_state_sdvo = (void *)OS_ALLOC(sizeof(mmio_regs_sdvo_tnc));
743
if (!reg_args->mmio_state) {
744
EMGD_DEBUG("Failed Allocating mmio memory");
745
/* free the "parent" memory*/
750
if (!reg_args->mmio_state_sdvo) {
751
EMGD_DEBUG("Failed Allocating sdvo mmio memory");
752
/*Free other dependaant memory*/
753
OS_FREE(reg_args->mmio_state);
762
* This function calculates the size of memory to store data
764
* @param context void pointer to main igd context
765
* @param reg_buffer pointer to register structure returned from a reg_alloc
766
* @param _platform_context
770
static void reg_free_tnc(igd_context_t *context,
771
reg_buffer_t *reg_buffer,
772
void *_platform_context)
774
reg_buffer_tnc_t* reg_args;
776
EMGD_DEBUG("Entry - reg_free");
779
reg_args = (reg_buffer_tnc_t*)reg_buffer->platform_buffer;
782
if (NULL != reg_args->mmio_state) {
783
OS_FREE(reg_args->mmio_state);
786
if (NULL != reg_args->mmio_state_sdvo) {
787
OS_FREE(reg_args->mmio_state_sdvo);
790
if (NULL != reg_args->vga_mem) {
791
OS_FREE(reg_args->vga_mem);
794
if (NULL != reg_args->rb_state) {
795
OS_FREE(reg_args->rb_state);
806
* This functions save the regs
808
* @param context void pointer to main igd context
809
* @param reg_buffer pointer to register structure returned from a reg_alloc
810
* @param _platform_context
812
* @return 0 on success
813
* @return -1 on failure
815
static int reg_save_tnc(igd_context_t *context,
816
reg_buffer_t *reg_buffer,
817
void *_platform_context)
819
reg_buffer_tnc_t *reg_args;
820
unsigned long *buffer, *buffer_sdvo;
821
reg_platform_context_tnc_t *platform_context =
822
(reg_platform_context_tnc_t *)_platform_context;
824
unsigned char *mmio, *mmio_sdvo;
828
if (reg_buffer == NULL) {
832
/* Before save need to idle the ring buffer */
833
context->dispatch.idle((igd_driver_h)context);
835
reg_args = (reg_buffer_tnc_t *)reg_buffer->platform_buffer;
836
if (reg_args == NULL) {
840
mmio = context->device_context.virt_mmadr;
841
mmio_sdvo = context->device_context.virt_mmadr_sdvo;
844
/* Save vga registers */
845
if (reg_buffer->flags & IGD_REG_SAVE_VGA) {
846
EMGD_DEBUG("Saving VGA registers");
847
reg_save_vga_tnc(context, ®_args->vga_state,
848
platform_context->ar, platform_context->cr, platform_context->sr,
849
platform_context->gr);
852
/* Save VGA memory */
854
if (reg_buffer->flags & IGD_REG_SAVE_VGA_MEM) {
855
EMGD_DEBUG("Saving VGA memory");
856
if (!reg_args->vga_mem) {
857
reg_args->vga_mem = (void *)OS_ALLOC_LARGE(64 * 1024);
858
if (reg_args->vga_mem != NULL) {
859
OS_MEMCPY(reg_args->vga_mem,
860
(void *)context->device_context.virt_fb_adr, 64*1024);
862
EMGD_ERROR("Unable to allocate memory for vga memory");
865
OS_MEMCPY(reg_args->vga_mem,
866
(void *)context->device_context.virt_fb_adr, 64*1024);
871
/* Save mmio registers */
872
if (reg_buffer->flags & IGD_REG_SAVE_MMIO) {
873
EMGD_DEBUG("Saving MMIO registers");
874
buffer = reg_args->mmio_state;
875
for (i=0; platform_context->mmio_regs[i] != 0xffffffff; i++) {
876
*buffer++ = EMGD_READ32(mmio + platform_context->mmio_regs[i]);
879
buffer_sdvo = reg_args->mmio_state_sdvo;
880
for (i=0; platform_context->mmio_regs_sdvo[i] != 0xffffffff; i++) {
881
*buffer_sdvo++ = EMGD_READ32(mmio_sdvo + platform_context->mmio_regs_sdvo[i]);
884
reg_save_gtt_tnc(context, mmio, reg_args);
887
/* Save DAC registers */
888
if (reg_buffer->flags & IGD_REG_SAVE_DAC) {
889
EMGD_DEBUG("Saving DAC registers");
890
reg_save_dac_tnc(context, ®_args->dac_state, platform_context);
893
/* Save Mode state */
894
if(reg_buffer->flags & IGD_REG_SAVE_MODE) {
895
EMGD_DEBUG("Saving mode state");
896
/* At driver initialization though mode_save is requested, mode isn't
897
* initialized. So skip the mode_save if dispatch function isn't
898
* available. In this case, mode_save() will be done as part of
900
if (context->mod_dispatch.mode_save && !reg_buffer->mode_buffer) {
901
context->mod_dispatch.mode_save(context,
902
®_buffer->mode_buffer,
905
EMGD_DEBUG("mode_save() is skipped as mode_init() isn't done.");
909
/* Save the SGX clock gating settings */
910
reg_args->clk_gating_ctl = EMGD_READ32(mmio + PSB_CR_CLKGATECTL);
916
* This function restores the regs states
918
* @param context void pointer to main igd context
919
* @param reg_buffer pointer to register structure returned from a reg_alloc
920
* @param _platform_context
922
* @return 0 on success
923
* @return -1 on failure
925
int reg_restore_tnc(igd_context_t *context,
926
reg_buffer_t *reg_buffer,
927
void *_platform_context)
929
reg_buffer_tnc_t* reg_args;
930
reg_platform_context_tnc_t *platform_context =
931
(reg_platform_context_tnc_t *)_platform_context;
932
unsigned char *mmio, *mmio_sdvo;
933
unsigned long *buffer, *buffer_sdvo;
936
EMGD_DEBUG("Entry - reg_restore");
938
if (reg_buffer == NULL) {
942
reg_args = (reg_buffer_tnc_t *)reg_buffer->platform_buffer;
943
if (reg_args == NULL) {
947
EMGD_DEBUG(" flags = 0x%lx", reg_buffer->flags);
949
mmio = context->device_context.virt_mmadr;
950
mmio_sdvo = context->device_context.virt_mmadr_sdvo;
952
/* Restore Mode state */
953
if (reg_buffer->flags & IGD_REG_SAVE_MODE) {
954
if (reg_buffer->mode_buffer) {
955
context->mod_dispatch.mode_restore(context,
956
®_buffer->mode_buffer,
959
EMGD_DEBUG("mode_restore() already happened in mode_shutdown().");
963
/* Restore MMIO registers */
964
if (reg_buffer->flags & IGD_REG_SAVE_MMIO) {
965
EMGD_DEBUG("Restoring MMIO registers");
966
buffer = reg_args->mmio_state;
967
for (i=0; platform_context->mmio_regs[i] != 0xffffffff; i++) {
968
if (platform_context->mmio_regs[i] == MI_ARB_STATE) {
969
EMGD_DEBUG("Handle special masked register case");
970
EMGD_WRITE32(0x04100000 | *buffer++, mmio +
971
platform_context->mmio_regs[i]);
972
} else if (platform_context->mmio_regs[i] == DPLLACNTR ||
973
platform_context->mmio_regs[i] == DPLLBCNTR) {
975
EMGD_DEBUG("Handle special DPLL settling");
976
EMGD_WRITE32(*buffer++,
977
mmio + platform_context->mmio_regs[i]);
980
EMGD_WRITE32(*buffer++, mmio + platform_context->mmio_regs[i]);
983
// reg_restore_gtt_tnc(context, reg_args);
985
buffer_sdvo = reg_args->mmio_state_sdvo;
986
for (i=0; platform_context->mmio_regs_sdvo[i] != 0xffffffff; i++) {
987
if (platform_context->mmio_regs_sdvo[i] == MI_ARB_STATE) {
988
EMGD_DEBUG("Handle special masked register case");
989
EMGD_WRITE32(0x04100000 | *buffer_sdvo++, mmio_sdvo +
990
platform_context->mmio_regs_sdvo[i]);
991
} else if (platform_context->mmio_regs_sdvo[i] == DPLLACNTR ||
992
platform_context->mmio_regs_sdvo[i] == DPLLBCNTR) {
994
EMGD_DEBUG("Handle special DPLL settling");
995
EMGD_WRITE32(*buffer_sdvo++,
996
mmio_sdvo + platform_context->mmio_regs_sdvo[i]);
999
EMGD_WRITE32(*buffer_sdvo++, mmio_sdvo + platform_context->mmio_regs_sdvo[i]);
1002
reg_restore_gtt_tnc(context, reg_args);
1006
/* Restore VGA memory */
1007
if (reg_buffer->flags & IGD_REG_SAVE_VGA_MEM) {
1008
if (reg_args->vga_mem) {
1009
OS_MEMCPY((void *)context->device_context.virt_fb_adr,
1010
reg_args->vga_mem, 64*1024);
1012
EMGD_ERROR("Trying to restore NULL VGA memory");
1017
/* Restore DAC registers */
1018
if (reg_buffer->flags & IGD_REG_SAVE_DAC) {
1019
reg_restore_dac_tnc(context, ®_args->dac_state, platform_context);
1022
/* Restore VGA registers */
1023
if (reg_buffer->flags & IGD_REG_SAVE_VGA) {
1024
reg_restore_vga_tnc(context, ®_args->vga_state,
1025
platform_context->ar, platform_context->cr, platform_context->sr,
1026
platform_context->gr);
1029
/* Restore the SGX clock gating settings */
1030
EMGD_WRITE32(reg_args->clk_gating_ctl, mmio + PSB_CR_CLKGATECTL);
1036
* This function saves the GTT table entries into a buffer so that the GTT
1037
* can be restored later.
1039
* @param context needs this to get the GTT table size and to get the
1040
* virtual address to the GTT table
1041
* @param mmio virtual address to MMIO
1042
* @param reg_args a pre-allocated context where GTT entries are saved
1044
* @return 0 on success
1045
* @return -1 on failure
1047
static int reg_save_gtt_tnc(igd_context_t *context, unsigned char *mmio,
1048
reg_buffer_tnc_t *reg_args)
1052
/* Read the GTT entries from GTT ADR and save it in the array. */
1053
for (i = 0; i < (context->device_context.gatt_pages); i++) {
1054
reg_args->gtt[i] = EMGD_READ32(
1055
context->device_context.virt_gttadr + i);
1058
/* Save the address of the SGX MMU */
1059
reg_args->sgx_phyaddr = EMGD_READ32(mmio + PSB_CR_BIF_DIR_LIST_BASE0);
1065
* This function restores the GTT table entries.
1067
* @param context the context contains the GTT size and address
1068
* @param reg_args this has the saved GTT entries
1070
* @return 0 on success
1071
* @return -1 on failure
1073
static int reg_restore_gtt_tnc(igd_context_t *context,
1074
reg_buffer_tnc_t *reg_args)
1077
unsigned char *mmio;
1078
unsigned long sgx_mmu;
1080
/* If the first element is 0, then nothing was saved */
1081
if (0 == reg_args->gtt[0]) {
1085
/* Restore the GTT tablep */
1086
for (i=0; i < context->device_context.gatt_pages; i++) {
1087
EMGD_WRITE32(reg_args->gtt[i],
1088
context->device_context.virt_gttadr + i);
1091
mmio = context->device_context.virt_mmadr;
1094
* FIXME: The following code restore the SGX MMU. This
1095
* is probably not necessary and may be incorrect.
1097
/* Invalidate directory cache */
1098
sgx_mmu = EMGD_READ32(mmio + PSB_CR_BIF_CTRL);
1100
EMGD_WRITE32(sgx_mmu, mmio + PSB_CR_BIF_CTRL);
1101
EMGD_READ32(mmio + PSB_CR_BIF_CTRL);
1103
EMGD_WRITE32(reg_args->sgx_phyaddr, mmio + PSB_CR_BIF_DIR_LIST_BASE0);
1104
EMGD_READ32(mmio + PSB_CR_BIF_DIR_LIST_BASE0);
1106
/* Turn on host access to aperture via the MMU */
1107
sgx_mmu = EMGD_READ32(mmio + PSB_CR_BIF_CTRL);
1108
sgx_mmu &= 0xFFFF0000;
1109
EMGD_WRITE32(sgx_mmu, mmio + PSB_CR_BIF_CTRL);
1110
EMGD_READ32(mmio + PSB_CR_BIF_CTRL);
added
removed
emgd-dkms-1.5.15.3082/emgd/state/reg/tnc/reg_tnc.c
