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*-----------------------------------------------------------------------------
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* Filename: msvdx_init.c
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*-----------------------------------------------------------------------------
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* Copyright © 2002-2010, Intel Corporation.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*-----------------------------------------------------------------------------
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* Initialize the MSVDX video engine. This loads the MTX firmware and
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* starts a MTX thread running the firmware.
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* The host communicates with the firmware via messages. The following
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* messages are supported:
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* CMD_COMPLETED <- MTX
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* CMD_COMPLTED_BATCH <- MTX
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* DEBLOCK_REQUIRED <- MTX
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* TEST_RESPONSE <- MTX
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*-----------------------------------------------------------------------------
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#include <igd_errno.h>
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#include <plb/context.h>
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#include <drm_emgd_private.h>
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struct drm_device *gpDrmDevice = NULL;
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static int init_msvdx_first_time = 1;
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extern void send_to_mtx(igd_context_t *context, unsigned long *init_msg);
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extern int process_mtx_messages(igd_context_t *context,
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unsigned long *mtx_msgs, unsigned long mtx_msg_cnt,
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extern void populate_fence_id(igd_context_t *context, unsigned long *mtx_msgs,
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unsigned long mtx_msg_cnt);
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extern int msvdx_dequeue_send(igd_context_t *context);
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extern int alloc_ramdec_region(unsigned long *base_addr0, unsigned long *base_addr1,
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unsigned long size0, unsigned long size1);
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static int poll_mtx_irq(igd_context_t *context);
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static int reg_ready_psb(igd_context_t *context, unsigned long reg,
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unsigned long mask, unsigned long value);
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static int context_count = 0;
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void msvdx_reset_plb(igd_context_t *context);
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static msvdx_fw_t *priv_fw = NULL;
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extern unsigned long jiffies_at_last_dequeue;
90
int msvdx_query_plb(igd_context_t *context,
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unsigned long *status)
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platform_context_plb_t *platform;
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platform = (platform_context_plb_t *)context->platform_context;
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*status |= VIDEO_STATE_FW_LOADED;
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if(!platform->rendec_base0 || !platform->rendec_base1) {
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*status |= VIDEO_STATE_RENDEC_FREED;
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int msvdx_pre_init_plb(struct drm_device *dev)
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int msvdx_init_plb(unsigned long base0, unsigned long base1,
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void *msvdx_fw, unsigned long msvdx_fw_size)
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drm_emgd_private *priv;
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igd_context_t *context;
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unsigned long ram_bank;
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unsigned long bank_size;
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unsigned long current_bank;
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unsigned long address;
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unsigned long acc_control;
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unsigned long base_addr0, base_addr1, size0, size1;
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unsigned long ram_id;
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unsigned long fw_size;
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unsigned long *fw_data;
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msvdx_fw_t *fw = NULL;
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platform_context_plb_t *platform = NULL;
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if (!priv_fw && msvdx_fw) {
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fw = (msvdx_fw_t *) msvdx_fw;
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priv_fw = kzalloc(sizeof(msvdx_fw_t), GFP_KERNEL);
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priv_fw->fw_text_size = fw->fw_text_size;
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priv_fw->fw_data_size = fw->fw_data_size;
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priv_fw->fw_version_size = fw->fw_version_size;
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priv_fw->fw_data_location = fw->fw_data_location;
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fw_size = sizeof(unsigned long) * fw->fw_text_size;
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priv_fw->fw_text = kmalloc(fw_size, GFP_KERNEL);
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memcpy(priv_fw->fw_text, (void *) ((unsigned long) msvdx_fw) +
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((unsigned long) fw->fw_text), fw_size);
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fw_size = sizeof(unsigned long) * fw->fw_data_size;
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priv_fw->fw_data = kmalloc(fw_size, GFP_KERNEL);
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memcpy(priv_fw->fw_data, (void *) ((unsigned long) msvdx_fw) +
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((unsigned long) fw->fw_data), fw_size);
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priv_fw->fw_version = kzalloc(priv_fw->fw_version_size, GFP_KERNEL);
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strcpy(priv_fw->fw_version, (char *) (((unsigned long) msvdx_fw) +
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((unsigned long) fw->fw_version)));
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} else if (!priv_fw) {
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printk(KERN_INFO "Kernel firmware is not loaded");
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priv = gpDrmDevice->dev_private;
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context = priv->context;
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mmio = context->device_context.virt_mmadr;
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//init_msvdx_first_time = 1;
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/* Reset MSVDX engine */
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EMGD_WRITE32(0x00000100, mmio + PSB_MSVDX_CONTROL);
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reg_ready_psb(context, PSB_MSVDX_CONTROL, 0x00000100, 0);
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* Make sure the clock is on.
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* Clock enable bits are 0 - 6, with each bit controlling one of the
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* clocks. For this, make sure all the clocks are enabled.
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EMGD_WRITE32(PSB_CLK_ENABLE_ALL, mmio + PSB_MSVDX_MAN_CLK_ENABLE);
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/* Set default MMU PTD to the same value used by the SGX */
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ctrl = EMGD_READ32(mmio + PSB_CR_BIF_DIR_LIST_BASE1);
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address = EMGD_READ32(mmio + PSB_CR_BIF_DIR_LIST_BASE1);
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EMGD_WRITE32(address, mmio + PSB_MSVDX_MMU_DIR_LIST_BASE0);
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EMGD_WRITE32(address, mmio + PSB_MSVDX_MMU_DIR_LIST_BASE1);
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EMGD_WRITE32(address, mmio + PSB_MSVDX_MMU_DIR_LIST_BASE2);
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EMGD_WRITE32(address, mmio + PSB_MSVDX_MMU_DIR_LIST_BASE3);
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* MMU TTE threshold = 12
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EMGD_WRITE32(0xc070000c, mmio + PSB_MSVDX_MMU_CONTROL1);
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/* Flush the directory cache */
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ctrl = EMGD_READ32(mmio + PSB_MSVDX_MMU_CONTROL0) | 0x0C; /* Flush */
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EMGD_WRITE32(ctrl, mmio + PSB_MSVDX_MMU_CONTROL0);
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/* Enable MMU by removing all bypass bits */
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EMGD_WRITE32(0, mmio + PSB_MSVDX_MMU_CONTROL0);
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/* Set up the RENDEC.
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* The RENDEC requires two blocks of virtual address space so those
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* must be allocated and then the RENDEC is initialized using those
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* bit 3 1 - search MTX_to_MTX header
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* bit 2 1 - skip next slice
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* bit 1 1 - flush remaining bit stream
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* bit 0 1 - initialize RENDEC
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* bit 24: 1 - enables data to be transferred through ext. memory
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* bit 19:18 WR burst size (0 = 32 bytes, 1 = 64 bytes, 2 = 128 bytes)
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* bit 17:16 RD burst size (0 = 32 bytes, 1 = 64 bytes, 2 = 128 bytes)
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* bit 7: 0 start size (zero)
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size0 = RENDEC_A_SIZE;
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size1 = RENDEC_B_SIZE;
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* These allocations need to be undone when shutting down. Where
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* should they be saved?
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if (init_msvdx_first_time) {
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//printk(KERN_INFO "get the base_addr=%lx, base_addr1=%lx\n", base_addr0,base_addr1);
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/* Save the offsets so it can be freed and restored later */
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platform = (platform_context_plb_t *)context->platform_context;
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platform->rendec_base0 = base_addr0;
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platform->rendec_base1 = base_addr1;
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init_msvdx_first_time = 0;
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INIT_LIST_HEAD(&platform->msvdx_queue);
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spin_lock_init(&platform->msvdx_lock);
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/* restore offsets. */
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platform = (platform_context_plb_t *)context->platform_context;
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base_addr0 = platform->rendec_base0;
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base_addr1 = platform->rendec_base1;
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/* Init link list to fix HSD202831 */
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INIT_LIST_HEAD(&platform->msvdx_queue);
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platform->msvdx_busy = 0;
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EMGD_WRITE32(base_addr0, mmio + PSB_MSVDX_RENDEC_BASE_ADDR0);
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EMGD_WRITE32(base_addr1, mmio + PSB_MSVDX_RENDEC_BASE_ADDR1);
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EMGD_WRITE32((((size1 / 4096) << 16) | (size0 / 4096)),
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mmio + PSB_MSVDX_RENDEC_BUFFER_SIZE);
273
* Burst size R = 4 words
274
* Burst size W = 4 words
275
* External memory enabled
280
EMGD_WRITE32(0x01050000, mmio + PSB_MSVDX_RENDEC_CONTROL1);
282
EMGD_WRITE32(0x00101010, mmio + PSB_MSVDX_RENDEC_CONTEXT0);
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EMGD_WRITE32(0x00101010, mmio + PSB_MSVDX_RENDEC_CONTEXT1);
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EMGD_WRITE32(0x00101010, mmio + PSB_MSVDX_RENDEC_CONTEXT2);
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EMGD_WRITE32(0x00101010, mmio + PSB_MSVDX_RENDEC_CONTEXT3);
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EMGD_WRITE32(0x00101010, mmio + PSB_MSVDX_RENDEC_CONTEXT4);
287
EMGD_WRITE32(0x00101010, mmio + PSB_MSVDX_RENDEC_CONTEXT5);
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EMGD_WRITE32(0x00000001, mmio + PSB_MSVDX_RENDEC_CONTROL0);
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/* Start Firmware Load process */
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EMGD_WRITE32(0x00000001, mmio + PSB_MSVDX_MTX_SOFT_RESET);
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/* Reset the counter that looks for MSVDX getting into a bad state */
298
jiffies_at_last_dequeue = 0;
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* Should this check the core revision and only do this if it is
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* a specific version or range of versions?
304
* Stepping prior to D0, need to set COMMS_OFFSET_FLAGS to 0
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* Stepping D0 should set MSVDX_DEVICE_NODE_FLAGS_DEFAULT_D0 (0x222)
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* Stepping D1 should set MSVDX_DEVICE_NODE_FLAGS_DEFAULT_D1 (0x220)
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/* If POULSBO_D1 or later use MSVDX_DEVICE_NODE_FLAGS_MMU_HW_INVALIDATION */
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EMGD_WRITE32(MSVDX_DEVICE_NODE_FLAGS_DEFAULT,
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mmio + PSB_MSVDX_COMMS_OFFSET_FLAGS);
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/* Else EMGD_WRITE32(0x00, mmio + PSB_MSVDX_COMMS_OFFSET_FLAGS); */
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/* Initialize communication control */
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EMGD_WRITE32(0x00, mmio + PSB_MSVDX_COMMS_MSG_COUNTER);
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EMGD_WRITE32(0x00, mmio + PSB_MSVDX_COMMS_SIGNATURE);
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EMGD_WRITE32(0x00, mmio + PSB_MSVDX_COMMS_TO_HOST_RD_INDEX);
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EMGD_WRITE32(0x00, mmio + PSB_MSVDX_COMMS_TO_HOST_WRT_INDEX);
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EMGD_WRITE32(0x00, mmio + PSB_MSVDX_COMMS_TO_MTX_RD_INDEX);
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EMGD_WRITE32(0x00, mmio + PSB_MSVDX_COMMS_TO_MTX_WRT_INDEX);
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EMGD_WRITE32(0x00, mmio + PSB_MSVDX_COMMS_FW_STATUS);
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* Get the ram bank size
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* The banks size seems to be a 4 bit value in the MTX debug register.
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* Where this is documented other than the UMG code is not clear.
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ram_bank = EMGD_READ32(mmio + PSB_MSVDX_MTX_RAM_BANK);
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bank_size = (ram_bank & 0x000f0000) >> 16;
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bank_size = (1 << (bank_size + 2));
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/* Firmware version? */
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printk(KERN_INFO "Firmware version is %s\n", priv_fw->fw_version);
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/* Save RAM access control register */
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acc_control = EMGD_READ32(mmio + PSB_MSVDX_MTX_RAM_ACCESS_CONTROL);
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/* Loop writing text/code to core memory */
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address = PC_START_ADDRESS - MTX_CODE_BASE;
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fw_data = priv_fw->fw_text;
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fw_size = priv_fw->fw_text_size;
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for (i = 0; i < fw_size; i++) {
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/* Wait for MCMSTAT to become be idle 1 */
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if (reg_ready_psb(context, PSB_MSVDX_MTX_RAM_ACCESS_STATUS,
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0xffffffff, 0x00000001) == 0) {
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ram_id = MTX_CORE_CODE_MEM + (address / bank_size);
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if (ram_id != current_bank) {
352
* bits 20:27 - ram bank (CODE_BASE | DATA_BASE)
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* bits 2:19 - address
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* bit 1 - enable auto increment addressing mode
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ctrl = (ram_id << 20) | (((address >> 2) & 0x000ffffc) << 2) |
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EMGD_WRITE32(ctrl, mmio + PSB_MSVDX_MTX_RAM_ACCESS_CONTROL);
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current_bank = ram_id;
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/* Wait for MCMSTAT to become be idle 1 */
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reg_ready_psb(context, PSB_MSVDX_MTX_RAM_ACCESS_STATUS,
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0xffffffff, 0x00000001);
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EMGD_WRITE32(fw_data[i],
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mmio + PSB_MSVDX_MTX_RAM_ACCESS_DATA_TRANSFER);
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printk(KERN_ERR "Timeout waiting for MCMSTAT to be idle\n");
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/* verify firmware upload. */
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address = PC_START_ADDRESS - MTX_CODE_BASE;
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for (i = 0; i < fw_size; i++) {
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if (reg_ready_psb(context, PSB_MSVDX_MTX_RAM_ACCESS_STATUS,
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0xffffffff, 0x00000001) == 0) {
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ram_id = MTX_CORE_CODE_MEM + (address / bank_size);
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if (ram_id != current_bank) {
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* bits 20:27 - ram bank (CODE_BASE | DATA_BASE)
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* bits 2:19 - address
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* bit 1 - enable auto increment addressing mode
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ctrl = (ram_id << 20) | (((address >> 2) & 0x000ffffc) << 2) |
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EMGD_WRITE32(ctrl, mmio + PSB_MSVDX_MTX_RAM_ACCESS_CONTROL);
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current_bank = ram_id;
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reg_ready_psb(context, PSB_MSVDX_MTX_RAM_ACCESS_STATUS,
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0xffffffff, 0x00000001);
397
if (EMGD_READ32(mmio + PSB_MSVDX_MTX_RAM_ACCESS_DATA_TRANSFER) !=
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printk(KERN_ERR "Verify Error at index %ld\n", i);
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printk(KERN_ERR "Timeout waiting for MCMSTAT to be idle while verifying\n");
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fw_data = priv_fw->fw_data;
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fw_size = priv_fw->fw_data_size;
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/* Loop writing data to core memory */
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address = priv_fw->fw_data_location - MTX_DATA_BASE;
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for (i = 0; i < fw_size; i++) {
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if (reg_ready_psb(context, PSB_MSVDX_MTX_RAM_ACCESS_STATUS,
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0xffffffff, 0x00000001) == 0) {
416
ram_id = MTX_CORE_DATA_MEM + (address / bank_size);
417
if (ram_id != current_bank) {
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* bits 20:27 - ram bank (CODE_BASE | DATA_BASE)
420
* bits 2:19 - address
421
* bit 1 - enable auto increment addressing mode
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ctrl = (ram_id << 20) | (((address >> 2) & 0x000ffffc) << 2) |
425
EMGD_WRITE32(ctrl, mmio + PSB_MSVDX_MTX_RAM_ACCESS_CONTROL);
426
current_bank = ram_id;
427
reg_ready_psb(context, PSB_MSVDX_MTX_RAM_ACCESS_STATUS,
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0xffffffff, 0x00000001);
432
EMGD_WRITE32(fw_data[i],
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mmio + PSB_MSVDX_MTX_RAM_ACCESS_DATA_TRANSFER);
435
printk(KERN_ERR "Timeout waiting for MCMSTAT to be idle - data segment\n");
439
/* Restore the RAM access control register */
440
EMGD_WRITE32(acc_control, mmio + PSB_MSVDX_MTX_RAM_ACCESS_CONTROL);
442
/* Start the firmware thread running */
443
EMGD_WRITE32(PC_START_ADDRESS, mmio + PSB_MSVDX_MTX_REGISTER_READ_WRITE_DATA);
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EMGD_WRITE32(MTX_PC, mmio + PSB_MSVDX_MTX_REGISTER_READ_WRITE_REQUEST);
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reg_ready_psb(context, PSB_MSVDX_MTX_REGISTER_READ_WRITE_REQUEST,
446
0x80000000, 0x80000000);
449
printk(KERN_INFO "Enabling MTX 0x%x\n", EMGD_READ32(mmio + PSB_MSVDX_MTX_ENABLE));
450
EMGD_WRITE32(MSVDX_MTX_ENABLE_MTX_ENABLE_MASK, mmio + PSB_MSVDX_MTX_ENABLE);
451
printk(KERN_INFO "Enabled MTX 0x%x\n", EMGD_READ32(mmio + PSB_MSVDX_MTX_ENABLE));
454
* Wait for signature value to be written.
456
* This is how the firmware thread notifies us that it is running.
458
if (reg_ready_psb(context, PSB_MSVDX_COMMS_SIGNATURE, 0xffffffff,
460
/* Error initializing firmware.... */
461
EMGD_DEBUG("Error, no MSVDX COMMS Signature");
462
return 0; /* FIXME: return an error code */
464
printk(KERN_INFO "MSVDX COMMS Signature OK\n");
466
/* Locate message buffers */
467
platform->mtx_buf_size = EMGD_READ32(mmio+PSB_MSVDX_COMMS_TO_MTX_BUF_SIZE) & 0xFFFF;
468
platform->host_buf_size = EMGD_READ32(mmio+PSB_MSVDX_COMMS_TO_HOST_BUF_SIZE) & 0xFFFF;
469
platform->mtx_buf_offset = MSVDX_BASE + (EMGD_READ32(mmio+PSB_MSVDX_COMMS_TO_MTX_BUF_SIZE) >> 16) + 0x2000;
470
platform->host_buf_offset = MSVDX_BASE + (EMGD_READ32(mmio+PSB_MSVDX_COMMS_TO_HOST_BUF_SIZE) >> 16) + 0x2000;
472
platform->sequence = 1;
473
platform->mtx_submitted = 0;
475
/* Send initialization message to firmware, newer versions don't */
477
unsigned long init_msg[2];
479
init_msg[0] = 8 | (0x80 << 8);
481
/* physical address of the PD shared by SGX/MSVDX */
482
init_msg[1] = EMGD_READ32(mmio + 0x40c84);
484
send_to_mtx(context, init_msg);
486
/* Check response from MTX firmware */
487
poll_mtx_irq(context);
490
/* Clear the firmware buffer, this is mostly to make debugging easier */
494
for (i = 0; i < platform->mtx_buf_size; i++) {
495
EMGD_WRITE32(0, mmio + platform->mtx_buf_offset + (i <<2));
497
for (i = 0; i < platform->host_buf_size; i++) {
498
EMGD_WRITE32(0, mmio + platform->host_buf_offset + (i <<2));
503
/* Enable minimal clocks */
504
EMGD_WRITE32(PSB_CLK_ENABLE_MIN, mmio + PSB_MSVDX_MAN_CLK_ENABLE);
506
/* Enable MTX interrupts to host */
507
EMGD_WRITE32(1<<14, mmio + PSB_MSVDX_HOST_INTERRUPT_ENABLE);
512
return 0; /* Successfully initialized the MTX firmware */
516
int msvdx_uninit_plb(igd_context_t *context)
521
msvdx_reset_plb(context);
528
int msvdx_close_context(igd_context_t *context)
543
int msvdx_create_context(igd_context_t *context)
553
int process_video_decode_plb(igd_context_t *context, unsigned long offset, void *virt_addr, unsigned long *fence_id)
555
unsigned long *mtx_buf;
556
unsigned long *mtx_msgs;
557
unsigned long mtx_offset;
558
unsigned long mtx_msg_cnt;
559
unsigned long irq_flags;
561
platform_context_plb_t *platform;
566
platform = (platform_context_plb_t *)context->platform_context;
568
mtx_buf = (unsigned long *) virt_addr;
569
mtx_offset = mtx_buf[0];
570
mtx_msg_cnt = mtx_buf[1];
572
// printk(KERN_INFO "process_video_decode_plb where buf=%lx, offset=%lx, cnt=%lx\n",
573
// mtx_buf, offset, mtx_msg_cnt);
574
if (mtx_msg_cnt > 0x20) {
575
printk(KERN_ERR "Message count too big at %ld\n", mtx_msg_cnt);
579
mtx_msgs = mtx_buf + (mtx_offset / sizeof (unsigned long));
580
if (mtx_msg_cnt > 0) {
581
//if ((mtx_buf[0] != 0x8) || (mtx_buf[2] != 0x8504)) {
583
spin_lock_irqsave(&platform->msvdx_lock, irq_flags);
585
if (!platform->msvdx_busy) {
587
platform->msvdx_busy = 1;
588
spin_unlock_irqrestore(&platform->msvdx_lock, irq_flags);
591
if (platform->msvdx_needs_reset) {
592
msvdx_reset_plb(context);
593
msvdx_init_plb(0, 0, NULL, 0);
594
jiffies_at_last_dequeue = 0;
596
// Send message buffer to MSVDX Firmware
598
populate_fence_id(context, mtx_msgs, mtx_msg_cnt);
599
ret = process_mtx_messages(context, mtx_msgs, mtx_msg_cnt, platform->msvdx_fence);
606
struct msvdx_cmd_queue *msvdx_cmd;
608
spin_unlock_irqrestore(&platform->msvdx_lock, irq_flags);
610
msvdx_cmd = kzalloc(sizeof(struct msvdx_cmd_queue), GFP_KERNEL);
611
if (msvdx_cmd == NULL) {
612
printk(KERN_ERR "MSVDXQUE: Out of memory\n");
616
populate_fence_id(context, mtx_msgs, mtx_msg_cnt);
617
msvdx_cmd->cmd = mtx_msgs;
618
msvdx_cmd->cmd_size = mtx_msg_cnt;
619
/* If more than 1000 msec (1 second or 1000 jiffies) passes since
620
* the last time a video cmd has been decoded, MSVDX may be hung
621
* and needing to be reset.
623
if ((jiffies_at_last_dequeue != 0) &&
624
((jiffies - jiffies_at_last_dequeue) > 1000)) {
625
printk(KERN_ERR "Video decode hardware appears to be hung; "
627
platform->msvdx_needs_reset = 1;
629
if (platform->msvdx_needs_reset) {
630
msvdx_reset_plb(context);
631
msvdx_init_plb(0, 0, NULL, 0);
632
platform->msvdx_busy = 0;
633
jiffies_at_last_dequeue = 0;
636
spin_lock_irqsave(&platform->msvdx_lock, irq_flags);
637
list_add_tail(&msvdx_cmd->head, &platform->msvdx_queue);
638
if (!platform->msvdx_busy) {
639
platform->msvdx_busy = 1;
640
msvdx_dequeue_send(context);
643
spin_unlock_irqrestore(&platform->msvdx_lock, irq_flags);
646
*fence_id = platform->msvdx_fence;
648
/* return the fence id even there is no messages to process.
649
* Used this for context id.
651
*fence_id = platform->msvdx_fence;
657
int msvdx_get_fence_id(igd_context_t *context, unsigned long *fence_id)
660
platform_context_plb_t *platform;
662
platform = (platform_context_plb_t *)context->platform_context;
664
*fence_id = platform->mtx_completed;
669
int msvdx_flush_tlb(igd_context_t *context)
671
unsigned char *mmio = context->device_context.virt_mmadr;
672
unsigned long msvdx_mmu;
673
msvdx_mmu = EMGD_READ32(mmio + PSB_MSVDX_MMU_CONTROL0);
674
msvdx_mmu &= 0xFFFFFFF0;
675
msvdx_mmu |= 0x0C; /* MMU_INVALDC + MMU_FLUSH */
676
EMGD_WRITE32(msvdx_mmu, mmio + PSB_MSVDX_MMU_CONTROL0);
678
msvdx_mmu = EMGD_READ32(mmio + PSB_MSVDX_MMU_CONTROL0);
679
msvdx_mmu &= 0xFFFFFF00;
680
EMGD_WRITE32(msvdx_mmu, mmio + PSB_MSVDX_MMU_CONTROL0);
681
EMGD_READ32(mmio + PSB_MSVDX_MMU_CONTROL0);
689
* Resets the MSVDX engine via the soft reset control.
691
* This function is exported.
693
void msvdx_reset_plb(igd_context_t *context)
695
unsigned char *mmio = context->device_context.virt_mmadr;
696
platform_context_plb_t *platform;
700
platform = (platform_context_plb_t *)context->platform_context;
702
/* Reset MSVDX engine */
703
EMGD_WRITE32(0x11111100, mmio + PSB_MSVDX_CONTROL);
704
reg_ready_psb(context, PSB_MSVDX_CONTROL, 0x00000100, 0);
706
/* Clear interrupt and clear pending interrupts */
707
EMGD_WRITE32(0, mmio + PSB_MSVDX_HOST_INTERRUPT_ENABLE);
708
EMGD_WRITE32(0xffffffff, mmio + PSB_MSVDX_INTERRUPT_CLEAR);
710
/* Mark the engine as being reset */
711
platform->msvdx_needs_reset = 0;
716
* When shuting down, need to reset the MSVDX engine too.
718
int msvdx_shutdown_plb(igd_context_t *context)
720
platform_context_plb_t *platform;
723
platform = (platform_context_plb_t *)context->platform_context;
725
/* Reset MSVDX engine */
726
msvdx_reset_plb(context);
728
/* Free RENDEC memory allocations */
729
platform->rendec_base0 = 0;
730
platform->rendec_base1 = 0;
731
init_msvdx_first_time = 1;
737
static int reg_ready_psb(igd_context_t *context,
742
unsigned char *mmio = context->device_context.virt_mmadr;
743
unsigned long status;
747
status = EMGD_READ32(mmio + reg);
748
if ((status & mask) == value) {
755
/* Timeout waiting for RAM ACCESS ready */
756
EMGD_DEBUG("TIMEOUT: Got 0x%08lx while waiting for 0x%08lx", status, value);
761
static int poll_mtx_irq(igd_context_t *context)
763
unsigned char *mmio = context->device_context.virt_mmadr;
765
unsigned long mtx_int;
770
ret = reg_ready_psb(context, PSB_MSVDX_INTERRUPT_STATUS, mtx_int, mtx_int);
772
/* Timeout waiting on interrupt status */
776
/* Clear the interrupt */
777
EMGD_WRITE32(mtx_int, mmio + PSB_MSVDX_INTERRUPT_CLEAR);
added
removed
emgd-dkms-1.5.15.3082/emgd/video/msvdx/msvdx_init.c
