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Viewing changes to libdrm-poulsbo/shared-core/nv04_timer.c

  • Committer: Luca Forina
  • Date: 2011-02-14 10:01:54 UTC
  • Revision ID: luca.forina@gmail.com-20110214100154-ai9gynuqb1dna2ea
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libdrm-poulsbo/shared-core/nv04_timer.c
 
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#include "drmP.h"
 
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#include "drm.h"
 
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#include "nouveau_drv.h"
 
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#include "nouveau_drm.h"
 
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int
 
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nv04_timer_init(struct drm_device *dev)
 
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{
 
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        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
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        NV_WRITE(NV04_PTIMER_INTR_EN_0, 0x00000000);
 
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        NV_WRITE(NV04_PTIMER_INTR_0, 0xFFFFFFFF);
 
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        NV_WRITE(NV04_PTIMER_NUMERATOR, 0x00000008);
 
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        NV_WRITE(NV04_PTIMER_DENOMINATOR, 0x00000003);
 
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        return 0;
 
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}
 
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uint64_t
 
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nv04_timer_read(struct drm_device *dev)
 
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{
 
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        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
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        uint32_t low;
 
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        /* From kmmio dumps on nv28 this looks like how the blob does this.
 
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         * It reads the high dword twice, before and after.
 
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         * The only explanation seems to be that the 64-bit timer counter
 
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         * advances between high and low dword reads and may corrupt the
 
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         * result. Not confirmed.
 
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         */
 
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        uint32_t high2 = NV_READ(NV04_PTIMER_TIME_1);
 
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        uint32_t high1;
 
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        do {
 
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                high1 = high2;
 
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                low = NV_READ(NV04_PTIMER_TIME_0);
 
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                high2 = NV_READ(NV04_PTIMER_TIME_1);
 
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        } while(high1 != high2);
 
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        return (((uint64_t)high2) << 32) | (uint64_t)low;
 
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}
 
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void
 
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nv04_timer_takedown(struct drm_device *dev)
 
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{
 
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}
 
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