← Back to branch summary

~jderose/ubuntu/raring/qemu/vde-again

« back to all changes in this revision

Viewing changes to hw/grackle_pci.c

  • Committer: Bazaar Package Importer
  • Author(s): Aurelien Jarno, Aurelien Jarno
  • Date: 2009-03-07 06:20:34 UTC
  • mfrom: (1.1.9 upstream)
  • mto: This revision was merged to the branch mainline in revision 7.
  • Revision ID: james.westby@ubuntu.com-20090307062034-i3pead4mw653v2el
Tags: 0.10.0-1
http://bugs.debian.org/514462
http://bugs.debian.org/470231
http://bugs.debian.org/415996
http://bugs.debian.org/513210
http://bugs.debian.org/297572
[ Aurelien Jarno ]
* New upstream release:
  - Fix fr-be keyboard mapping (closes: bug#514462).
  - Fix stat64 structure on ppc-linux-user (closes: bug#470231).
  - Add a chroot option (closes: bug#415996).
  - Add evdev support (closes: bug#513210).
  - Fix loop on symlinks in user mode (closes: bug#297572).
  - Bump depends on openbios-sparc.
  - Depends on openbios-ppc.
  - Update 12_signal_powerpc_support.patch.
  - Update 21_net_soopts.patch.
  - Drop 44_socklen_t_check.patch (merged upstream).
  - Drop 49_null_check.patch (merged upstream).
  - Update 64_ppc_asm_constraints.patch.
  - Drop security/CVE-2008-0928-fedora.patch (merged upstream).
  - Drop security/CVE-2007-5730.patch (merged upstream).
* patches/80_stable-branch.patch: add patches from stable branch:
  - Fix race condition between signal handler/execution loop (closes:
    bug#474386, bug#501731).
* debian/copyright: update.
* Compile and install .dtb files:
  - debian/control: build-depends on device-tree-compiler.
  - debian/patches/81_compile_dtb.patch: new patch from upstream.
  - debian/rules: compile and install bamboo.dtb and mpc8544.dtb.

Show diffs side-by-side

added added

removed removed

Lines of Context:
hw/grackle_pci.c
27
27
#include "ppc_mac.h"
28
28
#include "pci.h"
29
29
 
 
30
/* debug Grackle */
 
31
//#define DEBUG_GRACKLE
 
32
 
 
33
#ifdef DEBUG_GRACKLE
 
34
#define GRACKLE_DPRINTF(fmt, args...) \
 
35
do { printf("GRACKLE: " fmt , ##args); } while (0)
 
36
#else
 
37
#define GRACKLE_DPRINTF(fmt, args...)
 
38
#endif
 
39
 
30
40
typedef target_phys_addr_t pci_addr_t;
31
41
#include "pci_host.h"
32
42
 
36
46
                                       uint32_t val)
37
47
{
38
48
    GrackleState *s = opaque;
 
49
 
 
50
    GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
 
51
                    val);
39
52
#ifdef TARGET_WORDS_BIGENDIAN
40
53
    val = bswap32(val);
41
54
#endif
51
64
#ifdef TARGET_WORDS_BIGENDIAN
52
65
    val = bswap32(val);
53
66
#endif
 
67
    GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
 
68
                    val);
54
69
    return val;
55
70
}
56
71
 
86
101
 
87
102
static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level)
88
103
{
 
104
    GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
89
105
    qemu_set_irq(pic[irq_num + 0x15], level);
90
106
}
91
107
 
 
108
static void pci_grackle_save(QEMUFile* f, void *opaque)
 
109
{
 
110
    PCIDevice *d = opaque;
 
111
 
 
112
    pci_device_save(d, f);
 
113
}
 
114
 
 
115
static int pci_grackle_load(QEMUFile* f, void *opaque, int version_id)
 
116
{
 
117
    PCIDevice *d = opaque;
 
118
 
 
119
    if (version_id != 1)
 
120
        return -EINVAL;
 
121
 
 
122
    return pci_device_load(d, f);
 
123
}
 
124
 
 
125
static void pci_grackle_reset(void *opaque)
 
126
{
 
127
}
 
128
 
92
129
PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
93
130
{
94
131
    GrackleState *s;
107
144
    cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);
108
145
    d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice),
109
146
                            0, NULL, NULL);
110
 
    d->config[0x00] = 0x57; // vendor_id
111
 
    d->config[0x01] = 0x10;
112
 
    d->config[0x02] = 0x02; // device_id
113
 
    d->config[0x03] = 0x00;
 
147
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
 
148
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106);
114
149
    d->config[0x08] = 0x00; // revision
115
150
    d->config[0x09] = 0x01;
116
 
    d->config[0x0a] = 0x00; // class_sub = host
117
 
    d->config[0x0b] = 0x06; // class_base = PCI_bridge
 
151
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
118
152
    d->config[0x0e] = 0x00; // header_type
119
153
 
120
154
#if 0
121
155
    /* PCI2PCI bridge same values as PearPC - check this */
122
 
    d->config[0x00] = 0x11; // vendor_id
123
 
    d->config[0x01] = 0x10;
124
 
    d->config[0x02] = 0x26; // device_id
125
 
    d->config[0x03] = 0x00;
 
156
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
 
157
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
126
158
    d->config[0x08] = 0x02; // revision
127
 
    d->config[0x0a] = 0x04; // class_sub = pci2pci
128
 
    d->config[0x0b] = 0x06; // class_base = PCI_bridge
 
159
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
129
160
    d->config[0x0e] = 0x01; // header_type
130
161
 
131
162
    d->config[0x18] = 0x0;  // primary_bus
144
175
    d->config[0x26] = 0x00; // prefetchable_memory_limit
145
176
    d->config[0x27] = 0x85;
146
177
#endif
 
178
    register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load, d);
 
179
    qemu_register_reset(pci_grackle_reset, d);
 
180
    pci_grackle_reset(d);
 
181
 
147
182
    return s->bus;
148
183
}
149