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const uint32_t *intbit_to_level;
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uint32_t cputimer_lbit, cputimer_mbit;
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uint32_t pil_out[MAX_CPUS];
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struct SLAVIO_CPUINTCTLState *slaves[MAX_CPUS];
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} SLAVIO_INTCTLState;
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typedef struct SLAVIO_CPUINTCTLState {
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uint32_t intreg_pending;
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SLAVIO_INTCTLState *master;
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} SLAVIO_CPUINTCTLState;
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#define INTCTL_MAXADDR 0xf
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#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
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#define INTCTLM_MAXADDR 0x13
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#define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
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#define INTCTLM_MASK 0x1f
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#define INTCTLM_SIZE 0x14
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#define MASTER_IRQ_MASK ~0x0fa2007f
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#define MASTER_DISABLE 0x80000000
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#define CPU_SOFTIRQ_MASK 0xfffe0000
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81
#define CPU_IRQ_INT15_IN 0x0004000
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#define CPU_IRQ_INT15_MASK 0x80000000
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static void slavio_check_interrupts(void *opaque);
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static void slavio_check_interrupts(SLAVIO_INTCTLState *s);
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// per-cpu interrupt controller
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static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
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SLAVIO_INTCTLState *s = opaque;
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SLAVIO_CPUINTCTLState *s = opaque;
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uint32_t saddr, ret;
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cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
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saddr = (addr & INTCTL_MAXADDR) >> 2;
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ret = s->intreg_pending[cpu];
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ret = s->intreg_pending;
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DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, ret);
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DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);
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static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
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SLAVIO_INTCTLState *s = opaque;
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SLAVIO_CPUINTCTLState *s = opaque;
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cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
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saddr = (addr & INTCTL_MAXADDR) >> 2;
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DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
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DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
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case 1: // clear pending softints
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if (val & CPU_IRQ_INT15_IN)
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val |= CPU_IRQ_INT15_MASK;
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val &= CPU_SOFTIRQ_MASK;
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s->intreg_pending[cpu] &= ~val;
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slavio_check_interrupts(s);
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DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
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s->intreg_pending &= ~val;
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slavio_check_interrupts(s->master);
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DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
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case 2: // set softint
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val &= CPU_SOFTIRQ_MASK;
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s->intreg_pending[cpu] |= val;
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slavio_check_interrupts(s);
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DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
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s->intreg_pending |= val;
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slavio_check_interrupts(s->master);
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DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
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static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
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SLAVIO_INTCTLState *s = opaque;
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saddr = (addr & INTCTLM_MASK) >> 2;
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DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
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183
case 2: // clear (enable)
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184
// Force clear unused bits
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val &= MASTER_IRQ_MASK;
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s->intregm_disabled &= ~val;
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DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
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DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
188
s->intregm_disabled);
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slavio_check_interrupts(s);
184
191
case 3: // set (disable, clear pending)
187
194
s->intregm_disabled |= val;
188
195
s->intregm_pending &= ~val;
189
196
slavio_check_interrupts(s);
190
DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
197
DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
198
s->intregm_disabled);
193
201
s->target_cpu = val & (MAX_CPUS - 1);
219
227
for (i = 0; i < MAX_CPUS; i++) {
220
term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
228
term_printf("per-cpu %d: pending 0x%08x\n", i,
229
s->slaves[i]->intreg_pending);
222
term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
231
term_printf("master: pending 0x%08x, disabled 0x%08x\n",
232
s->intregm_pending, s->intregm_disabled);
225
235
void slavio_irq_info(void *opaque)
291
300
s->irq_count[pil]++;
293
302
s->intregm_pending |= mask;
294
s->intreg_pending[s->target_cpu] |= 1 << pil;
303
s->slaves[s->target_cpu]->intreg_pending |= 1 << pil;
296
305
s->intregm_pending &= ~mask;
297
s->intreg_pending[s->target_cpu] &= ~(1 << pil);
306
s->slaves[s->target_cpu]->intreg_pending &= ~(1 << pil);
299
308
slavio_check_interrupts(s);
310
319
s->intregm_pending |= s->cputimer_mbit;
311
s->intreg_pending[cpu] |= s->cputimer_lbit;
320
s->slaves[cpu]->intreg_pending |= s->cputimer_lbit;
313
322
s->intregm_pending &= ~s->cputimer_mbit;
314
s->intreg_pending[cpu] &= ~s->cputimer_lbit;
323
s->slaves[cpu]->intreg_pending &= ~s->cputimer_lbit;
317
326
slavio_check_interrupts(s);
370
379
int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
371
380
SLAVIO_INTCTLState *s;
381
SLAVIO_CPUINTCTLState *slave;
373
383
s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
377
385
s->intbit_to_level = intbit_to_level;
378
386
for (i = 0; i < MAX_CPUS; i++) {
379
slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
387
slave = qemu_mallocz(sizeof(SLAVIO_CPUINTCTLState));
392
slavio_intctl_io_memory = cpu_register_io_memory(0,
393
slavio_intctl_mem_read,
394
slavio_intctl_mem_write,
380
396
cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
381
397
slavio_intctl_io_memory);
399
s->slaves[i] = slave;
382
400
s->cpu_irqs[i] = parent_irq[i];
385
slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
403
slavio_intctlm_io_memory = cpu_register_io_memory(0,
404
slavio_intctlm_mem_read,
405
slavio_intctlm_mem_write,
386
407
cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
388
register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
409
register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
410
slavio_intctl_load, s);
389
411
qemu_register_reset(slavio_intctl_reset, s);
390
412
*irq = qemu_allocate_irqs(slavio_set_irq, s, 32);