593
613
#endif /* TARGET_SPARC64 */
594
614
#endif /* !CONFIG_USER_ONLY */
596
void memcpy32(target_ulong *dst, const target_ulong *src)
608
#ifdef TARGET_SPARC64
609
#if !defined(CONFIG_USER_ONLY)
610
#include "qemu-common.h"
612
#include "qemu-timer.h"
615
void do_tick_set_count(void *opaque, uint64_t count)
617
#if !defined(CONFIG_USER_ONLY)
618
ptimer_set_count(opaque, -count);
622
uint64_t do_tick_get_count(void *opaque)
624
#if !defined(CONFIG_USER_ONLY)
625
return -ptimer_get_count(opaque);
631
void do_tick_set_limit(void *opaque, uint64_t limit)
633
#if !defined(CONFIG_USER_ONLY)
634
ptimer_set_limit(opaque, -limit, 0);
617
#if defined(CONFIG_USER_ONLY)
618
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
624
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
626
target_phys_addr_t phys_addr;
627
int prot, access_index;
629
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
630
MMU_KERNEL_IDX) != 0)
631
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
632
0, MMU_KERNEL_IDX) != 0)
634
if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
640
void cpu_reset(CPUSPARCState *env)
642
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
643
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
644
log_cpu_state(env, 0);
650
env->regwptr = env->regbase + (env->cwp * 16);
651
#if defined(CONFIG_USER_ONLY)
652
#ifdef TARGET_SPARC64
653
env->cleanwin = env->nwindows - 2;
654
env->cansave = env->nwindows - 2;
655
env->pstate = PS_RMO | PS_PEF | PS_IE;
656
env->asi = 0x82; // Primary no-fault
662
#ifdef TARGET_SPARC64
663
env->pstate = PS_PRIV;
664
env->hpstate = HS_PRIV;
665
env->tsptr = &env->ts[env->tl & MAXTL_MASK];
668
env->mmuregs[0] &= ~(MMU_E | MMU_NF);
669
env->mmuregs[0] |= env->def->mmu_bm;
672
env->npc = env->pc + 4;
676
static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
678
sparc_def_t def1, *def = &def1;
680
if (cpu_sparc_find_by_name(def, cpu_model) < 0)
683
env->def = qemu_mallocz(sizeof(*def));
684
memcpy(env->def, def, sizeof(*def));
685
#if defined(CONFIG_USER_ONLY)
686
if ((env->def->features & CPU_FEATURE_FLOAT))
687
env->def->features |= CPU_FEATURE_FLOAT128;
689
env->cpu_model_str = cpu_model;
690
env->version = def->iu_version;
691
env->fsr = def->fpu_version;
692
env->nwindows = def->nwindows;
693
#if !defined(TARGET_SPARC64)
694
env->mmuregs[0] |= def->mmu_version;
695
cpu_sparc_set_id(env, 0);
696
env->mxccregs[7] |= def->mxcc_version;
698
env->mmu_version = def->mmu_version;
699
env->maxtl = def->maxtl;
700
env->version |= def->maxtl << 8;
701
env->version |= def->nwindows - 1;
706
static void cpu_sparc_close(CPUSPARCState *env)
712
CPUSPARCState *cpu_sparc_init(const char *cpu_model)
716
env = qemu_mallocz(sizeof(CPUSPARCState));
719
gen_intermediate_code_init(env);
721
if (cpu_sparc_register(env, cpu_model) < 0) {
722
cpu_sparc_close(env);
730
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
732
#if !defined(TARGET_SPARC64)
733
env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
737
static const sparc_def_t sparc_defs[] = {
738
#ifdef TARGET_SPARC64
740
.name = "Fujitsu Sparc64",
741
.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
742
.fpu_version = 0x00000000,
743
.mmu_version = mmu_us_12,
746
.features = CPU_DEFAULT_FEATURES,
749
.name = "Fujitsu Sparc64 III",
750
.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
751
.fpu_version = 0x00000000,
752
.mmu_version = mmu_us_12,
755
.features = CPU_DEFAULT_FEATURES,
758
.name = "Fujitsu Sparc64 IV",
759
.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
760
.fpu_version = 0x00000000,
761
.mmu_version = mmu_us_12,
764
.features = CPU_DEFAULT_FEATURES,
767
.name = "Fujitsu Sparc64 V",
768
.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
769
.fpu_version = 0x00000000,
770
.mmu_version = mmu_us_12,
773
.features = CPU_DEFAULT_FEATURES,
776
.name = "TI UltraSparc I",
777
.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
778
.fpu_version = 0x00000000,
779
.mmu_version = mmu_us_12,
782
.features = CPU_DEFAULT_FEATURES,
785
.name = "TI UltraSparc II",
786
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
787
.fpu_version = 0x00000000,
788
.mmu_version = mmu_us_12,
791
.features = CPU_DEFAULT_FEATURES,
794
.name = "TI UltraSparc IIi",
795
.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
796
.fpu_version = 0x00000000,
797
.mmu_version = mmu_us_12,
800
.features = CPU_DEFAULT_FEATURES,
803
.name = "TI UltraSparc IIe",
804
.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
805
.fpu_version = 0x00000000,
806
.mmu_version = mmu_us_12,
809
.features = CPU_DEFAULT_FEATURES,
812
.name = "Sun UltraSparc III",
813
.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
814
.fpu_version = 0x00000000,
815
.mmu_version = mmu_us_12,
818
.features = CPU_DEFAULT_FEATURES,
821
.name = "Sun UltraSparc III Cu",
822
.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
823
.fpu_version = 0x00000000,
824
.mmu_version = mmu_us_3,
827
.features = CPU_DEFAULT_FEATURES,
830
.name = "Sun UltraSparc IIIi",
831
.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
832
.fpu_version = 0x00000000,
833
.mmu_version = mmu_us_12,
836
.features = CPU_DEFAULT_FEATURES,
839
.name = "Sun UltraSparc IV",
840
.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
841
.fpu_version = 0x00000000,
842
.mmu_version = mmu_us_4,
845
.features = CPU_DEFAULT_FEATURES,
848
.name = "Sun UltraSparc IV+",
849
.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
850
.fpu_version = 0x00000000,
851
.mmu_version = mmu_us_12,
854
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
857
.name = "Sun UltraSparc IIIi+",
858
.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
859
.fpu_version = 0x00000000,
860
.mmu_version = mmu_us_3,
863
.features = CPU_DEFAULT_FEATURES,
866
.name = "Sun UltraSparc T1",
867
// defined in sparc_ifu_fdp.v and ctu.h
868
.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
869
.fpu_version = 0x00000000,
870
.mmu_version = mmu_sun4v,
873
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
877
.name = "Sun UltraSparc T2",
878
// defined in tlu_asi_ctl.v and n2_revid_cust.v
879
.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
880
.fpu_version = 0x00000000,
881
.mmu_version = mmu_sun4v,
884
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
888
.name = "NEC UltraSparc I",
889
.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
890
.fpu_version = 0x00000000,
891
.mmu_version = mmu_us_12,
894
.features = CPU_DEFAULT_FEATURES,
898
.name = "Fujitsu MB86900",
899
.iu_version = 0x00 << 24, /* Impl 0, ver 0 */
900
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
901
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
902
.mmu_bm = 0x00004000,
903
.mmu_ctpr_mask = 0x007ffff0,
904
.mmu_cxr_mask = 0x0000003f,
905
.mmu_sfsr_mask = 0xffffffff,
906
.mmu_trcr_mask = 0xffffffff,
908
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
911
.name = "Fujitsu MB86904",
912
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
913
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
914
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
915
.mmu_bm = 0x00004000,
916
.mmu_ctpr_mask = 0x00ffffc0,
917
.mmu_cxr_mask = 0x000000ff,
918
.mmu_sfsr_mask = 0x00016fff,
919
.mmu_trcr_mask = 0x00ffffff,
921
.features = CPU_DEFAULT_FEATURES,
924
.name = "Fujitsu MB86907",
925
.iu_version = 0x05 << 24, /* Impl 0, ver 5 */
926
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
927
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
928
.mmu_bm = 0x00004000,
929
.mmu_ctpr_mask = 0xffffffc0,
930
.mmu_cxr_mask = 0x000000ff,
931
.mmu_sfsr_mask = 0x00016fff,
932
.mmu_trcr_mask = 0xffffffff,
934
.features = CPU_DEFAULT_FEATURES,
937
.name = "LSI L64811",
938
.iu_version = 0x10 << 24, /* Impl 1, ver 0 */
939
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
940
.mmu_version = 0x10 << 24,
941
.mmu_bm = 0x00004000,
942
.mmu_ctpr_mask = 0x007ffff0,
943
.mmu_cxr_mask = 0x0000003f,
944
.mmu_sfsr_mask = 0xffffffff,
945
.mmu_trcr_mask = 0xffffffff,
947
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
951
.name = "Cypress CY7C601",
952
.iu_version = 0x11 << 24, /* Impl 1, ver 1 */
953
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
954
.mmu_version = 0x10 << 24,
955
.mmu_bm = 0x00004000,
956
.mmu_ctpr_mask = 0x007ffff0,
957
.mmu_cxr_mask = 0x0000003f,
958
.mmu_sfsr_mask = 0xffffffff,
959
.mmu_trcr_mask = 0xffffffff,
961
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
965
.name = "Cypress CY7C611",
966
.iu_version = 0x13 << 24, /* Impl 1, ver 3 */
967
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
968
.mmu_version = 0x10 << 24,
969
.mmu_bm = 0x00004000,
970
.mmu_ctpr_mask = 0x007ffff0,
971
.mmu_cxr_mask = 0x0000003f,
972
.mmu_sfsr_mask = 0xffffffff,
973
.mmu_trcr_mask = 0xffffffff,
975
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
979
.name = "TI MicroSparc I",
980
.iu_version = 0x41000000,
981
.fpu_version = 4 << 17,
982
.mmu_version = 0x41000000,
983
.mmu_bm = 0x00004000,
984
.mmu_ctpr_mask = 0x007ffff0,
985
.mmu_cxr_mask = 0x0000003f,
986
.mmu_sfsr_mask = 0x00016fff,
987
.mmu_trcr_mask = 0x0000003f,
989
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
990
CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
994
.name = "TI MicroSparc II",
995
.iu_version = 0x42000000,
996
.fpu_version = 4 << 17,
997
.mmu_version = 0x02000000,
998
.mmu_bm = 0x00004000,
999
.mmu_ctpr_mask = 0x00ffffc0,
1000
.mmu_cxr_mask = 0x000000ff,
1001
.mmu_sfsr_mask = 0x00016fff,
1002
.mmu_trcr_mask = 0x00ffffff,
1004
.features = CPU_DEFAULT_FEATURES,
1007
.name = "TI MicroSparc IIep",
1008
.iu_version = 0x42000000,
1009
.fpu_version = 4 << 17,
1010
.mmu_version = 0x04000000,
1011
.mmu_bm = 0x00004000,
1012
.mmu_ctpr_mask = 0x00ffffc0,
1013
.mmu_cxr_mask = 0x000000ff,
1014
.mmu_sfsr_mask = 0x00016bff,
1015
.mmu_trcr_mask = 0x00ffffff,
1017
.features = CPU_DEFAULT_FEATURES,
1020
.name = "TI SuperSparc 40", // STP1020NPGA
1021
.iu_version = 0x41000000, // SuperSPARC 2.x
1022
.fpu_version = 0 << 17,
1023
.mmu_version = 0x00000800, // SuperSPARC 2.x, no MXCC
1024
.mmu_bm = 0x00002000,
1025
.mmu_ctpr_mask = 0xffffffc0,
1026
.mmu_cxr_mask = 0x0000ffff,
1027
.mmu_sfsr_mask = 0xffffffff,
1028
.mmu_trcr_mask = 0xffffffff,
1030
.features = CPU_DEFAULT_FEATURES,
1033
.name = "TI SuperSparc 50", // STP1020PGA
1034
.iu_version = 0x40000000, // SuperSPARC 3.x
1035
.fpu_version = 0 << 17,
1036
.mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
1037
.mmu_bm = 0x00002000,
1038
.mmu_ctpr_mask = 0xffffffc0,
1039
.mmu_cxr_mask = 0x0000ffff,
1040
.mmu_sfsr_mask = 0xffffffff,
1041
.mmu_trcr_mask = 0xffffffff,
1043
.features = CPU_DEFAULT_FEATURES,
1046
.name = "TI SuperSparc 51",
1047
.iu_version = 0x40000000, // SuperSPARC 3.x
1048
.fpu_version = 0 << 17,
1049
.mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
1050
.mmu_bm = 0x00002000,
1051
.mmu_ctpr_mask = 0xffffffc0,
1052
.mmu_cxr_mask = 0x0000ffff,
1053
.mmu_sfsr_mask = 0xffffffff,
1054
.mmu_trcr_mask = 0xffffffff,
1055
.mxcc_version = 0x00000104,
1057
.features = CPU_DEFAULT_FEATURES,
1060
.name = "TI SuperSparc 60", // STP1020APGA
1061
.iu_version = 0x40000000, // SuperSPARC 3.x
1062
.fpu_version = 0 << 17,
1063
.mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
1064
.mmu_bm = 0x00002000,
1065
.mmu_ctpr_mask = 0xffffffc0,
1066
.mmu_cxr_mask = 0x0000ffff,
1067
.mmu_sfsr_mask = 0xffffffff,
1068
.mmu_trcr_mask = 0xffffffff,
1070
.features = CPU_DEFAULT_FEATURES,
1073
.name = "TI SuperSparc 61",
1074
.iu_version = 0x44000000, // SuperSPARC 3.x
1075
.fpu_version = 0 << 17,
1076
.mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
1077
.mmu_bm = 0x00002000,
1078
.mmu_ctpr_mask = 0xffffffc0,
1079
.mmu_cxr_mask = 0x0000ffff,
1080
.mmu_sfsr_mask = 0xffffffff,
1081
.mmu_trcr_mask = 0xffffffff,
1082
.mxcc_version = 0x00000104,
1084
.features = CPU_DEFAULT_FEATURES,
1087
.name = "TI SuperSparc II",
1088
.iu_version = 0x40000000, // SuperSPARC II 1.x
1089
.fpu_version = 0 << 17,
1090
.mmu_version = 0x08000000, // SuperSPARC II 1.x, MXCC
1091
.mmu_bm = 0x00002000,
1092
.mmu_ctpr_mask = 0xffffffc0,
1093
.mmu_cxr_mask = 0x0000ffff,
1094
.mmu_sfsr_mask = 0xffffffff,
1095
.mmu_trcr_mask = 0xffffffff,
1096
.mxcc_version = 0x00000104,
1098
.features = CPU_DEFAULT_FEATURES,
1101
.name = "Ross RT625",
1102
.iu_version = 0x1e000000,
1103
.fpu_version = 1 << 17,
1104
.mmu_version = 0x1e000000,
1105
.mmu_bm = 0x00004000,
1106
.mmu_ctpr_mask = 0x007ffff0,
1107
.mmu_cxr_mask = 0x0000003f,
1108
.mmu_sfsr_mask = 0xffffffff,
1109
.mmu_trcr_mask = 0xffffffff,
1111
.features = CPU_DEFAULT_FEATURES,
1114
.name = "Ross RT620",
1115
.iu_version = 0x1f000000,
1116
.fpu_version = 1 << 17,
1117
.mmu_version = 0x1f000000,
1118
.mmu_bm = 0x00004000,
1119
.mmu_ctpr_mask = 0x007ffff0,
1120
.mmu_cxr_mask = 0x0000003f,
1121
.mmu_sfsr_mask = 0xffffffff,
1122
.mmu_trcr_mask = 0xffffffff,
1124
.features = CPU_DEFAULT_FEATURES,
1127
.name = "BIT B5010",
1128
.iu_version = 0x20000000,
1129
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
1130
.mmu_version = 0x20000000,
1131
.mmu_bm = 0x00004000,
1132
.mmu_ctpr_mask = 0x007ffff0,
1133
.mmu_cxr_mask = 0x0000003f,
1134
.mmu_sfsr_mask = 0xffffffff,
1135
.mmu_trcr_mask = 0xffffffff,
1137
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1141
.name = "Matsushita MN10501",
1142
.iu_version = 0x50000000,
1143
.fpu_version = 0 << 17,
1144
.mmu_version = 0x50000000,
1145
.mmu_bm = 0x00004000,
1146
.mmu_ctpr_mask = 0x007ffff0,
1147
.mmu_cxr_mask = 0x0000003f,
1148
.mmu_sfsr_mask = 0xffffffff,
1149
.mmu_trcr_mask = 0xffffffff,
1151
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
1155
.name = "Weitek W8601",
1156
.iu_version = 0x90 << 24, /* Impl 9, ver 0 */
1157
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1158
.mmu_version = 0x10 << 24,
1159
.mmu_bm = 0x00004000,
1160
.mmu_ctpr_mask = 0x007ffff0,
1161
.mmu_cxr_mask = 0x0000003f,
1162
.mmu_sfsr_mask = 0xffffffff,
1163
.mmu_trcr_mask = 0xffffffff,
1165
.features = CPU_DEFAULT_FEATURES,
1169
.iu_version = 0xf2000000,
1170
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1171
.mmu_version = 0xf2000000,
1172
.mmu_bm = 0x00004000,
1173
.mmu_ctpr_mask = 0x007ffff0,
1174
.mmu_cxr_mask = 0x0000003f,
1175
.mmu_sfsr_mask = 0xffffffff,
1176
.mmu_trcr_mask = 0xffffffff,
1178
.features = CPU_DEFAULT_FEATURES,
1182
.iu_version = 0xf3000000,
1183
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1184
.mmu_version = 0xf3000000,
1185
.mmu_bm = 0x00004000,
1186
.mmu_ctpr_mask = 0x007ffff0,
1187
.mmu_cxr_mask = 0x0000003f,
1188
.mmu_sfsr_mask = 0xffffffff,
1189
.mmu_trcr_mask = 0xffffffff,
1191
.features = CPU_DEFAULT_FEATURES,
1196
static const char * const feature_name[] = {
1213
static void print_features(FILE *f,
1214
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1215
uint32_t features, const char *prefix)
1219
for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1220
if (feature_name[i] && (features & (1 << i))) {
1222
(*cpu_fprintf)(f, "%s", prefix);
1223
(*cpu_fprintf)(f, "%s ", feature_name[i]);
1227
static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
1231
for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1232
if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
1233
*features |= 1 << i;
1236
fprintf(stderr, "CPU feature %s not found\n", flagname);
1239
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
1242
const sparc_def_t *def = NULL;
1243
char *s = strdup(cpu_model);
1244
char *featurestr, *name = strtok(s, ",");
1245
uint32_t plus_features = 0;
1246
uint32_t minus_features = 0;
1247
long long iu_version;
1248
uint32_t fpu_version, mmu_version, nwindows;
1250
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
1251
if (strcasecmp(name, sparc_defs[i].name) == 0) {
1252
def = &sparc_defs[i];
1257
memcpy(cpu_def, def, sizeof(*def));
1259
featurestr = strtok(NULL, ",");
1260
while (featurestr) {
1263
if (featurestr[0] == '+') {
1264
add_flagname_to_bitmaps(featurestr + 1, &plus_features);
1265
} else if (featurestr[0] == '-') {
1266
add_flagname_to_bitmaps(featurestr + 1, &minus_features);
1267
} else if ((val = strchr(featurestr, '='))) {
1269
if (!strcmp(featurestr, "iu_version")) {
1272
iu_version = strtoll(val, &err, 0);
1273
if (!*val || *err) {
1274
fprintf(stderr, "bad numerical value %s\n", val);
1277
cpu_def->iu_version = iu_version;
1278
#ifdef DEBUG_FEATURES
1279
fprintf(stderr, "iu_version %llx\n", iu_version);
1281
} else if (!strcmp(featurestr, "fpu_version")) {
1284
fpu_version = strtol(val, &err, 0);
1285
if (!*val || *err) {
1286
fprintf(stderr, "bad numerical value %s\n", val);
1289
cpu_def->fpu_version = fpu_version;
1290
#ifdef DEBUG_FEATURES
1291
fprintf(stderr, "fpu_version %llx\n", fpu_version);
1293
} else if (!strcmp(featurestr, "mmu_version")) {
1296
mmu_version = strtol(val, &err, 0);
1297
if (!*val || *err) {
1298
fprintf(stderr, "bad numerical value %s\n", val);
1301
cpu_def->mmu_version = mmu_version;
1302
#ifdef DEBUG_FEATURES
1303
fprintf(stderr, "mmu_version %llx\n", mmu_version);
1305
} else if (!strcmp(featurestr, "nwindows")) {
1308
nwindows = strtol(val, &err, 0);
1309
if (!*val || *err || nwindows > MAX_NWINDOWS ||
1310
nwindows < MIN_NWINDOWS) {
1311
fprintf(stderr, "bad numerical value %s\n", val);
1314
cpu_def->nwindows = nwindows;
1315
#ifdef DEBUG_FEATURES
1316
fprintf(stderr, "nwindows %d\n", nwindows);
1319
fprintf(stderr, "unrecognized feature %s\n", featurestr);
1323
fprintf(stderr, "feature string `%s' not in format "
1324
"(+feature|-feature|feature=xyz)\n", featurestr);
1327
featurestr = strtok(NULL, ",");
1329
cpu_def->features |= plus_features;
1330
cpu_def->features &= ~minus_features;
1331
#ifdef DEBUG_FEATURES
1332
print_features(stderr, fprintf, cpu_def->features, NULL);
1342
void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
1346
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
1347
(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ",
1349
sparc_defs[i].iu_version,
1350
sparc_defs[i].fpu_version,
1351
sparc_defs[i].mmu_version,
1352
sparc_defs[i].nwindows);
1353
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
1354
~sparc_defs[i].features, "-");
1355
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
1356
sparc_defs[i].features, "+");
1357
(*cpu_fprintf)(f, "\n");
1359
(*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
1360
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
1361
(*cpu_fprintf)(f, "\n");
1362
(*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
1363
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
1364
(*cpu_fprintf)(f, "\n");
1365
(*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
1366
"fpu_version mmu_version nwindows\n");
1369
#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1371
void cpu_dump_state(CPUState *env, FILE *f,
1372
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1377
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
1379
cpu_fprintf(f, "General Registers:\n");
1380
for (i = 0; i < 4; i++)
1381
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1382
cpu_fprintf(f, "\n");
1384
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1385
cpu_fprintf(f, "\nCurrent Register Window:\n");
1386
for (x = 0; x < 3; x++) {
1387
for (i = 0; i < 4; i++)
1388
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1389
(x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1390
env->regwptr[i + x * 8]);
1391
cpu_fprintf(f, "\n");
1393
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1394
(x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1395
env->regwptr[i + x * 8]);
1396
cpu_fprintf(f, "\n");
1398
cpu_fprintf(f, "\nFloating Point Registers:\n");
1399
for (i = 0; i < 32; i++) {
1401
cpu_fprintf(f, "%%f%02d:", i);
1402
cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]);
1404
cpu_fprintf(f, "\n");
1406
#ifdef TARGET_SPARC64
1407
cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
1408
env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
1409
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d "
1410
"cleanwin %d cwp %d\n",
1411
env->cansave, env->canrestore, env->otherwin, env->wstate,
1412
env->cleanwin, env->nwindows - 1 - env->cwp);
1414
cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
1415
GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1416
GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1417
env->psrs?'S':'-', env->psrps?'P':'-',
1418
env->psret?'E':'-', env->wim);
1420
cpu_fprintf(f, "fsr: 0x%08x\n", env->fsr);