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Viewing changes to drivers/isdn/hisax/hfc_pci.c

  • Committer: Package Import Robot
  • Author(s): maximilian attems, maximilian attems, Ben Hutchings
  • Date: 2012-06-06 10:25:57 UTC
  • mfrom: (1.2.38)
  • Revision ID: package-import@ubuntu.com-20120606102557-b9j3506wcwrqrnx8
Tags: 3.4.1-1~experimental.1
* New upstream release: http://kernelnewbies.org/Linux_3.4
* New upstream stable update:
  http://www.kernel.org/pub/linux/kernel/v3.x/ChangeLog-3.4.1

[ maximilian attems ]
* Enable DM_VERITY, NF_CONNTRACK_TIMEOUT, NF_CT_NETLINK_TIMEOUT,
  IP_NF_MATCH_RPFILTER, IP6_NF_MATCH_RPFILTER, NETFILTER_NETLINK_ACCT,
  NETFILTER_XT_MATCH_NFACCT, NET_SCH_PLUG, SCSI_UFSHCD, SCSI_VIRTIO,
  NET_TEAM, ATH6KL.

[ Ben Hutchings ]
* DFSG: Remove the new vs6624 driver, which contains non-free firmware
* aufs: Update to aufs3.4-20120521
* [rt] Update to 3.4-rt8 and reenable

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added added

removed removed

Lines of Context:
drivers/isdn/hisax/hfc_pci.c
57
57
        {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T, "German telekom", "A1T"},
58
58
        {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575, "Motorola MC145575", "MC145575"},
59
59
        {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0, "Zoltrix", "2BD0"},
60
 
        {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,"Digi International", "Digi DataFire Micro V IOM2 (Europe)"},
61
 
        {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,"Digi International", "Digi DataFire Micro V (Europe)"},
62
 
        {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,"Digi International", "Digi DataFire Micro V IOM2 (North America)"},
63
 
        {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,"Digi International", "Digi DataFire Micro V (North America)"},
 
60
        {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E, "Digi International", "Digi DataFire Micro V IOM2 (Europe)"},
 
61
        {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E, "Digi International", "Digi DataFire Micro V (Europe)"},
 
62
        {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A, "Digi International", "Digi DataFire Micro V IOM2 (North America)"},
 
63
        {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A, "Digi International", "Digi DataFire Micro V (North America)"},
64
64
        {PCI_VENDOR_ID_SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2, "Sitecom Europe", "DC-105 ISDN PCI"},
65
65
        {0, 0, NULL, NULL},
66
66
};
73
73
release_io_hfcpci(struct IsdnCardState *cs)
74
74
{
75
75
        printk(KERN_INFO "HiSax: release hfcpci at %p\n",
76
 
                cs->hw.hfcpci.pci_io);
 
76
               cs->hw.hfcpci.pci_io);
77
77
        cs->hw.hfcpci.int_m2 = 0;                                       /* interrupt output off ! */
78
78
        Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
79
79
        Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET);                       /* Reset On */
84
84
        pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, 0);       /* disable memory mapped ports + busmaster */
85
85
        del_timer(&cs->hw.hfcpci.timer);
86
86
        pci_free_consistent(cs->hw.hfcpci.dev, 0x8000,
87
 
                cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma);
 
87
                            cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma);
88
88
        cs->hw.hfcpci.fifos = NULL;
89
89
        iounmap((void *)cs->hw.hfcpci.pci_io);
90
90
}
124
124
        Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
125
125
 
126
126
        cs->hw.hfcpci.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
127
 
            HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
 
127
                HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
128
128
        Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
129
129
 
130
130
        /* Clear already pending ints */
170
170
        cs->hw.hfcpci.timer.expires = jiffies + 75;
171
171
        /* WD RESET */
172
172
/*      WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcpci.ctmt | 0x80);
173
 
   add_timer(&cs->hw.hfcpci.timer);
174
 
 */
 
173
        add_timer(&cs->hw.hfcpci.timer);
 
174
*/
175
175
}
176
176
 
177
177
 
215
215
/***************************************/
216
216
static void hfcpci_clear_fifo_rx(struct IsdnCardState *cs, int fifo)
217
217
{       u_char fifo_state;
218
 
        bzfifo_type *bzr;
 
218
        bzfifo_type *bzr;
219
219
 
220
220
        if (fifo) {
221
 
                bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
 
221
                bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
222
222
                fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2RX;
223
223
        } else {
224
 
                bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
 
224
                bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
225
225
                fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1RX;
226
226
        }
227
227
        if (fifo_state)
228
 
                cs->hw.hfcpci.fifo_en ^= fifo_state;
 
228
                cs->hw.hfcpci.fifo_en ^= fifo_state;
229
229
        Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
230
230
        cs->hw.hfcpci.last_bfifo_cnt[fifo] = 0;
231
231
        bzr->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
233
233
        bzr->f1 = MAX_B_FRAMES;
234
234
        bzr->f2 = bzr->f1;      /* init F pointers to remain constant */
235
235
        if (fifo_state)
236
 
                cs->hw.hfcpci.fifo_en |= fifo_state;
 
236
                cs->hw.hfcpci.fifo_en |= fifo_state;
237
237
        Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
238
238
}
239
239
 
242
242
/***************************************/
243
243
static void hfcpci_clear_fifo_tx(struct IsdnCardState *cs, int fifo)
244
244
{       u_char fifo_state;
245
 
        bzfifo_type *bzt;
 
245
        bzfifo_type *bzt;
246
246
 
247
247
        if (fifo) {
248
 
                bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
 
248
                bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
249
249
                fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2TX;
250
250
        } else {
251
 
                bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
 
251
                bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
252
252
                fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1TX;
253
253
        }
254
254
        if (fifo_state)
255
 
                cs->hw.hfcpci.fifo_en ^= fifo_state;
 
255
                cs->hw.hfcpci.fifo_en ^= fifo_state;
256
256
        Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
257
257
        bzt->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
258
258
        bzt->za[MAX_B_FRAMES].z2 = bzt->za[MAX_B_FRAMES].z1;
259
259
        bzt->f1 = MAX_B_FRAMES;
260
260
        bzt->f2 = bzt->f1;      /* init F pointers to remain constant */
261
261
        if (fifo_state)
262
 
                cs->hw.hfcpci.fifo_en |= fifo_state;
 
262
                cs->hw.hfcpci.fifo_en |= fifo_state;
263
263
        Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
264
264
}
265
265
 
268
268
/*********************************************/
269
269
static struct sk_buff
270
270
*
271
 
hfcpci_empty_fifo(struct BCState *bcs, bzfifo_type * bz, u_char * bdata, int count)
 
271
hfcpci_empty_fifo(struct BCState *bcs, bzfifo_type *bz, u_char *bdata, int count)
272
272
{
273
273
        u_char *ptr, *ptr1, new_f2;
274
274
        struct sk_buff *skb;
395
395
/* check for transparent receive data and read max one threshold size if avail */
396
396
/*******************************************************************************/
397
397
static int
398
 
hfcpci_empty_fifo_trans(struct BCState *bcs, bzfifo_type * bz, u_char * bdata)
 
398
hfcpci_empty_fifo_trans(struct BCState *bcs, bzfifo_type *bz, u_char *bdata)
399
399
{
400
400
        unsigned short *z1r, *z2r;
401
401
        int new_z2, fcnt, maxlen;
467
467
                bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b1;
468
468
                real_fifo = 0;
469
469
        }
470
 
      Begin:
 
470
Begin:
471
471
        count--;
472
472
        if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
473
473
                debugl1(cs, "rec_data %d blocked", bcs->channel);
494
494
                if (rcnt < 0)
495
495
                        rcnt += MAX_B_FRAMES + 1;
496
496
                if (cs->hw.hfcpci.last_bfifo_cnt[real_fifo] > rcnt + 1) {
497
 
                        rcnt = 0;
 
497
                        rcnt = 0;
498
498
                        hfcpci_clear_fifo_rx(cs, real_fifo);
499
499
                }
500
500
                cs->hw.hfcpci.last_bfifo_cnt[real_fifo] = rcnt;
647
647
                                debugl1(cs, "hfcpci_fill_fifo_trans %d frame length %d discarded",
648
648
                                        bcs->channel, bcs->tx_skb->len);
649
649
 
650
 
                        if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
651
 
                                (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
 
650
                        if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
 
651
                            (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
652
652
                                u_long  flags;
653
653
                                spin_lock_irqsave(&bcs->aclock, flags);
654
654
                                bcs->ackcnt += bcs->tx_skb->len;
710
710
                memcpy(dst, src, count);
711
711
        }
712
712
        bcs->tx_cnt -= bcs->tx_skb->len;
713
 
        if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
714
 
                (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
 
713
        if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
 
714
            (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
715
715
                u_long  flags;
716
716
                spin_lock_irqsave(&bcs->aclock, flags);
717
717
                bcs->ackcnt += bcs->tx_skb->len;
736
736
        struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
737
737
 
738
738
        switch (pr) {
739
 
                case (PH_DATA | REQUEST):
740
 
                case (PH_PULL | REQUEST):
741
 
                case (PH_PULL | INDICATION):
742
 
                        st->l1.l1hw(st, pr, arg);
743
 
                        break;
744
 
                case (PH_ACTIVATE | REQUEST):
745
 
                        st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
746
 
                        break;
747
 
                case (PH_TESTLOOP | REQUEST):
748
 
                        if (1 & (long) arg)
749
 
                                debugl1(cs, "PH_TEST_LOOP B1");
750
 
                        if (2 & (long) arg)
751
 
                                debugl1(cs, "PH_TEST_LOOP B2");
752
 
                        if (!(3 & (long) arg))
753
 
                                debugl1(cs, "PH_TEST_LOOP DISABLED");
754
 
                        st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
755
 
                        break;
756
 
                default:
757
 
                        if (cs->debug)
758
 
                                debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
759
 
                        break;
 
739
        case (PH_DATA | REQUEST):
 
740
        case (PH_PULL | REQUEST):
 
741
        case (PH_PULL | INDICATION):
 
742
                st->l1.l1hw(st, pr, arg);
 
743
                break;
 
744
        case (PH_ACTIVATE | REQUEST):
 
745
                st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
 
746
                break;
 
747
        case (PH_TESTLOOP | REQUEST):
 
748
                if (1 & (long) arg)
 
749
                        debugl1(cs, "PH_TEST_LOOP B1");
 
750
                if (2 & (long) arg)
 
751
                        debugl1(cs, "PH_TEST_LOOP B2");
 
752
                if (!(3 & (long) arg))
 
753
                        debugl1(cs, "PH_TEST_LOOP DISABLED");
 
754
                st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
 
755
                break;
 
756
        default:
 
757
                if (cs->debug)
 
758
                        debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
 
759
                break;
760
760
        }
761
761
}
762
762
 
766
766
/* set/reset echo mode */
767
767
/***********************/
768
768
static int
769
 
hfcpci_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic)
 
769
hfcpci_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic)
770
770
{
771
771
        u_long  flags;
772
772
        int     i = *(unsigned int *) ic->parm.num;
773
773
 
774
774
        if ((ic->arg == 98) &&
775
775
            (!(cs->hw.hfcpci.int_m1 & (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC + HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC)))) {
776
 
                spin_lock_irqsave(&cs->lock, flags);
 
776
                spin_lock_irqsave(&cs->lock, flags);
777
777
                Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_NT); /* ST-Bit delay for NT-Mode */
778
778
                Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 0);    /* HFC ST G0 */
779
779
                udelay(10);
839
839
 
840
840
        bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
841
841
        bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
842
 
      Begin:
 
842
Begin:
843
843
        count--;
844
844
        if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
845
845
                debugl1(cs, "echo_rec_data blocked");
1078
1078
                        } else
1079
1079
                                sched_event_D_pci(cs, D_XMTBUFREADY);
1080
1080
                }
1081
 
              afterXPR:
 
1081
        afterXPR:
1082
1082
                if (cs->hw.hfcpci.int_s1 && count--) {
1083
1083
                        val = cs->hw.hfcpci.int_s1;
1084
1084
                        cs->hw.hfcpci.int_s1 = 0;
1110
1110
        struct sk_buff *skb = arg;
1111
1111
 
1112
1112
        switch (pr) {
1113
 
                case (PH_DATA | REQUEST):
1114
 
                        if (cs->debug & DEB_DLOG_HEX)
1115
 
                                LogFrame(cs, skb->data, skb->len);
1116
 
                        if (cs->debug & DEB_DLOG_VERBOSE)
1117
 
                                dlogframe(cs, skb, 0);
1118
 
                        spin_lock_irqsave(&cs->lock, flags);
1119
 
                        if (cs->tx_skb) {
1120
 
                                skb_queue_tail(&cs->sq, skb);
1121
 
#ifdef L2FRAME_DEBUG            /* psa */
1122
 
                                if (cs->debug & L1_DEB_LAPD)
1123
 
                                        Logl2Frame(cs, skb, "PH_DATA Queued", 0);
1124
 
#endif
1125
 
                        } else {
1126
 
                                cs->tx_skb = skb;
1127
 
                                cs->tx_cnt = 0;
1128
 
#ifdef L2FRAME_DEBUG            /* psa */
1129
 
                                if (cs->debug & L1_DEB_LAPD)
1130
 
                                        Logl2Frame(cs, skb, "PH_DATA", 0);
1131
 
#endif
1132
 
                                if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1133
 
                                        hfcpci_fill_dfifo(cs);
1134
 
                                        test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1135
 
                                } else
1136
 
                                        debugl1(cs, "hfcpci_fill_dfifo blocked");
1137
 
 
1138
 
                        }
1139
 
                        spin_unlock_irqrestore(&cs->lock, flags);
1140
 
                        break;
1141
 
                case (PH_PULL | INDICATION):
1142
 
                        spin_lock_irqsave(&cs->lock, flags);
1143
 
                        if (cs->tx_skb) {
1144
 
                                if (cs->debug & L1_DEB_WARN)
1145
 
                                        debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
1146
 
                                skb_queue_tail(&cs->sq, skb);
1147
 
                                spin_unlock_irqrestore(&cs->lock, flags);
1148
 
                                break;
1149
 
                        }
1150
 
                        if (cs->debug & DEB_DLOG_HEX)
1151
 
                                LogFrame(cs, skb->data, skb->len);
1152
 
                        if (cs->debug & DEB_DLOG_VERBOSE)
1153
 
                                dlogframe(cs, skb, 0);
 
1113
        case (PH_DATA | REQUEST):
 
1114
                if (cs->debug & DEB_DLOG_HEX)
 
1115
                        LogFrame(cs, skb->data, skb->len);
 
1116
                if (cs->debug & DEB_DLOG_VERBOSE)
 
1117
                        dlogframe(cs, skb, 0);
 
1118
                spin_lock_irqsave(&cs->lock, flags);
 
1119
                if (cs->tx_skb) {
 
1120
                        skb_queue_tail(&cs->sq, skb);
 
1121
#ifdef L2FRAME_DEBUG            /* psa */
 
1122
                        if (cs->debug & L1_DEB_LAPD)
 
1123
                                Logl2Frame(cs, skb, "PH_DATA Queued", 0);
 
1124
#endif
 
1125
                } else {
1154
1126
                        cs->tx_skb = skb;
1155
1127
                        cs->tx_cnt = 0;
1156
1128
#ifdef L2FRAME_DEBUG            /* psa */
1157
1129
                        if (cs->debug & L1_DEB_LAPD)
1158
 
                                Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
 
1130
                                Logl2Frame(cs, skb, "PH_DATA", 0);
1159
1131
#endif
1160
1132
                        if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1161
1133
                                hfcpci_fill_dfifo(cs);
1162
1134
                                test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1163
1135
                        } else
1164
1136
                                debugl1(cs, "hfcpci_fill_dfifo blocked");
1165
 
                        spin_unlock_irqrestore(&cs->lock, flags);
1166
 
                        break;
1167
 
                case (PH_PULL | REQUEST):
1168
 
#ifdef L2FRAME_DEBUG            /* psa */
1169
 
                        if (cs->debug & L1_DEB_LAPD)
1170
 
                                debugl1(cs, "-> PH_REQUEST_PULL");
1171
 
#endif
1172
 
                        if (!cs->tx_skb) {
1173
 
                                test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1174
 
                                st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1175
 
                        } else
1176
 
                                test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1177
 
                        break;
1178
 
                case (HW_RESET | REQUEST):
1179
 
                        spin_lock_irqsave(&cs->lock, flags);
1180
 
                        Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);    /* HFC ST 3 */
1181
 
                        udelay(6);
1182
 
                        Write_hfc(cs, HFCPCI_STATES, 3);        /* HFC ST 2 */
1183
 
                        cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1184
 
                        Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1185
 
                        Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
1186
 
                        spin_unlock_irqrestore(&cs->lock, flags);
1187
 
                        l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
1188
 
                        break;
1189
 
                case (HW_ENABLE | REQUEST):
1190
 
                        spin_lock_irqsave(&cs->lock, flags);
1191
 
                        Write_hfc(cs, HFCPCI_STATES, HFCPCI_DO_ACTION);
1192
 
                        spin_unlock_irqrestore(&cs->lock, flags);
1193
 
                        break;
1194
 
                case (HW_DEACTIVATE | REQUEST):
1195
 
                        spin_lock_irqsave(&cs->lock, flags);
1196
 
                        cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER;
1197
 
                        Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1198
 
                        spin_unlock_irqrestore(&cs->lock, flags);
1199
 
                        break;
1200
 
                case (HW_INFO3 | REQUEST):
1201
 
                        spin_lock_irqsave(&cs->lock, flags);
1202
 
                        cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1203
 
                        Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1204
 
                        spin_unlock_irqrestore(&cs->lock, flags);
1205
 
                        break;
1206
 
                case (HW_TESTLOOP | REQUEST):
1207
 
                        spin_lock_irqsave(&cs->lock, flags);
1208
 
                        switch ((long) arg) {
1209
 
                                case (1):
1210
 
                                        Write_hfc(cs, HFCPCI_B1_SSL, 0x80);     /* tx slot */
1211
 
                                        Write_hfc(cs, HFCPCI_B1_RSL, 0x80);     /* rx slot */
1212
 
                                        cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1;
1213
 
                                        Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1214
 
                                        break;
1215
 
 
1216
 
                                case (2):
1217
 
                                        Write_hfc(cs, HFCPCI_B2_SSL, 0x81);     /* tx slot */
1218
 
                                        Write_hfc(cs, HFCPCI_B2_RSL, 0x81);     /* rx slot */
1219
 
                                        cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08;
1220
 
                                        Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1221
 
                                        break;
1222
 
 
1223
 
                                default:
1224
 
                                        spin_unlock_irqrestore(&cs->lock, flags);
1225
 
                                        if (cs->debug & L1_DEB_WARN)
1226
 
                                                debugl1(cs, "hfcpci_l1hw loop invalid %4lx", (long) arg);
1227
 
                                        return;
1228
 
                        }
1229
 
                        cs->hw.hfcpci.trm |= 0x80;      /* enable IOM-loop */
1230
 
                        Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
1231
 
                        spin_unlock_irqrestore(&cs->lock, flags);
1232
 
                        break;
 
1137
 
 
1138
                }
 
1139
                spin_unlock_irqrestore(&cs->lock, flags);
 
1140
                break;
 
1141
        case (PH_PULL | INDICATION):
 
1142
                spin_lock_irqsave(&cs->lock, flags);
 
1143
                if (cs->tx_skb) {
 
1144
                        if (cs->debug & L1_DEB_WARN)
 
1145
                                debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
 
1146
                        skb_queue_tail(&cs->sq, skb);
 
1147
                        spin_unlock_irqrestore(&cs->lock, flags);
 
1148
                        break;
 
1149
                }
 
1150
                if (cs->debug & DEB_DLOG_HEX)
 
1151
                        LogFrame(cs, skb->data, skb->len);
 
1152
                if (cs->debug & DEB_DLOG_VERBOSE)
 
1153
                        dlogframe(cs, skb, 0);
 
1154
                cs->tx_skb = skb;
 
1155
                cs->tx_cnt = 0;
 
1156
#ifdef L2FRAME_DEBUG            /* psa */
 
1157
                if (cs->debug & L1_DEB_LAPD)
 
1158
                        Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
 
1159
#endif
 
1160
                if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 
1161
                        hfcpci_fill_dfifo(cs);
 
1162
                        test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 
1163
                } else
 
1164
                        debugl1(cs, "hfcpci_fill_dfifo blocked");
 
1165
                spin_unlock_irqrestore(&cs->lock, flags);
 
1166
                break;
 
1167
        case (PH_PULL | REQUEST):
 
1168
#ifdef L2FRAME_DEBUG            /* psa */
 
1169
                if (cs->debug & L1_DEB_LAPD)
 
1170
                        debugl1(cs, "-> PH_REQUEST_PULL");
 
1171
#endif
 
1172
                if (!cs->tx_skb) {
 
1173
                        test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 
1174
                        st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
 
1175
                } else
 
1176
                        test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 
1177
                break;
 
1178
        case (HW_RESET | REQUEST):
 
1179
                spin_lock_irqsave(&cs->lock, flags);
 
1180
                Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);    /* HFC ST 3 */
 
1181
                udelay(6);
 
1182
                Write_hfc(cs, HFCPCI_STATES, 3);        /* HFC ST 2 */
 
1183
                cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
 
1184
                Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
 
1185
                Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
 
1186
                spin_unlock_irqrestore(&cs->lock, flags);
 
1187
                l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
 
1188
                break;
 
1189
        case (HW_ENABLE | REQUEST):
 
1190
                spin_lock_irqsave(&cs->lock, flags);
 
1191
                Write_hfc(cs, HFCPCI_STATES, HFCPCI_DO_ACTION);
 
1192
                spin_unlock_irqrestore(&cs->lock, flags);
 
1193
                break;
 
1194
        case (HW_DEACTIVATE | REQUEST):
 
1195
                spin_lock_irqsave(&cs->lock, flags);
 
1196
                cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER;
 
1197
                Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
 
1198
                spin_unlock_irqrestore(&cs->lock, flags);
 
1199
                break;
 
1200
        case (HW_INFO3 | REQUEST):
 
1201
                spin_lock_irqsave(&cs->lock, flags);
 
1202
                cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
 
1203
                Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
 
1204
                spin_unlock_irqrestore(&cs->lock, flags);
 
1205
                break;
 
1206
        case (HW_TESTLOOP | REQUEST):
 
1207
                spin_lock_irqsave(&cs->lock, flags);
 
1208
                switch ((long) arg) {
 
1209
                case (1):
 
1210
                        Write_hfc(cs, HFCPCI_B1_SSL, 0x80);     /* tx slot */
 
1211
                        Write_hfc(cs, HFCPCI_B1_RSL, 0x80);     /* rx slot */
 
1212
                        cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1;
 
1213
                        Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
 
1214
                        break;
 
1215
 
 
1216
                case (2):
 
1217
                        Write_hfc(cs, HFCPCI_B2_SSL, 0x81);     /* tx slot */
 
1218
                        Write_hfc(cs, HFCPCI_B2_RSL, 0x81);     /* rx slot */
 
1219
                        cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08;
 
1220
                        Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
 
1221
                        break;
 
1222
 
1233
1223
                default:
 
1224
                        spin_unlock_irqrestore(&cs->lock, flags);
1234
1225
                        if (cs->debug & L1_DEB_WARN)
1235
 
                                debugl1(cs, "hfcpci_l1hw unknown pr %4x", pr);
1236
 
                        break;
 
1226
                                debugl1(cs, "hfcpci_l1hw loop invalid %4lx", (long) arg);
 
1227
                        return;
 
1228
                }
 
1229
                cs->hw.hfcpci.trm |= 0x80;      /* enable IOM-loop */
 
1230
                Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
 
1231
                spin_unlock_irqrestore(&cs->lock, flags);
 
1232
                break;
 
1233
        default:
 
1234
                if (cs->debug & L1_DEB_WARN)
 
1235
                        debugl1(cs, "hfcpci_l1hw unknown pr %4x", pr);
 
1236
                break;
1237
1237
        }
1238
1238
}
1239
1239
 
1295
1295
                }
1296
1296
        }
1297
1297
        switch (mode) {
1298
 
                case (L1_MODE_NULL):
1299
 
                        if (bc) {
1300
 
                                cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
1301
 
                                cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
1302
 
                        } else {
1303
 
                                cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA;
1304
 
                                cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA;
1305
 
                        }
1306
 
                        if (fifo2) {
1307
 
                                cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1308
 
                                cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1309
 
                        } else {
1310
 
                                cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1311
 
                                cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1312
 
                        }
1313
 
                        break;
1314
 
                case (L1_MODE_TRANS):
1315
 
                        hfcpci_clear_fifo_rx(cs, fifo2);
1316
 
                        hfcpci_clear_fifo_tx(cs, fifo2);
1317
 
                        if (bc) {
1318
 
                                cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1319
 
                                cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1320
 
                        } else {
1321
 
                                cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1322
 
                                cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1323
 
                        }
1324
 
                        if (fifo2) {
1325
 
                                cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1326
 
                                cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1327
 
                                cs->hw.hfcpci.ctmt |= 2;
1328
 
                                cs->hw.hfcpci.conn &= ~0x18;
1329
 
                        } else {
1330
 
                                cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1331
 
                                cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1332
 
                                cs->hw.hfcpci.ctmt |= 1;
1333
 
                                cs->hw.hfcpci.conn &= ~0x03;
1334
 
                        }
1335
 
                        break;
1336
 
                case (L1_MODE_HDLC):
1337
 
                        hfcpci_clear_fifo_rx(cs, fifo2);
1338
 
                        hfcpci_clear_fifo_tx(cs, fifo2);
1339
 
                        if (bc) {
1340
 
                                cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1341
 
                                cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1342
 
                        } else {
1343
 
                                cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1344
 
                                cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1345
 
                        }
1346
 
                        if (fifo2) {
1347
 
                                cs->hw.hfcpci.last_bfifo_cnt[1] = 0;
1348
 
                                cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1349
 
                                cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1350
 
                                cs->hw.hfcpci.ctmt &= ~2;
1351
 
                                cs->hw.hfcpci.conn &= ~0x18;
1352
 
                        } else {
1353
 
                                cs->hw.hfcpci.last_bfifo_cnt[0] = 0;
1354
 
                                cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1355
 
                                cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1356
 
                                cs->hw.hfcpci.ctmt &= ~1;
1357
 
                                cs->hw.hfcpci.conn &= ~0x03;
1358
 
                        }
1359
 
                        break;
1360
 
                case (L1_MODE_EXTRN):
1361
 
                        if (bc) {
1362
 
                                cs->hw.hfcpci.conn |= 0x10;
1363
 
                                cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1364
 
                                cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1365
 
                                cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1366
 
                                cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1367
 
                        } else {
1368
 
                                cs->hw.hfcpci.conn |= 0x02;
1369
 
                                cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1370
 
                                cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1371
 
                                cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1372
 
                                cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1373
 
                        }
1374
 
                        break;
 
1298
        case (L1_MODE_NULL):
 
1299
                if (bc) {
 
1300
                        cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
 
1301
                        cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
 
1302
                } else {
 
1303
                        cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA;
 
1304
                        cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA;
 
1305
                }
 
1306
                if (fifo2) {
 
1307
                        cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
 
1308
                        cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
 
1309
                } else {
 
1310
                        cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
 
1311
                        cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
 
1312
                }
 
1313
                break;
 
1314
        case (L1_MODE_TRANS):
 
1315
                hfcpci_clear_fifo_rx(cs, fifo2);
 
1316
                hfcpci_clear_fifo_tx(cs, fifo2);
 
1317
                if (bc) {
 
1318
                        cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
 
1319
                        cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
 
1320
                } else {
 
1321
                        cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
 
1322
                        cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
 
1323
                }
 
1324
                if (fifo2) {
 
1325
                        cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
 
1326
                        cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
 
1327
                        cs->hw.hfcpci.ctmt |= 2;
 
1328
                        cs->hw.hfcpci.conn &= ~0x18;
 
1329
                } else {
 
1330
                        cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
 
1331
                        cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
 
1332
                        cs->hw.hfcpci.ctmt |= 1;
 
1333
                        cs->hw.hfcpci.conn &= ~0x03;
 
1334
                }
 
1335
                break;
 
1336
        case (L1_MODE_HDLC):
 
1337
                hfcpci_clear_fifo_rx(cs, fifo2);
 
1338
                hfcpci_clear_fifo_tx(cs, fifo2);
 
1339
                if (bc) {
 
1340
                        cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
 
1341
                        cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
 
1342
                } else {
 
1343
                        cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
 
1344
                        cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
 
1345
                }
 
1346
                if (fifo2) {
 
1347
                        cs->hw.hfcpci.last_bfifo_cnt[1] = 0;
 
1348
                        cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
 
1349
                        cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
 
1350
                        cs->hw.hfcpci.ctmt &= ~2;
 
1351
                        cs->hw.hfcpci.conn &= ~0x18;
 
1352
                } else {
 
1353
                        cs->hw.hfcpci.last_bfifo_cnt[0] = 0;
 
1354
                        cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
 
1355
                        cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
 
1356
                        cs->hw.hfcpci.ctmt &= ~1;
 
1357
                        cs->hw.hfcpci.conn &= ~0x03;
 
1358
                }
 
1359
                break;
 
1360
        case (L1_MODE_EXTRN):
 
1361
                if (bc) {
 
1362
                        cs->hw.hfcpci.conn |= 0x10;
 
1363
                        cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
 
1364
                        cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
 
1365
                        cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
 
1366
                        cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
 
1367
                } else {
 
1368
                        cs->hw.hfcpci.conn |= 0x02;
 
1369
                        cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
 
1370
                        cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
 
1371
                        cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
 
1372
                        cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
 
1373
                }
 
1374
                break;
1375
1375
        }
1376
1376
        Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e);
1377
1377
        Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1393
1393
        struct sk_buff  *skb = arg;
1394
1394
 
1395
1395
        switch (pr) {
1396
 
                case (PH_DATA | REQUEST):
1397
 
                        spin_lock_irqsave(&bcs->cs->lock, flags);
1398
 
                        if (bcs->tx_skb) {
1399
 
                                skb_queue_tail(&bcs->squeue, skb);
1400
 
                        } else {
1401
 
                                bcs->tx_skb = skb;
 
1396
        case (PH_DATA | REQUEST):
 
1397
                spin_lock_irqsave(&bcs->cs->lock, flags);
 
1398
                if (bcs->tx_skb) {
 
1399
                        skb_queue_tail(&bcs->squeue, skb);
 
1400
                } else {
 
1401
                        bcs->tx_skb = skb;
1402
1402
//                              test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1403
 
                                bcs->cs->BC_Send_Data(bcs);
1404
 
                        }
 
1403
                        bcs->cs->BC_Send_Data(bcs);
 
1404
                }
 
1405
                spin_unlock_irqrestore(&bcs->cs->lock, flags);
 
1406
                break;
 
1407
        case (PH_PULL | INDICATION):
 
1408
                spin_lock_irqsave(&bcs->cs->lock, flags);
 
1409
                if (bcs->tx_skb) {
1405
1410
                        spin_unlock_irqrestore(&bcs->cs->lock, flags);
 
1411
                        printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
1406
1412
                        break;
1407
 
                case (PH_PULL | INDICATION):
1408
 
                        spin_lock_irqsave(&bcs->cs->lock, flags);
1409
 
                        if (bcs->tx_skb) {
1410
 
                                spin_unlock_irqrestore(&bcs->cs->lock, flags);
1411
 
                                printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
1412
 
                                break;
1413
 
                        }
 
1413
                }
1414
1414
//                      test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1415
 
                        bcs->tx_skb = skb;
1416
 
                        bcs->cs->BC_Send_Data(bcs);
1417
 
                        spin_unlock_irqrestore(&bcs->cs->lock, flags);
1418
 
                        break;
1419
 
                case (PH_PULL | REQUEST):
1420
 
                        if (!bcs->tx_skb) {
1421
 
                                test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1422
 
                                st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1423
 
                        } else
1424
 
                                test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1425
 
                        break;
1426
 
                case (PH_ACTIVATE | REQUEST):
1427
 
                        spin_lock_irqsave(&bcs->cs->lock, flags);
1428
 
                        test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
1429
 
                        mode_hfcpci(bcs, st->l1.mode, st->l1.bc);
1430
 
                        spin_unlock_irqrestore(&bcs->cs->lock, flags);
1431
 
                        l1_msg_b(st, pr, arg);
1432
 
                        break;
1433
 
                case (PH_DEACTIVATE | REQUEST):
1434
 
                        l1_msg_b(st, pr, arg);
1435
 
                        break;
1436
 
                case (PH_DEACTIVATE | CONFIRM):
1437
 
                        spin_lock_irqsave(&bcs->cs->lock, flags);
1438
 
                        test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
1439
 
                        test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1440
 
                        mode_hfcpci(bcs, 0, st->l1.bc);
1441
 
                        spin_unlock_irqrestore(&bcs->cs->lock, flags);
1442
 
                        st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1443
 
                        break;
 
1415
                bcs->tx_skb = skb;
 
1416
                bcs->cs->BC_Send_Data(bcs);
 
1417
                spin_unlock_irqrestore(&bcs->cs->lock, flags);
 
1418
                break;
 
1419
        case (PH_PULL | REQUEST):
 
1420
                if (!bcs->tx_skb) {
 
1421
                        test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 
1422
                        st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
 
1423
                } else
 
1424
                        test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 
1425
                break;
 
1426
        case (PH_ACTIVATE | REQUEST):
 
1427
                spin_lock_irqsave(&bcs->cs->lock, flags);
 
1428
                test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
 
1429
                mode_hfcpci(bcs, st->l1.mode, st->l1.bc);
 
1430
                spin_unlock_irqrestore(&bcs->cs->lock, flags);
 
1431
                l1_msg_b(st, pr, arg);
 
1432
                break;
 
1433
        case (PH_DEACTIVATE | REQUEST):
 
1434
                l1_msg_b(st, pr, arg);
 
1435
                break;
 
1436
        case (PH_DEACTIVATE | CONFIRM):
 
1437
                spin_lock_irqsave(&bcs->cs->lock, flags);
 
1438
                test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
 
1439
                test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 
1440
                mode_hfcpci(bcs, 0, st->l1.bc);
 
1441
                spin_unlock_irqrestore(&bcs->cs->lock, flags);
 
1442
                st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
 
1443
                break;
1444
1444
        }
1445
1445
}
1446
1446
 
1510
1510
        if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1511
1511
                if (!cs->hw.hfcpci.nt_mode)
1512
1512
                        switch (cs->dc.hfcpci.ph_state) {
1513
 
                                case (0):
1514
 
                                        l1_msg(cs, HW_RESET | INDICATION, NULL);
1515
 
                                        break;
1516
 
                                case (3):
1517
 
                                        l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1518
 
                                        break;
1519
 
                                case (8):
1520
 
                                        l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1521
 
                                        break;
1522
 
                                case (6):
1523
 
                                        l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1524
 
                                        break;
1525
 
                                case (7):
1526
 
                                        l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1527
 
                                        break;
1528
 
                                default:
1529
 
                                        break;
1530
 
                } else {
 
1513
                        case (0):
 
1514
                                l1_msg(cs, HW_RESET | INDICATION, NULL);
 
1515
                                break;
 
1516
                        case (3):
 
1517
                                l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
 
1518
                                break;
 
1519
                        case (8):
 
1520
                                l1_msg(cs, HW_RSYNC | INDICATION, NULL);
 
1521
                                break;
 
1522
                        case (6):
 
1523
                                l1_msg(cs, HW_INFO2 | INDICATION, NULL);
 
1524
                                break;
 
1525
                        case (7):
 
1526
                                l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
 
1527
                                break;
 
1528
                        default:
 
1529
                                break;
 
1530
                        } else {
1531
1531
                        spin_lock_irqsave(&cs->lock, flags);
1532
1532
                        switch (cs->dc.hfcpci.ph_state) {
1533
 
                                case (2):
1534
 
                                        if (cs->hw.hfcpci.nt_timer < 0) {
1535
 
                                                cs->hw.hfcpci.nt_timer = 0;
1536
 
                                                cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1537
 
                                                Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1538
 
                                                /* Clear already pending ints */
1539
 
                                                if (Read_hfc(cs, HFCPCI_INT_S1));
1540
 
                                                Write_hfc(cs, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
1541
 
                                                udelay(10);
1542
 
                                                Write_hfc(cs, HFCPCI_STATES, 4);
1543
 
                                                cs->dc.hfcpci.ph_state = 4;
1544
 
                                        } else {
1545
 
                                                cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER;
1546
 
                                                Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1547
 
                                                cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER;
1548
 
                                                cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125;
1549
 
                                                Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1550
 
                                                Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1551
 
                                                cs->hw.hfcpci.nt_timer = NT_T1_COUNT;
1552
 
                                                Write_hfc(cs, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);      /* allow G2 -> G3 transition */
1553
 
                                        }
1554
 
                                        break;
1555
 
                                case (1):
1556
 
                                case (3):
1557
 
                                case (4):
 
1533
                        case (2):
 
1534
                                if (cs->hw.hfcpci.nt_timer < 0) {
1558
1535
                                        cs->hw.hfcpci.nt_timer = 0;
1559
1536
                                        cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1560
1537
                                        Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1561
 
                                        break;
1562
 
                                default:
1563
 
                                        break;
 
1538
                                        /* Clear already pending ints */
 
1539
                                        if (Read_hfc(cs, HFCPCI_INT_S1));
 
1540
                                        Write_hfc(cs, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
 
1541
                                        udelay(10);
 
1542
                                        Write_hfc(cs, HFCPCI_STATES, 4);
 
1543
                                        cs->dc.hfcpci.ph_state = 4;
 
1544
                                } else {
 
1545
                                        cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER;
 
1546
                                        Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
 
1547
                                        cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER;
 
1548
                                        cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125;
 
1549
                                        Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
 
1550
                                        Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
 
1551
                                        cs->hw.hfcpci.nt_timer = NT_T1_COUNT;
 
1552
                                        Write_hfc(cs, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);      /* allow G2 -> G3 transition */
 
1553
                                }
 
1554
                                break;
 
1555
                        case (1):
 
1556
                        case (3):
 
1557
                        case (4):
 
1558
                                cs->hw.hfcpci.nt_timer = 0;
 
1559
                                cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
 
1560
                                Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
 
1561
                                break;
 
1562
                        default:
 
1563
                                break;
1564
1564
                        }
1565
1565
                        spin_unlock_irqrestore(&cs->lock, flags);
1566
1566
                }
1602
1602
        if (cs->debug & L1_DEB_ISAC)
1603
1603
                debugl1(cs, "HFCPCI: card_msg %x", mt);
1604
1604
        switch (mt) {
1605
 
                case CARD_RESET:
1606
 
                        spin_lock_irqsave(&cs->lock, flags);
1607
 
                        reset_hfcpci(cs);
1608
 
                        spin_unlock_irqrestore(&cs->lock, flags);
1609
 
                        return (0);
1610
 
                case CARD_RELEASE:
1611
 
                        release_io_hfcpci(cs);
1612
 
                        return (0);
1613
 
                case CARD_INIT:
1614
 
                        spin_lock_irqsave(&cs->lock, flags);
1615
 
                        inithfcpci(cs);
1616
 
                        reset_hfcpci(cs);
1617
 
                        spin_unlock_irqrestore(&cs->lock, flags);
1618
 
                        msleep(80);                             /* Timeout 80ms */
1619
 
                        /* now switch timer interrupt off */
1620
 
                        spin_lock_irqsave(&cs->lock, flags);
1621
 
                        cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1622
 
                        Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1623
 
                        /* reinit mode reg */
1624
 
                        Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1625
 
                        spin_unlock_irqrestore(&cs->lock, flags);
1626
 
                        return (0);
1627
 
                case CARD_TEST:
1628
 
                        return (0);
 
1605
        case CARD_RESET:
 
1606
                spin_lock_irqsave(&cs->lock, flags);
 
1607
                reset_hfcpci(cs);
 
1608
                spin_unlock_irqrestore(&cs->lock, flags);
 
1609
                return (0);
 
1610
        case CARD_RELEASE:
 
1611
                release_io_hfcpci(cs);
 
1612
                return (0);
 
1613
        case CARD_INIT:
 
1614
                spin_lock_irqsave(&cs->lock, flags);
 
1615
                inithfcpci(cs);
 
1616
                reset_hfcpci(cs);
 
1617
                spin_unlock_irqrestore(&cs->lock, flags);
 
1618
                msleep(80);                             /* Timeout 80ms */
 
1619
                /* now switch timer interrupt off */
 
1620
                spin_lock_irqsave(&cs->lock, flags);
 
1621
                cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
 
1622
                Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
 
1623
                /* reinit mode reg */
 
1624
                Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
 
1625
                spin_unlock_irqrestore(&cs->lock, flags);
 
1626
                return (0);
 
1627
        case CARD_TEST:
 
1628
                return (0);
1629
1629
        }
1630
1630
        return (0);
1631
1631
}
1654
1654
        cs->dc.hfcpci.ph_state = 0;
1655
1655
        cs->hw.hfcpci.fifo = 255;
1656
1656
        if (cs->typ != ISDN_CTYPE_HFC_PCI)
1657
 
                return(0);
 
1657
                return (0);
1658
1658
 
1659
1659
        i = 0;
1660
1660
        while (id_list[i].vendor_id) {
1661
1661
                tmp_hfcpci = hisax_find_pci_device(id_list[i].vendor_id,
1662
 
                                             id_list[i].device_id,
1663
 
                                             dev_hfcpci);
 
1662
                                                   id_list[i].device_id,
 
1663
                                                   dev_hfcpci);
1664
1664
                i++;
1665
1665
                if (tmp_hfcpci) {
1666
1666
                        dma_addr_t      dma_mask = DMA_BIT_MASK(32) & ~0x7fffUL;
1668
1668
                                continue;
1669
1669
                        if (pci_set_dma_mask(tmp_hfcpci, dma_mask)) {
1670
1670
                                printk(KERN_WARNING
1671
 
                                        "HiSax hfc_pci: No suitable DMA available.\n");
 
1671
                                       "HiSax hfc_pci: No suitable DMA available.\n");
1672
1672
                                continue;
1673
1673
                        }
1674
1674
                        if (pci_set_consistent_dma_mask(tmp_hfcpci, dma_mask)) {
1675
1675
                                printk(KERN_WARNING
1676
 
                                        "HiSax hfc_pci: No suitable consistent DMA available.\n");
 
1676
                                       "HiSax hfc_pci: No suitable consistent DMA available.\n");
1677
1677
                                continue;
1678
1678
                        }
1679
1679
                        pci_set_master(tmp_hfcpci);
1680
 
                        if ((card->para[0]) && (card->para[0] != (tmp_hfcpci->resource[ 0].start & PCI_BASE_ADDRESS_IO_MASK)))
 
1680
                        if ((card->para[0]) && (card->para[0] != (tmp_hfcpci->resource[0].start & PCI_BASE_ADDRESS_IO_MASK)))
1681
1681
                                continue;
1682
1682
                        else
1683
1683
                                break;
1707
1707
 
1708
1708
        /* Allocate memory for FIFOS */
1709
1709
        cs->hw.hfcpci.fifos = pci_alloc_consistent(cs->hw.hfcpci.dev,
1710
 
                                        0x8000, &cs->hw.hfcpci.dma);
 
1710
                                                   0x8000, &cs->hw.hfcpci.dma);
1711
1711
        if (!cs->hw.hfcpci.fifos) {
1712
1712
                printk(KERN_WARNING "HFC-PCI: Error allocating FIFO memory!\n");
1713
1713
                return 0;
1714
1714
        }
1715
1715
        if (cs->hw.hfcpci.dma & 0x7fff) {
1716
1716
                printk(KERN_WARNING
1717
 
                    "HFC-PCI: Error DMA memory not on 32K boundary (%lx)\n",
1718
 
                    (u_long)cs->hw.hfcpci.dma);
 
1717
                       "HFC-PCI: Error DMA memory not on 32K boundary (%lx)\n",
 
1718
                       (u_long)cs->hw.hfcpci.dma);
1719
1719
                pci_free_consistent(cs->hw.hfcpci.dev, 0x8000,
1720
 
                        cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma);
 
1720
                                    cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma);
1721
1721
                return 0;
1722
1722
        }
1723
1723
        pci_write_config_dword(cs->hw.hfcpci.dev, 0x80, (u32)cs->hw.hfcpci.dma);