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Viewing changes to drivers/net/wireless/rtlwifi/rtl8192se/phy.c

  • Committer: Package Import Robot
  • Author(s): maximilian attems, maximilian attems, Ben Hutchings
  • Date: 2012-06-06 10:25:57 UTC
  • mfrom: (1.2.38)
  • Revision ID: package-import@ubuntu.com-20120606102557-b9j3506wcwrqrnx8
Tags: 3.4.1-1~experimental.1
* New upstream release: http://kernelnewbies.org/Linux_3.4
* New upstream stable update:
  http://www.kernel.org/pub/linux/kernel/v3.x/ChangeLog-3.4.1

[ maximilian attems ]
* Enable DM_VERITY, NF_CONNTRACK_TIMEOUT, NF_CT_NETLINK_TIMEOUT,
  IP_NF_MATCH_RPFILTER, IP6_NF_MATCH_RPFILTER, NETFILTER_NETLINK_ACCT,
  NETFILTER_XT_MATCH_NFACCT, NET_SCH_PLUG, SCSI_UFSHCD, SCSI_VIRTIO,
  NET_TEAM, ATH6KL.

[ Ben Hutchings ]
* DFSG: Remove the new vs6624 driver, which contains non-free firmware
* aufs: Update to aufs3.4-20120521
* [rt] Update to 3.4-rt8 and reenable

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Lines of Context:
drivers/net/wireless/rtlwifi/rtl8192se/phy.c
1
1
/******************************************************************************
2
2
 *
3
 
 * Copyright(c) 2009-2010  Realtek Corporation.
 
3
 * Copyright(c) 2009-2012  Realtek Corporation.
4
4
 *
5
5
 * This program is free software; you can redistribute it and/or modify it
6
6
 * under the terms of version 2 of the GNU General Public License as
27
27
 *
28
28
 *****************************************************************************/
29
29
 
30
 
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
 
 
32
30
#include "../wifi.h"
33
31
#include "../pci.h"
34
32
#include "../ps.h"
58
56
        struct rtl_priv *rtlpriv = rtl_priv(hw);
59
57
        u32 returnvalue = 0, originalvalue, bitshift;
60
58
 
61
 
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x)\n",
62
 
                        regaddr, bitmask));
 
59
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
 
60
                 regaddr, bitmask);
63
61
 
64
62
        originalvalue = rtl_read_dword(rtlpriv, regaddr);
65
63
        bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
66
64
        returnvalue = (originalvalue & bitmask) >> bitshift;
67
65
 
68
 
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
69
 
                 ("BBR MASK=0x%x Addr[0x%x]=0x%x\n",
70
 
                 bitmask, regaddr, originalvalue));
 
66
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
 
67
                 bitmask, regaddr, originalvalue);
71
68
 
72
69
        return returnvalue;
73
70
 
79
76
        struct rtl_priv *rtlpriv = rtl_priv(hw);
80
77
        u32 originalvalue, bitshift;
81
78
 
82
 
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
83
 
                        " data(%#x)\n", regaddr, bitmask, data));
 
79
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 
80
                 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
 
81
                 regaddr, bitmask, data);
84
82
 
85
83
        if (bitmask != MASKDWORD) {
86
84
                originalvalue = rtl_read_dword(rtlpriv, regaddr);
90
88
 
91
89
        rtl_write_dword(rtlpriv, regaddr, data);
92
90
 
93
 
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
94
 
                        " data(%#x)\n", regaddr, bitmask, data));
 
91
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 
92
                 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
 
93
                 regaddr, bitmask, data);
95
94
 
96
95
}
97
96
 
149
148
        retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
150
149
                                 BLSSI_READBACK_DATA);
151
150
 
152
 
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x]=0x%x\n",
153
 
                 rfpath, pphyreg->rflssi_readback, retvalue));
 
151
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
 
152
                 rfpath, pphyreg->rflssi_readback, retvalue);
154
153
 
155
154
        return retvalue;
156
155
 
172
171
        data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
173
172
        rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
174
173
 
175
 
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
176
 
                 rfpath, pphyreg->rf3wire_offset, data_and_addr));
 
174
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
 
175
                 rfpath, pphyreg->rf3wire_offset, data_and_addr);
177
176
}
178
177
 
179
178
 
183
182
        struct rtl_priv *rtlpriv = rtl_priv(hw);
184
183
        u32 original_value, readback_value, bitshift;
185
184
 
186
 
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), rfpath(%#x), "
187
 
                 "bitmask(%#x)\n", regaddr, rfpath, bitmask));
 
185
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 
186
                 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
 
187
                 regaddr, rfpath, bitmask);
188
188
 
189
189
        spin_lock(&rtlpriv->locks.rf_lock);
190
190
 
195
195
 
196
196
        spin_unlock(&rtlpriv->locks.rf_lock);
197
197
 
198
 
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), rfpath(%#x), "
199
 
                 "bitmask(%#x), original_value(%#x)\n", regaddr, rfpath,
200
 
                 bitmask, original_value));
 
198
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 
199
                 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
 
200
                 regaddr, rfpath, bitmask, original_value);
201
201
 
202
202
        return readback_value;
203
203
}
212
212
        if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
213
213
                return;
214
214
 
215
 
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
216
 
                 " data(%#x), rfpath(%#x)\n", regaddr, bitmask, data, rfpath));
 
215
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 
216
                 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 
217
                 regaddr, bitmask, data, rfpath);
217
218
 
218
219
        spin_lock(&rtlpriv->locks.rf_lock);
219
220
 
228
229
 
229
230
        spin_unlock(&rtlpriv->locks.rf_lock);
230
231
 
231
 
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x), "
232
 
                 "data(%#x), rfpath(%#x)\n", regaddr, bitmask, data, rfpath));
 
232
        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 
233
                 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 
234
                 regaddr, bitmask, data, rfpath);
233
235
 
234
236
}
235
237
 
249
251
                        break;
250
252
                default:
251
253
                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
252
 
                                 ("Unknown operation.\n"));
 
254
                                 "Unknown operation\n");
253
255
                        break;
254
256
                }
255
257
        }
264
266
        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
265
267
        u8 reg_bw_opmode;
266
268
 
267
 
        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("Switch to %s bandwidth\n",
268
 
                  rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
269
 
                  "20MHz" : "40MHz"));
 
269
        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
 
270
                 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 
271
                 "20MHz" : "40MHz");
270
272
 
271
273
        if (rtlphy->set_bwmode_inprogress)
272
274
                return;
290
292
                break;
291
293
        default:
292
294
                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
293
 
                         ("unknown bandwidth: %#X\n",
294
 
                         rtlphy->current_chan_bw));
 
295
                         "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
295
296
                break;
296
297
        }
297
298
 
316
317
                break;
317
318
        default:
318
319
                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
319
 
                         ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
 
320
                         "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
320
321
                break;
321
322
        }
322
323
 
323
324
        rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
324
325
        rtlphy->set_bwmode_inprogress = false;
325
 
        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
 
326
        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
326
327
}
327
328
 
328
329
static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
332
333
        struct swchnlcmd *pcmd;
333
334
 
334
335
        if (cmdtable == NULL) {
335
 
                RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
 
336
                RT_ASSERT(false, "cmdtable cannot be NULL\n");
336
337
                return false;
337
338
        }
338
339
 
377
378
        rfdependcmdcnt = 0;
378
379
 
379
380
        RT_ASSERT((channel >= 1 && channel <= 14),
380
 
                  ("illegal channel for Zebra: %d\n", channel));
 
381
                  "invalid channel for Zebra: %d\n", channel);
381
382
 
382
383
        _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
383
384
                                         MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
438
439
                        break;
439
440
                default:
440
441
                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
441
 
                                 ("switch case not process\n"));
 
442
                                 "switch case not processed\n");
442
443
                        break;
443
444
                }
444
445
 
458
459
        u32 delay;
459
460
        bool ret;
460
461
 
461
 
        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
462
 
                 ("switch to channel%d\n",
463
 
                 rtlphy->current_channel));
 
462
        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
 
463
                 rtlphy->current_channel);
464
464
 
465
465
        if (rtlphy->sw_chnl_inprogress)
466
466
                return 0;
496
496
 
497
497
        rtlphy->sw_chnl_inprogress = false;
498
498
 
499
 
        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
 
499
        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
500
500
 
501
501
        return 1;
502
502
}
556
556
                                do {
557
557
                                        InitializeCount++;
558
558
                                        RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
559
 
                                                 ("IPS Set eRf nic enable\n"));
 
559
                                                 "IPS Set eRf nic enable\n");
560
560
                                        rtstatus = rtl_ps_enable_nic(hw);
561
 
                                } while ((rtstatus != true) &&
562
 
                                         (InitializeCount < 10));
 
561
                                } while (!rtstatus && (InitializeCount < 10));
563
562
 
564
563
                                RT_CLEAR_PS_LEVEL(ppsc,
565
564
                                                  RT_RF_OFF_LEVL_HALT_NIC);
566
565
                        } else {
567
566
                                RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
568
 
                                         ("awake, sleeped:%d ms "
569
 
                                        "state_inap:%x\n",
570
 
                                        jiffies_to_msecs(jiffies -
571
 
                                        ppsc->last_sleep_jiffies),
572
 
                                        rtlpriv->psc.state_inap));
 
567
                                         "awake, sleeped:%d ms state_inap:%x\n",
 
568
                                         jiffies_to_msecs(jiffies -
 
569
                                                          ppsc->
 
570
                                                          last_sleep_jiffies),
 
571
                                         rtlpriv->psc.state_inap);
573
572
                                ppsc->last_awake_jiffies = jiffies;
574
573
                                rtl_write_word(rtlpriv, CMDR, 0x37FC);
575
574
                                rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
587
586
        case ERFOFF:{
588
587
                        if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
589
588
                                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
590
 
                                         ("IPS Set eRf nic disable\n"));
 
589
                                         "IPS Set eRf nic disable\n");
591
590
                                rtl_ps_disable_nic(hw);
592
591
                                RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
593
592
                        } else {
613
612
                                        continue;
614
613
                                } else {
615
614
                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
616
 
                                                 ("eRf Off/Sleep: "
617
 
                                                 "%d times TcbBusyQueue[%d] = "
618
 
                                                 "%d before doze!\n",
619
 
                                                 (i + 1), queue_id,
620
 
                                                 skb_queue_len(&ring->queue)));
 
615
                                                 "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
 
616
                                                 i + 1, queue_id,
 
617
                                                 skb_queue_len(&ring->queue));
621
618
 
622
619
                                        udelay(10);
623
620
                                        i++;
625
622
 
626
623
                                if (i >= MAX_DOZE_WAITING_TIMES_9x) {
627
624
                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
628
 
                                                 ("\nERFOFF: %d times"
629
 
                                                 "TcbBusyQueue[%d] = %d !\n",
 
625
                                                 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
630
626
                                                 MAX_DOZE_WAITING_TIMES_9x,
631
627
                                                 queue_id,
632
 
                                                 skb_queue_len(&ring->queue)));
 
628
                                                 skb_queue_len(&ring->queue));
633
629
                                        break;
634
630
                                }
635
631
                        }
636
632
 
637
633
                        RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
638
 
                                 ("Set ERFSLEEP awaked:%d ms\n",
 
634
                                 "Set ERFSLEEP awaked:%d ms\n",
639
635
                                 jiffies_to_msecs(jiffies -
640
 
                                 ppsc->last_awake_jiffies)));
 
636
                                                  ppsc->last_awake_jiffies));
641
637
 
642
638
                        RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
643
 
                                 ("sleep awaked:%d ms "
644
 
                                "state_inap:%x\n", jiffies_to_msecs(jiffies -
645
 
                                ppsc->last_awake_jiffies),
646
 
                                rtlpriv->psc.state_inap));
 
639
                                 "sleep awaked:%d ms state_inap:%x\n",
 
640
                                 jiffies_to_msecs(jiffies -
 
641
                                                  ppsc->last_awake_jiffies),
 
642
                                 rtlpriv->psc.state_inap);
647
643
                        ppsc->last_sleep_jiffies = jiffies;
648
644
                        _rtl92se_phy_set_rf_sleep(hw);
649
645
            break;
650
646
        default:
651
647
                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
652
 
                         ("switch case not process\n"));
 
648
                         "switch case not processed\n");
653
649
                bresult = false;
654
650
                break;
655
651
        }
681
677
{
682
678
        struct rtl_priv *rtlpriv = rtl_priv(hw);
683
679
        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 
680
        int index;
684
681
 
685
682
        if (reg_addr == RTXAGC_RATE18_06)
686
 
                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
687
 
                                                                         data;
688
 
        if (reg_addr == RTXAGC_RATE54_24)
689
 
                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
690
 
                                                                         data;
691
 
        if (reg_addr == RTXAGC_CCK_MCS32)
692
 
                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
693
 
                                                                         data;
694
 
        if (reg_addr == RTXAGC_MCS03_MCS00)
695
 
                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
696
 
                                                                         data;
697
 
        if (reg_addr == RTXAGC_MCS07_MCS04)
698
 
                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
699
 
                                                                         data;
700
 
        if (reg_addr == RTXAGC_MCS11_MCS08)
701
 
                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
702
 
                                                                         data;
703
 
        if (reg_addr == RTXAGC_MCS15_MCS12) {
704
 
                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
705
 
                                                                         data;
 
683
                index = 0;
 
684
        else if (reg_addr == RTXAGC_RATE54_24)
 
685
                index = 1;
 
686
        else if (reg_addr == RTXAGC_CCK_MCS32)
 
687
                index = 6;
 
688
        else if (reg_addr == RTXAGC_MCS03_MCS00)
 
689
                index = 2;
 
690
        else if (reg_addr == RTXAGC_MCS07_MCS04)
 
691
                index = 3;
 
692
        else if (reg_addr == RTXAGC_MCS11_MCS08)
 
693
                index = 4;
 
694
        else if (reg_addr == RTXAGC_MCS15_MCS12)
 
695
                index = 5;
 
696
        else
 
697
                return;
 
698
 
 
699
        rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][index] = data;
 
700
        if (index == 5)
706
701
                rtlphy->pwrgroup_cnt++;
707
 
        }
708
702
}
709
703
 
710
704
static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw)
993
987
                rtstatus = false;
994
988
        }
995
989
 
996
 
        if (rtstatus != true) {
 
990
        if (!rtstatus) {
997
991
                RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
998
 
                         ("Write BB Reg Fail!!"));
 
992
                         "Write BB Reg Fail!!\n");
999
993
                goto phy_BB8190_Config_ParaFile_Fail;
1000
994
        }
1001
995
 
1007
1001
                rtstatus = _rtl92s_phy_config_bb_with_pg(hw,
1008
1002
                                                 BASEBAND_CONFIG_PHY_REG);
1009
1003
        }
1010
 
        if (rtstatus != true) {
 
1004
        if (!rtstatus) {
1011
1005
                RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1012
 
                         ("_rtl92s_phy_bb_config_parafile(): "
1013
 
                         "BB_PG Reg Fail!!"));
 
1006
                         "_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
1014
1007
                goto phy_BB8190_Config_ParaFile_Fail;
1015
1008
        }
1016
1009
 
1017
1010
        /* 3. BB AGC table Initialization */
1018
1011
        rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
1019
1012
 
1020
 
        if (rtstatus != true) {
 
1013
        if (!rtstatus) {
1021
1014
                pr_err("%s(): AGC Table Fail\n", __func__);
1022
1015
                goto phy_BB8190_Config_ParaFile_Fail;
1023
1016
        }
1053
1046
                radio_b_tblen = RADIOB_ARRAYLENGTH;
1054
1047
        }
1055
1048
 
1056
 
        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Radio No %x\n", rfpath));
 
1049
        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
1057
1050
        rtstatus = true;
1058
1051
 
1059
1052
        switch (rfpath) {
1175
1168
            (rtlphy->rf_type == RF_2T2R && rf_num != 2) ||
1176
1169
            (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) {
1177
1170
                RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1178
 
                         ("RF_Type(%x) does not match "
1179
 
                         "RF_Num(%x)!!\n", rtlphy->rf_type, rf_num));
 
1171
                         "RF_Type(%x) does not match RF_Num(%x)!!\n",
 
1172
                         rtlphy->rf_type, rf_num);
1180
1173
                RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1181
 
                         ("path1 0x%x, path2 0x%x, pathmap "
1182
 
                          "0x%x\n", path1, path2, pathmap));
 
1174
                         "path1 0x%x, path2 0x%x, pathmap 0x%x\n",
 
1175
                         path1, path2, pathmap);
1183
1176
        }
1184
1177
 
1185
1178
        return rtstatus;
1214
1207
                        ROFDM0_XCAGCCORE1, MASKBYTE0);
1215
1208
        rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
1216
1209
                        ROFDM0_XDAGCCORE1, MASKBYTE0);
1217
 
        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Default initial gain "
1218
 
                 "(c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
 
1210
        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 
1211
                 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1219
1212
                 rtlphy->default_initialgain[0],
1220
1213
                 rtlphy->default_initialgain[1],
1221
1214
                 rtlphy->default_initialgain[2],
1222
 
                 rtlphy->default_initialgain[3]));
 
1215
                 rtlphy->default_initialgain[3]);
1223
1216
 
1224
1217
        /* read framesync */
1225
1218
        rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
1226
1219
        rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1227
1220
                                              MASKDWORD);
1228
1221
        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1229
 
                 ("Default framesync (0x%x) = 0x%x\n",
1230
 
                 ROFDM0_RXDETECTOR3, rtlphy->framesync));
 
1222
                 "Default framesync (0x%x) = 0x%x\n",
 
1223
                 ROFDM0_RXDETECTOR3, rtlphy->framesync);
1231
1224
 
1232
1225
}
1233
1226
 
1274
1267
        /* [0]:RF-A, [1]:RF-B */
1275
1268
        u8 cckpowerlevel[2], ofdmpowerLevel[2];
1276
1269
 
1277
 
        if (rtlefuse->txpwr_fromeprom == false)
 
1270
        if (!rtlefuse->txpwr_fromeprom)
1278
1271
                return;
1279
1272
 
1280
1273
        /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1287
1280
                        &ofdmpowerLevel[0]);
1288
1281
 
1289
1282
        RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1290
 
                        ("Channel-%d, cckPowerLevel (A / B) = "
1291
 
                        "0x%x / 0x%x,   ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1292
 
                        channel, cckpowerlevel[0], cckpowerlevel[1],
1293
 
                        ofdmpowerLevel[0], ofdmpowerLevel[1]));
 
1283
                 "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
 
1284
                 channel, cckpowerlevel[0], cckpowerlevel[1],
 
1285
                 ofdmpowerLevel[0], ofdmpowerLevel[1]);
1294
1286
 
1295
1287
        _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1296
1288
                        &ofdmpowerLevel[0]);
1316
1308
        } while (--pollingcnt);
1317
1309
 
1318
1310
        if (pollingcnt == 0)
1319
 
                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Set FW Cmd fail!!\n"));
 
1311
                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Set FW Cmd fail!!\n");
1320
1312
}
1321
1313
 
1322
1314
 
1345
1337
 
1346
1338
        switch (rtlhal->current_fwcmd_io) {
1347
1339
        case FW_CMD_RA_RESET:
1348
 
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1349
 
                         ("FW_CMD_RA_RESET\n"));
 
1340
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
1350
1341
                rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1351
1342
                rtl92s_phy_chk_fwcmd_iodone(hw);
1352
1343
                break;
1353
1344
        case FW_CMD_RA_ACTIVE:
1354
 
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1355
 
                         ("FW_CMD_RA_ACTIVE\n"));
 
1345
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
1356
1346
                rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1357
1347
                rtl92s_phy_chk_fwcmd_iodone(hw);
1358
1348
                break;
1359
1349
        case FW_CMD_RA_REFRESH_N:
1360
 
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1361
 
                         ("FW_CMD_RA_REFRESH_N\n"));
 
1350
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
1362
1351
                input = FW_RA_REFRESH;
1363
1352
                rtl_write_dword(rtlpriv, WFM5, input);
1364
1353
                rtl92s_phy_chk_fwcmd_iodone(hw);
1367
1356
                break;
1368
1357
        case FW_CMD_RA_REFRESH_BG:
1369
1358
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1370
 
                         ("FW_CMD_RA_REFRESH_BG\n"));
 
1359
                         "FW_CMD_RA_REFRESH_BG\n");
1371
1360
                rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1372
1361
                rtl92s_phy_chk_fwcmd_iodone(hw);
1373
1362
                rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
1375
1364
                break;
1376
1365
        case FW_CMD_RA_REFRESH_N_COMB:
1377
1366
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1378
 
                         ("FW_CMD_RA_REFRESH_N_COMB\n"));
 
1367
                         "FW_CMD_RA_REFRESH_N_COMB\n");
1379
1368
                input = FW_RA_IOT_N_COMB;
1380
1369
                rtl_write_dword(rtlpriv, WFM5, input);
1381
1370
                rtl92s_phy_chk_fwcmd_iodone(hw);
1382
1371
                break;
1383
1372
        case FW_CMD_RA_REFRESH_BG_COMB:
1384
1373
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1385
 
                         ("FW_CMD_RA_REFRESH_BG_COMB\n"));
 
1374
                         "FW_CMD_RA_REFRESH_BG_COMB\n");
1386
1375
                input = FW_RA_IOT_BG_COMB;
1387
1376
                rtl_write_dword(rtlpriv, WFM5, input);
1388
1377
                rtl92s_phy_chk_fwcmd_iodone(hw);
1389
1378
                break;
1390
1379
        case FW_CMD_IQK_ENABLE:
1391
 
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1392
 
                         ("FW_CMD_IQK_ENABLE\n"));
 
1380
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
1393
1381
                rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
1394
1382
                rtl92s_phy_chk_fwcmd_iodone(hw);
1395
1383
                break;
1424
1412
                rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1425
1413
                break;
1426
1414
        case FW_CMD_LPS_ENTER:
1427
 
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1428
 
                         ("FW_CMD_LPS_ENTER\n"));
 
1415
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
1429
1416
                current_aid = rtlpriv->mac80211.assoc_id;
1430
1417
                rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
1431
1418
                                ((current_aid | 0xc000) << 8)));
1434
1421
                 * turbo mode until driver leave LPS */
1435
1422
                break;
1436
1423
        case FW_CMD_LPS_LEAVE:
1437
 
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1438
 
                         ("FW_CMD_LPS_LEAVE\n"));
 
1424
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
1439
1425
                rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
1440
1426
                rtl92s_phy_chk_fwcmd_iodone(hw);
1441
1427
                break;
1442
1428
        case FW_CMD_ADD_A2_ENTRY:
1443
 
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1444
 
                         ("FW_CMD_ADD_A2_ENTRY\n"));
 
1429
                RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
1445
1430
                rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
1446
1431
                rtl92s_phy_chk_fwcmd_iodone(hw);
1447
1432
                break;
1448
1433
        case FW_CMD_CTRL_DM_BY_DRIVER:
1449
1434
                RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1450
 
                         ("FW_CMD_CTRL_DM_BY_DRIVER\n"));
 
1435
                         "FW_CMD_CTRL_DM_BY_DRIVER\n");
1451
1436
                rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
1452
1437
                rtl92s_phy_chk_fwcmd_iodone(hw);
1453
1438
                break;
1472
1457
        bool bPostProcessing = false;
1473
1458
 
1474
1459
        RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1475
 
                        ("Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1476
 
                        fw_cmdio, rtlhal->set_fwcmd_inprogress));
 
1460
                 "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
 
1461
                 fw_cmdio, rtlhal->set_fwcmd_inprogress);
1477
1462
 
1478
1463
        do {
1479
1464
                /* We re-map to combined FW CMD ones if firmware version */
1501
1486
                 * DM map table in the future. */
1502
1487
                switch (fw_cmdio) {
1503
1488
                case FW_CMD_RA_INIT:
1504
 
                        RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("RA init!!\n"));
 
1489
                        RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
1505
1490
                        fw_cmdmap |= FW_RA_INIT_CTL;
1506
1491
                        FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1507
1492
                        /* Clear control flag to sync with FW. */
1509
1494
                        break;
1510
1495
                case FW_CMD_DIG_DISABLE:
1511
1496
                        RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1512
 
                                 ("Set DIG disable!!\n"));
 
1497
                                 "Set DIG disable!!\n");
1513
1498
                        fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1514
1499
                        FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1515
1500
                        break;
1517
1502
                case FW_CMD_DIG_RESUME:
1518
1503
                        if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1519
1504
                                RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1520
 
                                        ("Set DIG enable or resume!!\n"));
 
1505
                                         "Set DIG enable or resume!!\n");
1521
1506
                                fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
1522
1507
                                FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1523
1508
                        }
1524
1509
                        break;
1525
1510
                case FW_CMD_DIG_HALT:
1526
1511
                        RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1527
 
                                 ("Set DIG halt!!\n"));
 
1512
                                 "Set DIG halt!!\n");
1528
1513
                        fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
1529
1514
                        FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1530
1515
                        break;
1540
1525
                                     (rtlefuse->thermalmeter[0] << 16));
1541
1526
 
1542
1527
                        RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1543
 
                                 ("Set TxPwr tracking!! "
1544
 
                                 "FwCmdMap(%#x), FwParam(%#x)\n",
1545
 
                                 fw_cmdmap, fw_param));
 
1528
                                 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
 
1529
                                 fw_cmdmap, fw_param);
1546
1530
 
1547
1531
                        FW_CMD_PARA_SET(rtlpriv, fw_param);
1548
1532
                        FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1563
1547
                        fw_param &= FW_RA_PARAM_CLR;
1564
1548
 
1565
1549
                        RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1566
 
                                 ("[FW CMD] [New Version] "
1567
 
                                 "Set RA/IOT Comb in n mode!! FwCmdMap(%#x), "
1568
 
                                 "FwParam(%#x)\n", fw_cmdmap, fw_param));
 
1550
                                 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
 
1551
                                 fw_cmdmap, fw_param);
1569
1552
 
1570
1553
                        FW_CMD_PARA_SET(rtlpriv, fw_param);
1571
1554
                        FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1635
1618
                        break;
1636
1619
                case FW_CMD_HIGH_PWR_ENABLE:
1637
1620
                        if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
1638
 
                                (rtlpriv->dm.dynamic_txpower_enable != true)) {
 
1621
                            !rtlpriv->dm.dynamic_txpower_enable) {
1639
1622
                                fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL |
1640
1623
                                              FW_SS_CTL);
1641
1624
                                FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1652
1635
                        break;
1653
1636
                case FW_CMD_PAPE_CONTROL:
1654
1637
                        RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1655
 
                                 ("[FW CMD] Set PAPE Control\n"));
 
1638
                                 "[FW CMD] Set PAPE Control\n");
1656
1639
                        fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
1657
1640
 
1658
1641
                        FW_CMD_IO_SET(rtlpriv, fw_cmdmap);