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#define sync_cache_w(ptr) __sync_cache_range_w(ptr, sizeof *(ptr))
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#define sync_cache_r(ptr) __sync_cache_range_r(ptr, sizeof *(ptr))
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* Disabling cache access for one CPU in an ARMv7 SMP system is tricky.
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* - Clear the SCTLR.C bit to prevent further cache allocations
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* - Flush the desired level of cache
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* - Clear the ACTLR "SMP" bit to disable local coherency
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* ... and so without any intervening memory access in between those steps,
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* not even to the stack.
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* WARNING -- After this has been called:
451
* - No ldrex/strex (and similar) instructions must be used.
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* - The CPU is obviously no longer coherent with the other CPUs.
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* - This is unlikely to work as expected if Linux is running non-secure.
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* - This is known to apply to several ARMv7 processor implementations,
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* however some exceptions may exist. Caveat emptor.
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* - The clobber list is dictated by the call to v7_flush_dcache_*.
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* fp is preserved to the stack explicitly prior disabling the cache
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* since adding it to the clobber list is incompatible with having
463
* CONFIG_FRAME_POINTER=y. ip is saved as well if ever r12-clobbering
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* trampoline are inserted by the linker and to keep sp 64-bit aligned.
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#define v7_exit_coherency_flush(level) \
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"stmfd sp!, {fp, ip} \n\t" \
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"mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \
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"bic r0, r0, #"__stringify(CR_C)" \n\t" \
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"mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \
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"bl v7_flush_dcache_"__stringify(level)" \n\t" \
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"mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \
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"bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \
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"mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \
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"ldmfd sp!, {fp, ip}" \
481
: : : "r0","r1","r2","r3","r4","r5","r6","r7", \
482
"r9","r10","lr","memory" )
added
removed
arch/arm/include/asm/cacheflush.h
