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/* UltraSPARC 64 mpn_modexact_1c_odd -- mpn by limb exact style remainder.
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THE FUNCTIONS IN THIS FILE ARE FOR INTERNAL USE ONLY. THEY'RE ALMOST
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CERTAIN TO BE SUBJECT TO INCOMPATIBLE CHANGES OR DISAPPEAR COMPLETELY IN
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FUTURE GNU MP RELEASES.
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Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2.1 of the License, or (at your
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option) any later version.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with the GNU MP Library; see the file COPYING.LIB. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "mpn/sparc64/sparc64.h"
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/* 64-bit divisor 32-bit divisor
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cycles/limb cycles/limb
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/* This implementation reduces the number of multiplies done, knowing that
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on ultrasparc 1 and 2 the mulx instruction stalls the whole chip.
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The key idea is to use the fact that the low limb of q*d equals l, this
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being the whole purpose of the q calculated. It means there's no need to
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calculate the lowest 32x32->64 part of the q*d, instead it can be
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inferred from l and the other three 32x32->64 parts. See sparc64.h for
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When d is 32-bits, the same applies, but in this case there's only one
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other 32x32->64 part (ie. HIGH(q)*d).
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The net effect is that for 64-bit divisor each limb is 4 mulx, or for
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32-bit divisor each is 2 mulx.
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No doubt this could be done in assembler, if that helped the scheduling,
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or perhaps guaranteed good code irrespective of the compiler.
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It might be possibly to use floating point. The loop is dominated by
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multiply latency, so not sure if floats would improve that. One
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possibility would be to take two limbs at a time, with a 128 bit inverse,
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if there's enough registers, which could effectively use float throughput
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to reduce total latency across two limbs. */
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#define ASSERT_RETVAL(r) \
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ASSERT (orig_c < d ? r < d : r <= d)
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mpn_modexact_1c_odd (mp_srcptr src, mp_size_t size, mp_limb_t d, mp_limb_t orig_c)
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mp_limb_t s, l, q, h, inverse;
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ASSERT_MPN (src, size);
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/* udivx is faster than 10 or 12 mulx's for one limb via an inverse */
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modlimb_invert (inverse, d);
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SUBC_LIMB (c, l, s, c);
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umul_ppmm_half_lowequal (h, q, d, l);
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/* With high s <= d the final step can be a subtract and addback.
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If c==0 then the addback will restore to l>=0. If c==d then
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will get l==d if s==0, but that's ok per the function
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l += (l > c ? d : 0);
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/* Can't skip a divide, just do the loop code once more. */
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SUBC_LIMB (c, l, s, c);
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umul_ppmm_half_lowequal (h, q, d, l);
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mp_limb_t dl = LOW32 (d);
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mp_limb_t dh = HIGH32 (d);
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SUBC_LIMB (c, l, s, c);
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umul_ppmm_lowequal (h, q, d, dh, dl, l);
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/* With high s <= d the final step can be a subtract and addback.
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If c==0 then the addback will restore to l>=0. If c==d then
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will get l==d if s==0, but that's ok per the function
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l += (l > c ? d : 0);
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/* Can't skip a divide, just do the loop code once more. */
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SUBC_LIMB (c, l, s, c);
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umul_ppmm_lowequal (h, q, d, dh, dl, l);
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removed
src/gmp/mpn/sparc64/mode1o.c
