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/* Copyright (c) 2007, Google Inc.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following disclaimer
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* in the documentation and/or other materials provided with the
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* * Neither the name of Google Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* Author: Mike Burrows
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* This module gets enough CPU information to optimize the
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* atomicops module on x86.
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#include "base/atomicops.h"
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#include "base/basictypes.h"
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#include "base/googleinit.h"
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#include "base/logging.h"
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// This file only makes sense with atomicops-internals-x86.h -- it
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// depends on structs that are defined in that file. If atomicops.h
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// doesn't sub-include that file, then we aren't needed, and shouldn't
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// try to do anything.
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#ifdef BASE_ATOMICOPS_INTERNALS_X86_H_
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// Inline cpuid instruction. In PIC compilations, %ebx contains the address
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// of the global offset table. To avoid breaking such executables, this code
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// must preserve that register's value across cpuid instructions.
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#define cpuid(a, b, c, d, inp) \
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asm ("mov %%ebx, %%edi\n" \
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"xchg %%edi, %%ebx\n" \
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: "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
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#elif defined (__x86_64__)
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#define cpuid(a, b, c, d, inp) \
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asm ("mov %%rbx, %%rdi\n" \
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"xchg %%rdi, %%rbx\n" \
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: "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
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#if defined(cpuid) // initialize the struct only on x86
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// Set the flags so that code will run correctly and conservatively
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// until InitGoogle() is called.
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struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
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false, // bug can't exist before process spawns multiple threads
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false, // no cmpxchg16b
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// Initialize the AtomicOps_Internalx86CPUFeatures struct.
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static void AtomicOps_Internalx86CPUFeaturesInit() {
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// Get vendor string (issue CPUID with eax = 0)
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cpuid(eax, ebx, ecx, edx, 0);
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memcpy(vendor, &ebx, 4);
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memcpy(vendor + 4, &edx, 4);
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memcpy(vendor + 8, &ecx, 4);
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// get feature flags in ecx/edx, and family/model in eax
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cpuid(eax, ebx, ecx, edx, 1);
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int family = (eax >> 8) & 0xf; // family and model fields
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int model = (eax >> 4) & 0xf;
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if (family == 0xf) { // use extended family and model fields
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family += (eax >> 20) & 0xff;
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model += ((eax >> 16) & 0xf) << 4;
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// Opteron Rev E has a bug in which on very rare occasions a locked
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// instruction doesn't act as a read-acquire barrier if followed by a
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// non-locked read-modify-write instruction. Rev F has this bug in
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// pre-release versions, but not in versions released to customers,
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// so we test only for Rev E, which is family 15, model 32..63 inclusive.
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if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD
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32 <= model && model <= 63) {
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AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true;
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AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
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// edx bit 26 is SSE2 which we use to tell use whether we can use mfence
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AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
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// ecx bit 13 indicates whether the cmpxchg16b instruction is supported
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AtomicOps_Internalx86CPUFeatures.has_cmpxchg16b = ((ecx >> 13) & 1);
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REGISTER_MODULE_INITIALIZER(atomicops_x86, {
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AtomicOps_Internalx86CPUFeaturesInit();
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#endif /* ifdef BASE_ATOMICOPS_INTERNALS_X86_H_ */