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- Committer: Bazaar Package Importer
- Author(s): Fernando Sanchez
- Date: 2001-01-24 14:05:34 UTC
- Revision ID: james.westby@ubuntu.com-20010124140534-3le9wmofforjjcd8
Tags: upstream-6.3
Import upstream version 6.3
- files added:
- Documentation
- Tests
added
removed
inst.h
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/* SPIM S20 MIPS simulator.
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Description of a SPIM S20 instruction.
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Copyright (C) 1990-2000 by James Larus (larus@cs.wisc.edu).
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ALL RIGHTS RESERVED.
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SPIM is distributed under the following conditions:
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You may make copies of SPIM for your own use and modify those copies.
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All copies of SPIM must retain my name and copyright notice.
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You may not sell SPIM or distributed SPIM in conjunction with a
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commerical product or service without the expressed written consent of
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James Larus.
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THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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PURPOSE. */
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/* $Header: /Software/SPIM/src/inst.h 7 12/24/00 1:37p Larus $
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*/
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/* Describes an expression that produce a value for an instruction's
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immediate field. Immediates have the form: label +/- offset. */
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typedef struct immexpr
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{
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int offset; /* Offset from symbol */
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struct lab *symbol; /* Symbolic label */
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short bits; /* > 0 => 31..16, < 0 => 15..0 */
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short pc_relative; /* Non-zero => offset from label in code */
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} imm_expr;
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/* Describes an expression that produce an address for an instruction.
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Address have the form: label +/- offset (register). */
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typedef struct addrexpr
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{
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unsigned char reg_no; /* Register number */
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imm_expr *imm; /* The immediate part */
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} addr_expr;
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/* Store the instruction fields in an overlapping manner similar to
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the real encoding. */
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typedef struct inst_s
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{
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short opcode;
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union
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{
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/* R-type or I-type: */
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struct
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{
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unsigned char rs;
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unsigned char rt;
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union
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{
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short imm;
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struct
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{
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unsigned char rd;
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unsigned char shamt;
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} r;
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} r_i;
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} r_i;
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/* J-type: */
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mem_addr target;
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} r_t;
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uint32 encoding;
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imm_expr *expr;
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char *source_line;
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} instruction;
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#define OPCODE(INST) (INST)->opcode
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#define SET_OPCODE(INST, VAL) (INST)->opcode = (short)(VAL)
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#define RS(INST) (INST)->r_t.r_i.rs
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#define SET_RS(INST, VAL) (INST)->r_t.r_i.rs = (unsigned char)(VAL)
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#define FS(INST) RS(INST)
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#define SET_FS(INST, VAL) SET_RS(INST, VAL)
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#define BASE(INST) RS(INST)
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#define SET_BASE(INST, VAL) SET_RS(INST, VAL)
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#define RT(INST) (INST)->r_t.r_i.rt
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#define SET_RT(INST, VAL) (INST)->r_t.r_i.rt = (unsigned char)(VAL)
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#define FT(INST) RT(INST)
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#define SET_FT(INST, VAL) SET_RT(INST, VAL)
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#define RD(INST) (INST)->r_t.r_i.r_i.r.rd
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#define SET_RD(INST, VAL) (INST)->r_t.r_i.r_i.r.rd = (unsigned char)(VAL)
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#define FD(INST) RD(INST)
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#define SET_FD(INST, VAL) SET_RD(INST, VAL)
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#define SHAMT(INST) (INST)->r_t.r_i.r_i.r.shamt
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#define SET_SHAMT(INST, VAL)(INST)->r_t.r_i.r_i.r.shamt = (unsigned char)(VAL)
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#define IMM(INST) (INST)->r_t.r_i.r_i.imm
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#define SET_IMM(INST, VAL) (INST)->r_t.r_i.r_i.imm = (short)(VAL)
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#define IOFFSET(INST) IMM(INST)
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#define SET_IOFFSET(INST, VAL) SET_IMM(INST, VAL)
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#define IDISP(INST) (SIGN_EX (IOFFSET (INST) << 2))
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#define COND(INST) IMM(INST)
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#define SET_COND(INST, VAL) SET_IMM(INST, VAL)
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#define TARGET(INST) (INST)->r_t.target
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#define SET_TARGET(INST, VAL) (INST)->r_t.target = (mem_addr)(VAL)
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#define ENCODING(INST) (INST)->encoding
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#define SET_ENCODING(INST, VAL) (INST)->encoding = (uint32)(VAL)
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#define EXPR(INST) (INST)->expr
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#define SET_EXPR(INST, VAL) (INST)->expr = (imm_expr*)(VAL)
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#define SOURCE(INST) (INST)->source_line
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#define SET_SOURCE(INST, VAL) (INST)->source_line = (char *)(VAL)
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#define COND_UN 0x1
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#define COND_EQ 0x2
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#define COND_LT 0x4
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#define COND_IN 0x8
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/* Minimum and maximum values that fit in instruction's imm field */
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#define IMM_MIN -(1<<15)
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#define IMM_MAX ((1<<15)-1)
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#define UIMM_MIN 0
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#define UIMM_MAX ((1<<16)-1)
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/* Raise an exception! */
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#define RAISE_EXCEPTION(CAUSE, MISC) \
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{ \
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if (((CAUSE)<= LAST_REAL_EXCEPT) || (Status_Reg & 0x1)) \
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{ \
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Cause = (CAUSE) << 2; \
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exception_occurred = 1; \
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EPC = PC; \
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Status_Reg = (Status_Reg & 0xffffffc0) | ((Status_Reg & 0xf) << 2); \
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MISC; \
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} \
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} \
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/* Recognized exceptions (see Ch. 5): */
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#define INT_EXCPT 0
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#define MOD_EXCPT 1
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#define TLBL_EXCPT 2
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#define TLBS_EXCPT 3
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#define ADDRL_EXCPT 4
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#define ADDRS_EXCPT 5
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#define IBUS_EXCPT 6
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#define DBUS_EXCPT 7
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#define SYSCALL_EXCPT 8
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#define BKPT_EXCPT 9
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#define RI_EXCPT 10
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#define CPU_EXCPT 11
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#define OVF_EXCPT 12
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#define CACHEABLE 13
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#define NOT_CACHEABLE 14
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/* Floating point exceptions (Ch. 8): */
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#define INEXACT_EXCEPT 13
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#define INVALID_EXCEPT 14
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#define DIV0_EXCEPT 15
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#define FOVF_EXCEPT 16
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#define FUNF_EXCEPT 17
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#define LAST_REAL_EXCEPT FUNF_EXCEPT
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/* Exported functions: */
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#ifdef __STDC__
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imm_expr *addr_expr_imm (addr_expr *expr);
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int addr_expr_reg (addr_expr *expr);
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imm_expr *const_imm_expr (int32 value);
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imm_expr *copy_imm_expr (imm_expr *old_expr);
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instruction *copy_inst (instruction *inst);
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mem_addr current_text_pc (void);
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int32 eval_imm_expr (imm_expr *expr);
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void free_inst (instruction *inst);
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void i_type_inst (int opcode, int rt, int rs, imm_expr *expr);
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void i_type_inst_free (int opcode, int rt, int rs, imm_expr *expr);
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void increment_text_pc (int delta);
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imm_expr *incr_expr_offset (imm_expr *expr, int32 value);
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instruction *inst_decode (uint32 value);
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int32 inst_encode (instruction *inst);
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int inst_is_breakpoint (mem_addr addr);
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void j_type_inst (int opcode, imm_expr *target);
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void k_text_begins_at_point (mem_addr addr);
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imm_expr *lower_bits_of_expr (imm_expr *old_expr);
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addr_expr *make_addr_expr (int offs, char *sym, int reg_no);
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imm_expr *make_imm_expr (int offs, char *sym, int pc_rel);
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int opcode_is_branch (int opcode);
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int opcode_is_jump (int opcode);
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int opcode_is_load_store (int opcode);
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void print_inst (mem_addr addr);
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int print_inst_internal (char *buf, int len, instruction *inst, mem_addr addr);
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void r_cond_type_inst (int opcode, int rs, int rt);
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void r_sh_type_inst (int opcode, int rd, int rt, int shamt);
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void r_type_inst (int opcode, int rd, int rs, int rt);
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instruction *set_breakpoint (mem_addr addr);
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void store_instruction (instruction *inst);
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void text_begins_at_point (mem_addr addr);
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imm_expr *upper_bits_of_expr (imm_expr *old_expr);
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void user_kernel_text_segment (int to_kernel);
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int zero_imm (imm_expr *expr);
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#else
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imm_expr *addr_expr_imm ();
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int addr_expr_reg ();
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imm_expr *const_imm_expr ();
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imm_expr *copy_imm_expr ();
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instruction *copy_inst ();
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mem_addr current_text_pc ();
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int32 eval_imm_expr ();
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void free_inst ();
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void i_type_inst ();
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void i_type_inst_free ();
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void increment_text_pc ();
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imm_expr *incr_expr_offset ();
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instruction *inst_decode ();
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int32 inst_encode ();
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int inst_is_breakpoint ();
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void j_type_inst ();
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void k_text_begins_at_point ();
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imm_expr *lower_bits_of_expr ();
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addr_expr *make_addr_expr ();
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imm_expr *make_imm_expr ();
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int opcode_is_branch ();
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int opcode_is_jump ();
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int opcode_is_load_store ();
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void print_inst ();
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int print_inst_internal ();
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void r_cond_type_inst ();
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void r_sh_type_inst ();
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void r_type_inst ();
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instruction *set_breakpoint ();
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void store_instruction ();
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void text_begins_at_point ();
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imm_expr *upper_bits_of_expr ();
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void user_kernel_text_segment ();
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int zero_imm ();
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#endif
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