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/* SPIM S20 MIPS simulator.
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Declarations of registers and code for accessing them.
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Copyright (C) 1990-2000 by James Larus (larus@cs.wisc.edu).
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SPIM is distributed under the following conditions:
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You may make copies of SPIM for your own use and modify those copies.
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All copies of SPIM must retain my name and copyright notice.
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You may not sell SPIM or distributed SPIM in conjunction with a
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commerical product or service without the expressed written consent of
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THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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/* $Header: /Software/SPIM/src/reg.h 4 12/24/00 1:37p Larus $
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typedef int32 reg_word;
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typedef uint32 u_reg_word;
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/* General purpose registers: */
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extern reg_word R[32];
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extern reg_word HI, LO;
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extern mem_addr PC, nPC;
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/* Argument passing registers */
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/* Result registers */
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/* Floating Point Coprocessor (1) registers :*/
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extern double *FPR; /* Dynamically allocate so overlay */
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extern float *FGR; /* is possible */
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extern int *FWR; /* is possible */
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extern int FP_reg_present; /* Presence bits for FP registers */
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extern int FP_reg_poison; /* Poison bits for FP registers */
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extern int FP_spec_load; /* Is register waiting for a speculative load */
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#define FPR_S(REGNO) (FGR[REGNO])
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#define FPR_D(REGNO) (double) (((REGNO) & 0x1) \
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? (run_error ("Bit 0 in FP double reg\n") ? 0.0 : 0.0)\
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#define FPR_W(REGNO) (FWR[REGNO])
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#define SET_FPR_S(REGNO, VALUE) {FGR[REGNO] = (float) (VALUE);}
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#define SET_FPR_D(REGNO, VALUE) {if ((REGNO) & 0x1) \
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run_error ("Bit 0 in FP double reg\n");\
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else FPR[(REGNO) >> 1] = (double) (VALUE);}
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#define SET_FPR_W(REGNO, VALUE) {FWR[REGNO] = (int) (VALUE);}
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/* Floating point control and condition registers: */
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#define FPId (CPR[1][0])
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#define FpCond (CPR[1][31])
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/* Other Coprocessor Registers. The floating point registers
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(coprocessor 1) are above. */
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extern reg_word CpCond[4], CCR[4][32], CPR[4][32];
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/* Exeception Handling Registers (actually registers in Coprocoessor
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0's register file) */
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extern int exception_occurred;
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#define EntryHI (CPR[0][0])
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#define EntryLO (CPR[0][1])
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#define Index (CPR[0][2])
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#define Random (CPR[0][3])
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#define Context (CPR[0][4])
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#define BadVAddr (CPR[0][8])
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#define Status_Reg (CPR[0][12])
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#define Cause (CPR[0][13])
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#define EPC (CPR[0][14])
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#define PRId (CPR[0][15])
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#define USER_MODE (Status_Reg & 0x2)
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#define INTERRUPTS_ON (Status_Reg & 0x1)
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reg.h
