283
287
Support for systems based on the DC21285 companion chip
284
288
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
291
bool "Freescale MXC/iMX-based"
293
select GENERIC_CLOCKEVENTS
296
select ARCH_REQUIRE_GPIOLIB
299
Support for Freescale MXC/iMX-based family of processors
302
bool "Freescale STMP3xxx"
306
select ARCH_REQUIRE_GPIOLIB
308
select GENERIC_CLOCKEVENTS
310
select USB_ARCH_HAS_EHCI
312
Support for systems based on the Freescale 3xxx CPUs.
287
315
bool "Hilscher NetX based"
288
316
select CPU_ARM926T
395
415
Support for the following Marvell Kirkwood series SoCs:
396
416
88F6180, 88F6192 and 88F6281.
399
bool "Micrel/Kendin KS8695"
402
select ARCH_REQUIRE_GPIOLIB
404
Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
405
System-on-Chip devices.
408
bool "NetSilicon NS9xxx"
412
select GENERIC_CLOCKEVENTS
415
Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
418
<http://www.digi.com/products/microprocessors/index.jsp>
421
419
bool "Marvell Loki (88RC8480)"
422
420
select CPU_FEROCEON
438
437
Support for the following Marvell MV78xx0 series SoCs:
439
438
MV781x0, MV782x0.
442
bool "Freescale MXC/iMX-based"
444
select GENERIC_CLOCKEVENTS
447
select ARCH_REQUIRE_GPIOLIB
449
Support for Freescale MXC/iMX-based family of processors
451
440
config ARCH_ORION5X
452
441
bool "Marvell Orion"
454
443
select CPU_FEROCEON
456
445
select GENERIC_GPIO
446
select ARCH_REQUIRE_GPIOLIB
457
447
select GENERIC_TIME
458
448
select GENERIC_CLOCKEVENTS
459
449
select PLAT_ORION
462
452
Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
463
453
Orion-2 (5281), Orion-1-90 (6183).
456
bool "Marvell PXA168/910"
459
select ARCH_REQUIRE_GPIOLIB
463
select GENERIC_CLOCKEVENTS
467
Support for Marvell's PXA168/910 processor line.
470
bool "Micrel/Kendin KS8695"
473
select ARCH_REQUIRE_GPIOLIB
475
Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
476
System-on-Chip devices.
479
bool "NetSilicon NS9xxx"
483
select GENERIC_CLOCKEVENTS
486
Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
489
<http://www.digi.com/products/microprocessors/index.jsp>
492
bool "Nuvoton W90X900 CPU"
494
select ARCH_REQUIRE_GPIOLIB
498
Support for Nuvoton (Winbond logic dept.) ARM9 processor,You
499
can login www.mcuos.com or www.nuvoton.com to know more.
465
501
config ARCH_PNX4008
466
502
bool "Philips Nexperia PNX4008 Mobile"
467
503
select CPU_ARM926T
480
516
select GENERIC_TIME
481
517
select GENERIC_CLOCKEVENTS
482
518
select TICK_ONESHOT
484
521
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
527
select GENERIC_CLOCKEVENTS
529
Support for Qualcomm MSM7K based systems. This runs on the ARM11
530
apps processor of the MSM7K and depends on a shared memory
531
interface to the ARM9 modem processor which runs the baseband stack
532
and controls some vital subsystems (clock and power control, etc).
488
536
select ARCH_ACORN
550
598
core with a wide array of integrated devices for
551
599
hand-held and low-power applications.
602
bool "ST-Ericsson U300 Series"
608
select GENERIC_CLOCKEVENTS
613
Support for ST-Ericsson U300 series mobile platforms.
553
615
config ARCH_DAVINCI
554
616
bool "TI DaVinci"
555
617
select CPU_ARM926T
573
638
Support for TI's OMAP platform (OMAP1 and OMAP2).
579
select GENERIC_CLOCKEVENTS
581
Support for Qualcomm MSM7K based systems. This runs on the ARM11
582
apps processor of the MSM7K and depends on a shared memory
583
interface to the ARM9 modem processor which runs the baseband stack
584
and controls some vital subsystems (clock and power control, etc).
587
bool "Nuvoton W90X900 CPU"
590
Support for Nuvoton (Winbond logic dept.) ARM9 processor,You
591
can login www.mcuos.com or www.nuvoton.com to know more.
595
642
source "arch/arm/mach-clps711x/Kconfig"
617
666
source "arch/arm/mach-mv78xx0/Kconfig"
619
668
source "arch/arm/mach-pxa/Kconfig"
669
source "arch/arm/plat-pxa/Kconfig"
671
source "arch/arm/mach-mmp/Kconfig"
621
673
source "arch/arm/mach-sa1100/Kconfig"
648
700
source "arch/arm/mach-s3c6410/Kconfig"
703
source "arch/arm/plat-stmp3xxx/Kconfig"
651
705
source "arch/arm/mach-lh7a40x/Kconfig"
653
source "arch/arm/mach-imx/Kconfig"
655
707
source "arch/arm/mach-h720x/Kconfig"
657
709
source "arch/arm/mach-versatile/Kconfig"
686
740
config PLAT_ORION
689
746
source arch/arm/mm/Kconfig
692
749
bool "Enable iWMMXt support"
693
depends on CPU_XSCALE || CPU_XSC3
694
default y if PXA27x || PXA3xx
750
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
751
default y if PXA27x || PXA3xx || ARCH_MMP
696
753
Enable support for iWMMXt context switching at run time if
697
754
running on a CPU that supports it.
706
763
source "arch/arm/Kconfig-nommu"
766
config ARM_ERRATA_411920
767
bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
768
depends on CPU_V6 && !SMP
770
Invalidation of the Instruction Cache operation can
771
fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
772
It does not affect the MPCore. This option enables the ARM Ltd.
773
recommended workaround.
775
config ARM_ERRATA_430973
776
bool "ARM errata: Stale prediction on replaced interworking branch"
779
This option enables the workaround for the 430973 Cortex-A8
780
(r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
781
interworking branch is replaced with another code sequence at the
782
same virtual address, whether due to self-modifying code or virtual
783
to physical address re-mapping, Cortex-A8 does not recover from the
784
stale interworking branch prediction. This results in Cortex-A8
785
executing the new code sequence in the incorrect ARM or Thumb state.
786
The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
787
and also flushes the branch target cache at every context switch.
788
Note that setting specific bits in the ACTLR register may not be
789
available in non-secure mode.
791
config ARM_ERRATA_458693
792
bool "ARM errata: Processor deadlock when a false hazard is created"
795
This option enables the workaround for the 458693 Cortex-A8 (r2p0)
796
erratum. For very specific sequences of memory operations, it is
797
possible for a hazard condition intended for a cache line to instead
798
be incorrectly associated with a different cache line. This false
799
hazard might then cause a processor deadlock. The workaround enables
800
the L1 caching of the NEON accesses and disables the PLD instruction
801
in the ACTLR register. Note that setting specific bits in the ACTLR
802
register may not be available in non-secure mode.
804
config ARM_ERRATA_460075
805
bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
808
This option enables the workaround for the 460075 Cortex-A8 (r2p0)
809
erratum. Any asynchronous access to the L2 cache may encounter a
810
situation in which recent store transactions to the L2 cache are lost
811
and overwritten with stale memory contents from external memory. The
812
workaround disables the write-allocate mode for the L2 cache via the
813
ACTLR register. Note that setting specific bits in the ACTLR register
814
may not be available in non-secure mode.
711
818
source "arch/arm/common/Kconfig"
775
882
bool "Symmetric Multi-Processing (EXPERIMENTAL)"
776
depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP)
883
depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
884
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
885
depends on GENERIC_CLOCKEVENTS
777
886
select USE_GENERIC_SMP_HELPERS
887
select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4)
779
889
This enables support for systems with more than one CPU. If you have
780
890
a system with only one CPU, like most personal computers, say N. If
831
953
config LOCAL_TIMERS
832
954
bool "Use local timer interrupts"
833
depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || REALVIEW_EB_A9MP)
955
depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
956
REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
958
select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4)
836
960
Enable support for local timers on SMP platforms, rather then the
837
961
legacy IPI broadcast method. Local timers allows the system
891
1015
UNPREDICTABLE (in fact it can be predicted that it won't work
892
1016
at all). If in doubt say Y.
894
config ARCH_FLATMEM_HAS_HOLES
1018
config ARCH_HAS_HOLES_MEMORYMODEL
899
1021
# Discontigmem is deprecated
900
1022
config ARCH_DISCONTIGMEM_ENABLE
916
1038
depends on NEED_MULTIPLE_NODES
1041
bool "High Memory Support (EXPERIMENTAL)"
1042
depends on MMU && EXPERIMENTAL
1044
The address space of ARM processors is only 4 Gigabytes large
1045
and it has to accommodate user address space, kernel address
1046
space as well as some memory mapped IO. That means that, if you
1047
have a large amount of physical memory and/or IO, not all of the
1048
memory can be "permanently mapped" by the kernel. The physical
1049
memory that is not permanently mapped is called "high memory".
1051
Depending on the selected kernel/user memory split, minimum
1052
vmalloc space and actual amount of RAM, you may not need this
1053
option which should result in a slightly faster kernel.
918
1057
source "mm/Kconfig"
921
1060
bool "Timer and CPU usage LEDs"
922
1061
depends on ARCH_CDB89712 || ARCH_EBSA110 || \
923
ARCH_EBSA285 || ARCH_IMX || ARCH_INTEGRATOR || \
1062
ARCH_EBSA285 || ARCH_INTEGRATOR || \
924
1063
ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
925
1064
ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
926
1065
ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
927
1066
ARCH_AT91 || ARCH_DAVINCI || \
928
ARCH_KS8695 || MACH_RD88F5182
1067
ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
930
1069
If you say Y here, the LEDs on your machine will be used
931
1070
to provide useful information about your current system status.
983
1122
correct operation of some network protocols. With an IP-only
984
1123
configuration it is safe to say N, otherwise say Y.
1125
config UACCESS_WITH_MEMCPY
1126
bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1127
depends on MMU && EXPERIMENTAL
1128
default y if CPU_FEROCEON
1130
Implement faster copy_to_user and clear_user methods for CPU
1131
cores where a 8-word STM instruction give significantly higher
1132
memory write throughput than a sequence of individual 32bit stores.
1134
A possible side effect is a slight increase in scheduling latency
1135
between threads sharing the same address space if they invoke
1136
such copy operations with large buffers.
1138
However, if the CPU data cache is using a write-allocate mode,
1139
this option is unlikely to provide any performance gain.
988
1143
menu "Boot options"
1087
1242
menu "CPU Power Management"
1089
if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
1244
if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA || ARCH_S3C64XX)
1091
1246
source "drivers/cpufreq/Kconfig"
1093
1248
config CPU_FREQ_SA1100
1095
depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_H3800 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT)
1250
depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT)
1098
1253
config CPU_FREQ_SA1110
1112
1267
If in doubt, say Y.
1115
tristate "CPUfreq driver for i.MX CPUs"
1116
depends on ARCH_IMX && CPU_FREQ
1119
This enables the CPUfreq driver for i.MX CPUs.
1123
1269
config CPU_FREQ_PXA
1125
1271
depends on CPU_FREQ && ARCH_PXA && PXA25x
1127
1273
select CPU_FREQ_DEFAULT_GOV_USERSPACE
1275
config CPU_FREQ_S3C64XX
1276
bool "CPUfreq support for Samsung S3C64XX CPUs"
1277
depends on CPU_FREQ && CPU_S3C6410
1131
1281
source "drivers/cpuidle/Kconfig"
added
removed
arch/arm/Kconfig
