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* drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
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* Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/highmem.h>
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#include <linux/delay.h>
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#include <linux/mmc/host.h>
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#define DRV_NAME "via_sdmmc"
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#define PCI_DEVICE_ID_VIA_9530 0x9530
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#define VIA_CRDR_SDC_OFF 0x200
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#define VIA_CRDR_DDMA_OFF 0x400
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#define VIA_CRDR_PCICTRL_OFF 0x600
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#define VIA_CRDR_MIN_CLOCK 375000
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#define VIA_CRDR_MAX_CLOCK 48000000
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#define VIA_CRDR_PCI_WORK_MODE 0x40
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#define VIA_CRDR_PCI_DBG_MODE 0x41
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#define VIA_CRDR_SDCTRL 0x0
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#define VIA_CRDR_SDCTRL_START 0x01
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#define VIA_CRDR_SDCTRL_WRITE 0x04
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#define VIA_CRDR_SDCTRL_SINGLE_WR 0x10
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#define VIA_CRDR_SDCTRL_SINGLE_RD 0x20
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#define VIA_CRDR_SDCTRL_MULTI_WR 0x30
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#define VIA_CRDR_SDCTRL_MULTI_RD 0x40
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#define VIA_CRDR_SDCTRL_STOP 0x70
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#define VIA_CRDR_SDCTRL_RSP_NONE 0x0
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#define VIA_CRDR_SDCTRL_RSP_R1 0x10000
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#define VIA_CRDR_SDCTRL_RSP_R2 0x20000
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#define VIA_CRDR_SDCTRL_RSP_R3 0x30000
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#define VIA_CRDR_SDCTRL_RSP_R1B 0x90000
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#define VIA_CRDR_SDCARG 0x4
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#define VIA_CRDR_SDBUSMODE 0x8
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#define VIA_CRDR_SDMODE_4BIT 0x02
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#define VIA_CRDR_SDMODE_CLK_ON 0x40
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#define VIA_CRDR_SDBLKLEN 0xc
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* Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
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* Bit 11 - Bit 13 : Reserved.
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* GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
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* INTEN : Enable SD host interrupt.
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* Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
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#define VIA_CRDR_SDBLKLEN_GPIDET 0x2000
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#define VIA_CRDR_SDBLKLEN_INTEN 0x8000
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#define VIA_CRDR_MAX_BLOCK_COUNT 65536
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#define VIA_CRDR_MAX_BLOCK_LENGTH 2048
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#define VIA_CRDR_SDRESP0 0x10
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#define VIA_CRDR_SDRESP1 0x14
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#define VIA_CRDR_SDRESP2 0x18
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#define VIA_CRDR_SDRESP3 0x1c
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#define VIA_CRDR_SDCURBLKCNT 0x20
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#define VIA_CRDR_SDINTMASK 0x24
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* MBDIE : Multiple Blocks transfer Done Interrupt Enable
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* BDDIE : Block Data transfer Done Interrupt Enable
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* CIRIE : Card Insertion or Removal Interrupt Enable
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* CRDIE : Command-Response transfer Done Interrupt Enable
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* CRTOIE : Command-Response response TimeOut Interrupt Enable
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* ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
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* DTIE : Data access Timeout Interrupt Enable
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* SCIE : reSponse CRC error Interrupt Enable
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* RCIE : Read data CRC error Interrupt Enable
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* WCIE : Write data CRC error Interrupt Enable
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#define VIA_CRDR_SDINTMASK_MBDIE 0x10
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#define VIA_CRDR_SDINTMASK_BDDIE 0x20
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#define VIA_CRDR_SDINTMASK_CIRIE 0x80
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#define VIA_CRDR_SDINTMASK_CRDIE 0x200
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#define VIA_CRDR_SDINTMASK_CRTOIE 0x400
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#define VIA_CRDR_SDINTMASK_ASCRDIE 0x800
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#define VIA_CRDR_SDINTMASK_DTIE 0x1000
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#define VIA_CRDR_SDINTMASK_SCIE 0x2000
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#define VIA_CRDR_SDINTMASK_RCIE 0x4000
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#define VIA_CRDR_SDINTMASK_WCIE 0x8000
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#define VIA_CRDR_SDACTIVE_INTMASK \
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(VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
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| VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
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| VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
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| VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
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#define VIA_CRDR_SDSTATUS 0x28
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* WP : SD card Write Protect status
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* SLOTG : SD SLOT status(Gpi pin status)
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* MBD : Multiple Blocks transfer Done interrupt status
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* BDD : Block Data transfer Done interrupt status
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* CIR : Card Insertion or Removal interrupt detected on GPI pin
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* CRD : Command-Response transfer Done interrupt status
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* CRTO : Command-Response response TimeOut interrupt status
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* ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
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* DT : Data access Timeout interrupt status
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* SC : reSponse CRC error interrupt status
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* RC : Read data CRC error interrupt status
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* WC : Write data CRC error interrupt status
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#define VIA_CRDR_SDSTS_CECC 0x01
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#define VIA_CRDR_SDSTS_WP 0x02
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#define VIA_CRDR_SDSTS_SLOTD 0x04
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#define VIA_CRDR_SDSTS_SLOTG 0x08
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#define VIA_CRDR_SDSTS_MBD 0x10
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#define VIA_CRDR_SDSTS_BDD 0x20
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#define VIA_CRDR_SDSTS_CD 0x40
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#define VIA_CRDR_SDSTS_CIR 0x80
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#define VIA_CRDR_SDSTS_IO 0x100
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#define VIA_CRDR_SDSTS_CRD 0x200
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#define VIA_CRDR_SDSTS_CRTO 0x400
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#define VIA_CRDR_SDSTS_ASCRDIE 0x800
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#define VIA_CRDR_SDSTS_DT 0x1000
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#define VIA_CRDR_SDSTS_SC 0x2000
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#define VIA_CRDR_SDSTS_RC 0x4000
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#define VIA_CRDR_SDSTS_WC 0x8000
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#define VIA_CRDR_SDSTS_IGN_MASK\
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(VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
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#define VIA_CRDR_SDSTS_INT_MASK \
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(VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
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| VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
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| VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
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| VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
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#define VIA_CRDR_SDSTS_W1C_MASK \
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(VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
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| VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
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| VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
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| VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
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#define VIA_CRDR_SDSTS_CMD_MASK \
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(VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
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#define VIA_CRDR_SDSTS_DATA_MASK\
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(VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
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| VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
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#define VIA_CRDR_SDSTATUS2 0x2a
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* CFE : Enable SD host automatic Clock FReezing
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#define VIA_CRDR_SDSTS_CFE 0x80
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#define VIA_CRDR_SDRSPTMO 0x2C
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#define VIA_CRDR_SDCLKSEL 0x30
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#define VIA_CRDR_SDEXTCTRL 0x34
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#define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01
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#define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02
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#define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04
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#define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08
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#define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10
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#define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20
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#define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40
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#define VIA_CRDR_SDEXTCTRL_HISPD 0x80
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/* 0x38-0xFF reserved */
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* Data DMA Control Registers
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#define VIA_CRDR_DMABASEADD 0x0
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#define VIA_CRDR_DMACOUNTER 0x4
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#define VIA_CRDR_DMACTRL 0x8
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* DIR :Transaction Direction
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* 0 : From card to memory
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* 1 : From memory to card
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#define VIA_CRDR_DMACTRL_DIR 0x100
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#define VIA_CRDR_DMACTRL_ENIRQ 0x10000
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#define VIA_CRDR_DMACTRL_SFTRST 0x1000000
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#define VIA_CRDR_DMASTS 0xc
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#define VIA_CRDR_DMASTART 0x10
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/*0x14-0xFF reserved*/
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* PCI Control Registers
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/*0x0 - 0x1 reserved*/
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#define VIA_CRDR_PCICLKGATT 0x2
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* 0 : Soft reset all the controller and it will be de-asserted automatically
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* 1 : Soft reset is de-asserted
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#define VIA_CRDR_PCICLKGATT_SFTRST 0x01
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* 3V3 : Pad power select
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* NOTE : No mater what the actual value should be, this bit always
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* read as 0. This is a hardware bug.
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#define VIA_CRDR_PCICLKGATT_3V3 0x10
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* PAD_PWRON : Pad Power on/off select
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* NOTE : No mater what the actual value should be, this bit always
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* read as 0. This is a hardware bug.
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#define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20
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#define VIA_CRDR_PCISDCCLK 0x5
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#define VIA_CRDR_PCIDMACLK 0x7
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#define VIA_CRDR_PCIDMACLK_SDC 0x2
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#define VIA_CRDR_PCIINTCTRL 0x8
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#define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04
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#define VIA_CRDR_PCIINTSTATUS 0x9
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#define VIA_CRDR_PCIINTSTATUS_SDC 0x04
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#define VIA_CRDR_PCITMOCTRL 0xa
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#define VIA_CRDR_PCITMOCTRL_NO 0x0
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#define VIA_CRDR_PCITMOCTRL_32US 0x1
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#define VIA_CRDR_PCITMOCTRL_256US 0x2
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#define VIA_CRDR_PCITMOCTRL_1024US 0x3
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#define VIA_CRDR_PCITMOCTRL_256MS 0x4
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#define VIA_CRDR_PCITMOCTRL_512MS 0x5
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#define VIA_CRDR_PCITMOCTRL_1024MS 0x6
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/*0xB-0xFF reserved*/
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enum PCI_HOST_CLK_CONTROL {
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struct via_crdr_mmc_host {
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struct mmc_host *mmc;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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void __iomem *mmiobase;
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void __iomem *sdhc_mmiobase;
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void __iomem *ddma_mmiobase;
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void __iomem *pcictrl_mmiobase;
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struct pcictrlreg pm_pcictrl_reg;
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struct sdhcreg pm_sdhc_reg;
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struct work_struct carddet_work;
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struct tasklet_struct finish_tasklet;
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struct timer_list timer;
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/* some devices need a very long delay for power to stabilize */
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#define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001
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static struct pci_device_id via_ids[] = {
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{PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
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MODULE_DEVICE_TABLE(pci, via_ids);
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static void via_print_sdchc(struct via_crdr_mmc_host *host)
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void __iomem *addrbase = host->sdhc_mmiobase;
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pr_debug("SDC MMIO Registers:\n");
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pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
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readl(addrbase + VIA_CRDR_SDCTRL),
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readl(addrbase + VIA_CRDR_SDCARG),
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readl(addrbase + VIA_CRDR_SDBUSMODE));
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pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
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readl(addrbase + VIA_CRDR_SDBLKLEN),
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readl(addrbase + VIA_CRDR_SDCURBLKCNT),
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readl(addrbase + VIA_CRDR_SDINTMASK));
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pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
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readl(addrbase + VIA_CRDR_SDSTATUS),
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readl(addrbase + VIA_CRDR_SDCLKSEL),
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readl(addrbase + VIA_CRDR_SDEXTCTRL));
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static void via_print_pcictrl(struct via_crdr_mmc_host *host)
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void __iomem *addrbase = host->pcictrl_mmiobase;
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pr_debug("PCI Control Registers:\n");
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pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
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readb(addrbase + VIA_CRDR_PCICLKGATT),
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readb(addrbase + VIA_CRDR_PCISDCCLK),
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readb(addrbase + VIA_CRDR_PCIDMACLK));
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pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
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readb(addrbase + VIA_CRDR_PCIINTCTRL),
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readb(addrbase + VIA_CRDR_PCIINTSTATUS));
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static void via_save_pcictrlreg(struct via_crdr_mmc_host *host)
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struct pcictrlreg *pm_pcictrl_reg;
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void __iomem *addrbase;
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pm_pcictrl_reg = &(host->pm_pcictrl_reg);
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addrbase = host->pcictrl_mmiobase;
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pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT);
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pm_pcictrl_reg->pciclkgat_reg |=
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VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
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pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK);
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pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK);
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pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL);
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pm_pcictrl_reg->pciintstatus_reg =
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readb(addrbase + VIA_CRDR_PCIINTSTATUS);
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pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL);
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static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host)
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struct pcictrlreg *pm_pcictrl_reg;
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void __iomem *addrbase;
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pm_pcictrl_reg = &(host->pm_pcictrl_reg);
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addrbase = host->pcictrl_mmiobase;
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writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT);
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writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK);
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writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK);
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writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL);
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writeb(pm_pcictrl_reg->pciintstatus_reg,
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addrbase + VIA_CRDR_PCIINTSTATUS);
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writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL);
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static void via_save_sdcreg(struct via_crdr_mmc_host *host)
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struct sdhcreg *pm_sdhc_reg;
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void __iomem *addrbase;
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pm_sdhc_reg = &(host->pm_sdhc_reg);
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addrbase = host->sdhc_mmiobase;
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pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL);
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pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG);
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pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE);
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pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN);
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pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT);
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pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK);
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pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS);
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pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO);
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pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL);
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pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL);
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static void via_restore_sdcreg(struct via_crdr_mmc_host *host)
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struct sdhcreg *pm_sdhc_reg;
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void __iomem *addrbase;
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pm_sdhc_reg = &(host->pm_sdhc_reg);
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addrbase = host->sdhc_mmiobase;
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writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
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writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
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writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
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writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
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writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
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writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
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writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
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writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
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writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
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writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
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static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost)
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if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY)
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static void via_set_ddma(struct via_crdr_mmc_host *host,
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dma_addr_t dmaaddr, u32 count, int dir, int enirq)
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void __iomem *addrbase;
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ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ;
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ctrl_data |= VIA_CRDR_DMACTRL_DIR;
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addrbase = host->ddma_mmiobase;
463
writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
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writel(count, addrbase + VIA_CRDR_DMACOUNTER);
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writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
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writel(0x01, addrbase + VIA_CRDR_DMASTART);
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/* It seems that our DMA can not work normally with 375kHz clock */
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/* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */
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addrbase = host->pcictrl_mmiobase;
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if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) {
472
dev_info(host->mmc->parent, "forcing card speed to 8MHz\n");
473
writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK);
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static void via_sdc_preparedata(struct via_crdr_mmc_host *host,
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struct mmc_data *data)
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void __iomem *addrbase;
487
BUG_ON(data->blksz > host->mmc->max_blk_size);
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BUG_ON(data->blocks > host->mmc->max_blk_count);
492
count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
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((data->flags & MMC_DATA_READ) ?
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PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
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via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg),
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(data->flags & MMC_DATA_WRITE) ? 1 : 0, 1);
500
addrbase = host->sdhc_mmiobase;
502
blk_reg = data->blksz - 1;
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blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
504
blk_reg |= (data->blocks) << 16;
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writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
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static void via_sdc_get_response(struct via_crdr_mmc_host *host,
510
struct mmc_command *cmd)
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void __iomem *addrbase = host->sdhc_mmiobase;
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u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0);
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u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1);
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u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2);
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u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3);
518
if (cmd->flags & MMC_RSP_136) {
519
cmd->resp[0] = ((u8) (dwdata1)) |
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(((u8) (dwdata0 >> 24)) << 8) |
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(((u8) (dwdata0 >> 16)) << 16) |
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(((u8) (dwdata0 >> 8)) << 24);
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cmd->resp[1] = ((u8) (dwdata2)) |
525
(((u8) (dwdata1 >> 24)) << 8) |
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(((u8) (dwdata1 >> 16)) << 16) |
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(((u8) (dwdata1 >> 8)) << 24);
529
cmd->resp[2] = ((u8) (dwdata3)) |
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(((u8) (dwdata2 >> 24)) << 8) |
531
(((u8) (dwdata2 >> 16)) << 16) |
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(((u8) (dwdata2 >> 8)) << 24);
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cmd->resp[3] = 0xff |
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((((u8) (dwdata3 >> 24))) << 8) |
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(((u8) (dwdata3 >> 16)) << 16) |
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(((u8) (dwdata3 >> 8)) << 24);
540
cmd->resp[0] = ((dwdata0 & 0xff) << 24) |
541
(((dwdata0 >> 8) & 0xff) << 16) |
542
(((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff);
545
cmd->resp[1] = ((dwdata1 & 0xff) << 24) |
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(((dwdata1 >> 8) & 0xff) << 16) |
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(((dwdata1 >> 16) & 0xff) << 8);
551
static void via_sdc_send_command(struct via_crdr_mmc_host *host,
552
struct mmc_command *cmd)
554
void __iomem *addrbase;
555
struct mmc_data *data;
561
mod_timer(&host->timer, jiffies + HZ);
565
cmdctrl = cmd->opcode << 8;
568
switch (mmc_resp_type(cmd)) {
570
cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE;
573
cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1;
576
cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B;
579
cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2;
582
cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3;
585
pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc));
592
via_sdc_preparedata(host, data);
595
if (data->blocks > 1) {
596
if (data->flags & MMC_DATA_WRITE) {
597
cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
598
cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR;
600
cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD;
603
if (data->flags & MMC_DATA_WRITE) {
604
cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
605
cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR;
607
cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD;
612
if (cmd == host->mrq->stop)
613
cmdctrl |= VIA_CRDR_SDCTRL_STOP;
615
cmdctrl |= VIA_CRDR_SDCTRL_START;
617
addrbase = host->sdhc_mmiobase;
618
writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
619
writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
622
static void via_sdc_finish_data(struct via_crdr_mmc_host *host)
624
struct mmc_data *data;
632
data->bytes_xfered = 0;
634
data->bytes_xfered = data->blocks * data->blksz;
636
dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
637
((data->flags & MMC_DATA_READ) ?
638
PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
641
via_sdc_send_command(host, data->stop);
643
tasklet_schedule(&host->finish_tasklet);
646
static void via_sdc_finish_command(struct via_crdr_mmc_host *host)
648
via_sdc_get_response(host, host->cmd);
650
host->cmd->error = 0;
652
if (!host->cmd->data)
653
tasklet_schedule(&host->finish_tasklet);
658
static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq)
660
void __iomem *addrbase;
661
struct via_crdr_mmc_host *host;
665
host = mmc_priv(mmc);
667
spin_lock_irqsave(&host->lock, flags);
669
addrbase = host->pcictrl_mmiobase;
670
writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
672
status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
673
status &= VIA_CRDR_SDSTS_W1C_MASK;
674
writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
676
WARN_ON(host->mrq != NULL);
679
status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
680
if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) {
681
host->mrq->cmd->error = -ENOMEDIUM;
682
tasklet_schedule(&host->finish_tasklet);
684
via_sdc_send_command(host, mrq->cmd);
688
spin_unlock_irqrestore(&host->lock, flags);
691
static void via_sdc_set_power(struct via_crdr_mmc_host *host,
692
unsigned short power, unsigned int on)
697
spin_lock_irqsave(&host->lock, flags);
699
host->power = (1 << power);
701
gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
702
if (host->power == MMC_VDD_165_195)
703
gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
705
gatt |= VIA_CRDR_PCICLKGATT_3V3;
707
gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON;
709
gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
710
writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
713
spin_unlock_irqrestore(&host->lock, flags);
715
via_pwron_sleep(host);
718
static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
720
struct via_crdr_mmc_host *host;
722
void __iomem *addrbase;
723
u32 org_data, sdextctrl;
726
host = mmc_priv(mmc);
728
spin_lock_irqsave(&host->lock, flags);
730
addrbase = host->sdhc_mmiobase;
731
org_data = readl(addrbase + VIA_CRDR_SDBUSMODE);
732
sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL);
734
if (ios->bus_width == MMC_BUS_WIDTH_1)
735
org_data &= ~VIA_CRDR_SDMODE_4BIT;
737
org_data |= VIA_CRDR_SDMODE_4BIT;
739
if (ios->power_mode == MMC_POWER_OFF)
740
org_data &= ~VIA_CRDR_SDMODE_CLK_ON;
742
org_data |= VIA_CRDR_SDMODE_CLK_ON;
744
if (ios->timing == MMC_TIMING_SD_HS)
745
sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD;
747
sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD;
749
writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
750
writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
752
if (ios->clock >= 48000000)
754
else if (ios->clock >= 33000000)
756
else if (ios->clock >= 24000000)
758
else if (ios->clock >= 16000000)
760
else if (ios->clock >= 12000000)
762
else if (ios->clock >= 8000000)
765
clock = PCI_CLK_375K;
767
addrbase = host->pcictrl_mmiobase;
768
if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock)
769
writeb(clock, addrbase + VIA_CRDR_PCISDCCLK);
772
spin_unlock_irqrestore(&host->lock, flags);
774
if (ios->power_mode != MMC_POWER_OFF)
775
via_sdc_set_power(host, ios->vdd, 1);
777
via_sdc_set_power(host, ios->vdd, 0);
780
static int via_sdc_get_ro(struct mmc_host *mmc)
782
struct via_crdr_mmc_host *host;
786
host = mmc_priv(mmc);
788
spin_lock_irqsave(&host->lock, flags);
790
status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
792
spin_unlock_irqrestore(&host->lock, flags);
794
return !(status & VIA_CRDR_SDSTS_WP);
797
static const struct mmc_host_ops via_sdc_ops = {
798
.request = via_sdc_request,
799
.set_ios = via_sdc_set_ios,
800
.get_ro = via_sdc_get_ro,
803
static void via_reset_pcictrl(struct via_crdr_mmc_host *host)
805
void __iomem *addrbase;
809
addrbase = host->pcictrl_mmiobase;
811
spin_lock_irqsave(&host->lock, flags);
813
via_save_pcictrlreg(host);
814
via_save_sdcreg(host);
816
spin_unlock_irqrestore(&host->lock, flags);
818
gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
819
if (host->power == MMC_VDD_165_195)
820
gatt &= VIA_CRDR_PCICLKGATT_3V3;
822
gatt |= VIA_CRDR_PCICLKGATT_3V3;
823
writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
824
via_pwron_sleep(host);
825
gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
826
writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
829
spin_lock_irqsave(&host->lock, flags);
831
via_restore_pcictrlreg(host);
832
via_restore_sdcreg(host);
835
spin_unlock_irqrestore(&host->lock, flags);
838
static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask)
840
BUG_ON(intmask == 0);
843
pr_err("%s: Got command interrupt 0x%x even "
844
"though no command operation was in progress.\n",
845
mmc_hostname(host->mmc), intmask);
849
if (intmask & VIA_CRDR_SDSTS_CRTO)
850
host->cmd->error = -ETIMEDOUT;
851
else if (intmask & VIA_CRDR_SDSTS_SC)
852
host->cmd->error = -EILSEQ;
854
if (host->cmd->error)
855
tasklet_schedule(&host->finish_tasklet);
856
else if (intmask & VIA_CRDR_SDSTS_CRD)
857
via_sdc_finish_command(host);
860
static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask)
862
BUG_ON(intmask == 0);
864
if (intmask & VIA_CRDR_SDSTS_DT)
865
host->data->error = -ETIMEDOUT;
866
else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC))
867
host->data->error = -EILSEQ;
869
via_sdc_finish_data(host);
872
static irqreturn_t via_sdc_isr(int irq, void *dev_id)
874
struct via_crdr_mmc_host *sdhost = dev_id;
875
void __iomem *addrbase;
883
spin_lock(&sdhost->lock);
885
addrbase = sdhost->pcictrl_mmiobase;
886
pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS);
887
if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) {
892
addrbase = sdhost->sdhc_mmiobase;
893
sd_status = readw(addrbase + VIA_CRDR_SDSTATUS);
894
sd_status &= VIA_CRDR_SDSTS_INT_MASK;
895
sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK;
901
if (sd_status & VIA_CRDR_SDSTS_CIR) {
902
writew(sd_status & VIA_CRDR_SDSTS_CIR,
903
addrbase + VIA_CRDR_SDSTATUS);
905
schedule_work(&sdhost->carddet_work);
908
sd_status &= ~VIA_CRDR_SDSTS_CIR;
909
if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) {
910
writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK,
911
addrbase + VIA_CRDR_SDSTATUS);
912
via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK);
914
if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) {
915
writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK,
916
addrbase + VIA_CRDR_SDSTATUS);
917
via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK);
920
sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK);
922
pr_err("%s: Unexpected interrupt 0x%x\n",
923
mmc_hostname(sdhost->mmc), sd_status);
924
writew(sd_status, addrbase + VIA_CRDR_SDSTATUS);
927
result = IRQ_HANDLED;
931
spin_unlock(&sdhost->lock);
936
static void via_sdc_timeout(unsigned long ulongdata)
938
struct via_crdr_mmc_host *sdhost;
941
sdhost = (struct via_crdr_mmc_host *)ulongdata;
943
spin_lock_irqsave(&sdhost->lock, flags);
946
pr_err("%s: Timeout waiting for hardware interrupt."
947
"cmd:0x%x\n", mmc_hostname(sdhost->mmc),
948
sdhost->mrq->cmd->opcode);
951
writel(VIA_CRDR_DMACTRL_SFTRST,
952
sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
953
sdhost->data->error = -ETIMEDOUT;
954
via_sdc_finish_data(sdhost);
957
sdhost->cmd->error = -ETIMEDOUT;
959
sdhost->mrq->cmd->error = -ETIMEDOUT;
960
tasklet_schedule(&sdhost->finish_tasklet);
965
spin_unlock_irqrestore(&sdhost->lock, flags);
968
static void via_sdc_tasklet_finish(unsigned long param)
970
struct via_crdr_mmc_host *host;
972
struct mmc_request *mrq;
974
host = (struct via_crdr_mmc_host *)param;
976
spin_lock_irqsave(&host->lock, flags);
978
del_timer(&host->timer);
984
spin_unlock_irqrestore(&host->lock, flags);
986
mmc_request_done(host->mmc, mrq);
989
static void via_sdc_card_detect(struct work_struct *work)
991
struct via_crdr_mmc_host *host;
992
void __iomem *addrbase;
996
host = container_of(work, struct via_crdr_mmc_host, carddet_work);
998
addrbase = host->ddma_mmiobase;
999
writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
1001
spin_lock_irqsave(&host->lock, flags);
1003
addrbase = host->pcictrl_mmiobase;
1004
writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
1006
addrbase = host->sdhc_mmiobase;
1007
status = readw(addrbase + VIA_CRDR_SDSTATUS);
1008
if (!(status & VIA_CRDR_SDSTS_SLOTG)) {
1010
pr_err("%s: Card removed during transfer!\n",
1011
mmc_hostname(host->mmc));
1012
host->mrq->cmd->error = -ENOMEDIUM;
1013
tasklet_schedule(&host->finish_tasklet);
1017
spin_unlock_irqrestore(&host->lock, flags);
1019
via_reset_pcictrl(host);
1021
spin_lock_irqsave(&host->lock, flags);
1025
spin_unlock_irqrestore(&host->lock, flags);
1027
via_print_pcictrl(host);
1028
via_print_sdchc(host);
1030
mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1033
static void via_init_mmc_host(struct via_crdr_mmc_host *host)
1035
struct mmc_host *mmc = host->mmc;
1036
void __iomem *addrbase;
1040
init_timer(&host->timer);
1041
host->timer.data = (unsigned long)host;
1042
host->timer.function = via_sdc_timeout;
1044
spin_lock_init(&host->lock);
1046
mmc->f_min = VIA_CRDR_MIN_CLOCK;
1047
mmc->f_max = VIA_CRDR_MAX_CLOCK;
1048
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1049
mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
1050
mmc->ops = &via_sdc_ops;
1052
/*Hardware cannot do scatter lists*/
1053
mmc->max_hw_segs = 1;
1054
mmc->max_phys_segs = 1;
1056
mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH;
1057
mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT;
1059
mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
1060
mmc->max_req_size = mmc->max_seg_size;
1062
INIT_WORK(&host->carddet_work, via_sdc_card_detect);
1064
tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish,
1065
(unsigned long)host);
1067
addrbase = host->sdhc_mmiobase;
1068
writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1071
lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1072
writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1074
status = readw(addrbase + VIA_CRDR_SDSTATUS);
1075
status &= VIA_CRDR_SDSTS_W1C_MASK;
1076
writew(status, addrbase + VIA_CRDR_SDSTATUS);
1078
status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1079
status |= VIA_CRDR_SDSTS_CFE;
1080
writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1082
writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL);
1084
writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
1088
static int __devinit via_sd_probe(struct pci_dev *pcidev,
1089
const struct pci_device_id *id)
1091
struct mmc_host *mmc;
1092
struct via_crdr_mmc_host *sdhost;
1097
pci_read_config_byte(pcidev, PCI_CLASS_REVISION, &rev);
1099
": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
1100
pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1103
ret = pci_enable_device(pcidev);
1107
ret = pci_request_regions(pcidev, DRV_NAME);
1111
pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0);
1112
pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0);
1114
mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev);
1120
sdhost = mmc_priv(mmc);
1122
dev_set_drvdata(&pcidev->dev, sdhost);
1124
len = pci_resource_len(pcidev, 0);
1125
base = pci_resource_start(pcidev, 0);
1126
sdhost->mmiobase = ioremap_nocache(base, len);
1127
if (!sdhost->mmiobase) {
1132
sdhost->sdhc_mmiobase =
1133
sdhost->mmiobase + VIA_CRDR_SDC_OFF;
1134
sdhost->ddma_mmiobase =
1135
sdhost->mmiobase + VIA_CRDR_DDMA_OFF;
1136
sdhost->pcictrl_mmiobase =
1137
sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF;
1139
sdhost->power = MMC_VDD_165_195;
1141
gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
1142
writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1143
via_pwron_sleep(sdhost);
1144
gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1145
writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1148
via_init_mmc_host(sdhost);
1151
request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME,
1156
writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN,
1157
sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1158
writeb(VIA_CRDR_PCITMOCTRL_1024MS,
1159
sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL);
1161
/* device-specific quirks */
1162
if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
1163
pcidev->subsystem_device == 0x3891)
1164
sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY;
1171
iounmap(sdhost->mmiobase);
1173
dev_set_drvdata(&pcidev->dev, NULL);
1176
pci_release_regions(pcidev);
1178
pci_disable_device(pcidev);
1183
static void __devexit via_sd_remove(struct pci_dev *pcidev)
1185
struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev);
1186
unsigned long flags;
1189
spin_lock_irqsave(&sdhost->lock, flags);
1191
/* Ensure we don't accept more commands from mmc layer */
1194
/* Disable generating further interrupts */
1195
writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1199
printk(KERN_ERR "%s: Controller removed during "
1200
"transfer\n", mmc_hostname(sdhost->mmc));
1202
/* make sure all DMA is stopped */
1203
writel(VIA_CRDR_DMACTRL_SFTRST,
1204
sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
1206
sdhost->mrq->cmd->error = -ENOMEDIUM;
1207
if (sdhost->mrq->stop)
1208
sdhost->mrq->stop->error = -ENOMEDIUM;
1209
tasklet_schedule(&sdhost->finish_tasklet);
1211
spin_unlock_irqrestore(&sdhost->lock, flags);
1213
mmc_remove_host(sdhost->mmc);
1215
free_irq(pcidev->irq, sdhost);
1217
del_timer_sync(&sdhost->timer);
1219
tasklet_kill(&sdhost->finish_tasklet);
1221
/* switch off power */
1222
gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1223
gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
1224
writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1226
iounmap(sdhost->mmiobase);
1227
dev_set_drvdata(&pcidev->dev, NULL);
1228
mmc_free_host(sdhost->mmc);
1229
pci_release_regions(pcidev);
1230
pci_disable_device(pcidev);
1233
": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
1234
pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1239
static void via_init_sdc_pm(struct via_crdr_mmc_host *host)
1241
struct sdhcreg *pm_sdhcreg;
1242
void __iomem *addrbase;
1246
pm_sdhcreg = &(host->pm_sdhc_reg);
1247
addrbase = host->sdhc_mmiobase;
1249
writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1251
lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1252
writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1254
status = readw(addrbase + VIA_CRDR_SDSTATUS);
1255
status &= VIA_CRDR_SDSTS_W1C_MASK;
1256
writew(status, addrbase + VIA_CRDR_SDSTATUS);
1258
status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1259
status |= VIA_CRDR_SDSTS_CFE;
1260
writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1262
writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
1263
writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
1264
writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
1265
writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
1266
writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
1267
writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
1269
via_print_pcictrl(host);
1270
via_print_sdchc(host);
1273
static int via_sd_suspend(struct pci_dev *pcidev, pm_message_t state)
1275
struct via_crdr_mmc_host *host;
1278
host = pci_get_drvdata(pcidev);
1280
via_save_pcictrlreg(host);
1281
via_save_sdcreg(host);
1283
ret = mmc_suspend_host(host->mmc, state);
1285
pci_save_state(pcidev);
1286
pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1287
pci_disable_device(pcidev);
1288
pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1293
static int via_sd_resume(struct pci_dev *pcidev)
1295
struct via_crdr_mmc_host *sdhost;
1299
sdhost = pci_get_drvdata(pcidev);
1301
gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
1302
if (sdhost->power == MMC_VDD_165_195)
1303
gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
1305
gatt |= VIA_CRDR_PCICLKGATT_3V3;
1306
writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1307
via_pwron_sleep(sdhost);
1308
gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1309
writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1314
pci_set_power_state(pcidev, PCI_D0);
1315
pci_restore_state(pcidev);
1316
ret = pci_enable_device(pcidev);
1320
via_restore_pcictrlreg(sdhost);
1321
via_init_sdc_pm(sdhost);
1323
ret = mmc_resume_host(sdhost->mmc);
1328
#else /* CONFIG_PM */
1330
#define via_sd_suspend NULL
1331
#define via_sd_resume NULL
1333
#endif /* CONFIG_PM */
1335
static struct pci_driver via_sd_driver = {
1337
.id_table = via_ids,
1338
.probe = via_sd_probe,
1339
.remove = __devexit_p(via_sd_remove),
1340
.suspend = via_sd_suspend,
1341
.resume = via_sd_resume,
1344
static int __init via_sd_drv_init(void)
1346
pr_info(DRV_NAME ": VIA SD/MMC Card Reader driver "
1347
"(C) 2008 VIA Technologies, Inc.\n");
1349
return pci_register_driver(&via_sd_driver);
1352
static void __exit via_sd_drv_exit(void)
1354
pci_unregister_driver(&via_sd_driver);
1357
module_init(via_sd_drv_init);
1358
module_exit(via_sd_drv_exit);
1360
MODULE_LICENSE("GPL");
1361
MODULE_AUTHOR("VIA Technologies Inc.");
1362
MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");