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Viewing changes to arch/arm/mach-davinci/irq.c

  • Committer: Bazaar Package Importer
  • Author(s): Luke Yelavich
  • Date: 2009-08-05 23:00:52 UTC
  • Revision ID: james.westby@ubuntu.com-20090805230052-7xedvqcyk9dnnxb2
Tags: 2.6.31-1.1
New upstream release

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arch/arm/mach-davinci/irq.c
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#include <linux/io.h>
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#include <mach/hardware.h>
 
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#include <mach/cputype.h>
 
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#include <mach/common.h>
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#include <asm/mach/irq.h>
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#define IRQ_BIT(irq)            ((irq) & 0x1f)
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static inline unsigned int davinci_irq_readl(int offset)
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{
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        return davinci_readl(DAVINCI_ARM_INTC_BASE + offset);
 
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        return __raw_readl(davinci_intc_base + offset);
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}
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static inline void davinci_irq_writel(unsigned long value, int offset)
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{
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        davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset);
 
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        __raw_writel(value, davinci_intc_base + offset);
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}
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/* Disable interrupt */
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        .unmask = davinci_unmask_irq,
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};
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/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
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static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
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        [IRQ_VDINT0]            = 2,
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        [IRQ_VDINT1]            = 6,
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        [IRQ_VDINT2]            = 6,
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        [IRQ_HISTINT]           = 6,
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        [IRQ_H3AINT]            = 6,
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        [IRQ_PRVUINT]           = 6,
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        [IRQ_RSZINT]            = 6,
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        [7]                     = 7,
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        [IRQ_VENCINT]           = 6,
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        [IRQ_ASQINT]            = 6,
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        [IRQ_IMXINT]            = 6,
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        [IRQ_VLCDINT]           = 6,
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        [IRQ_USBINT]            = 4,
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        [IRQ_EMACINT]           = 4,
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        [14]                    = 7,
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        [15]                    = 7,
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        [IRQ_CCINT0]            = 5,    /* dma */
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        [IRQ_CCERRINT]          = 5,    /* dma */
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        [IRQ_TCERRINT0]         = 5,    /* dma */
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        [IRQ_TCERRINT]          = 5,    /* dma */
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        [IRQ_PSCIN]             = 7,
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        [21]                    = 7,
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        [IRQ_IDE]               = 4,
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        [23]                    = 7,
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        [IRQ_MBXINT]            = 7,
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        [IRQ_MBRINT]            = 7,
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        [IRQ_MMCINT]            = 7,
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        [IRQ_SDIOINT]           = 7,
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        [28]                    = 7,
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        [IRQ_DDRINT]            = 7,
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        [IRQ_AEMIFINT]          = 7,
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        [IRQ_VLQINT]            = 4,
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        [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
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        [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
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        [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
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        [IRQ_TINT1_TINT34]      = 7,    /* system tick */
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        [IRQ_PWMINT0]           = 7,
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        [IRQ_PWMINT1]           = 7,
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        [IRQ_PWMINT2]           = 7,
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        [IRQ_I2C]               = 3,
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        [IRQ_UARTINT0]          = 3,
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        [IRQ_UARTINT1]          = 3,
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        [IRQ_UARTINT2]          = 3,
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        [IRQ_SPINT0]            = 3,
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        [IRQ_SPINT1]            = 3,
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        [45]                    = 7,
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        [IRQ_DSP2ARM0]          = 4,
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        [IRQ_DSP2ARM1]          = 4,
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        [IRQ_GPIO0]             = 7,
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        [IRQ_GPIO1]             = 7,
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        [IRQ_GPIO2]             = 7,
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        [IRQ_GPIO3]             = 7,
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        [IRQ_GPIO4]             = 7,
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        [IRQ_GPIO5]             = 7,
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        [IRQ_GPIO6]             = 7,
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        [IRQ_GPIO7]             = 7,
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        [IRQ_GPIOBNK0]          = 7,
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        [IRQ_GPIOBNK1]          = 7,
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        [IRQ_GPIOBNK2]          = 7,
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        [IRQ_GPIOBNK3]          = 7,
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        [IRQ_GPIOBNK4]          = 7,
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        [IRQ_COMMTX]            = 7,
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        [IRQ_COMMRX]            = 7,
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        [IRQ_EMUINT]            = 7,
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};
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/* ARM Interrupt Controller Initialization */
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void __init davinci_irq_init(void)
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{
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        unsigned i;
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        const u8 *priority = default_priorities;
 
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        const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
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        /* Clear all interrupt requests */
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        davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
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                unsigned        j;
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                u32             pri;
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                for (j = 0, pri = 0; j < 32; j += 4, priority++)
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                        pri |= (*priority & 0x07) << j;
 
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                for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
 
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                        pri |= (*davinci_def_priorities & 0x07) << j;
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                davinci_irq_writel(pri, i);
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        }
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