2
This program is free software; you can redistribute it and/or modify
3
it under the terms of the GNU General Public License as published by
4
the Free Software Foundation; either version 2, or (at your option)
7
This program is distributed in the hope that it will be useful,
8
but WITHOUT ANY WARRANTY; without even the implied warranty of
9
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10
GNU General Public License for more details.
12
You should have received a copy of the GNU General Public License along
13
with this program; if not, write to the Free Software Foundation, Inc.,
14
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
* author teawater <c7code-uc@yahoo.com.cn> <teawater@gmail.com>
20
//koodailar add for mingw 2005.12.18 ----------------------------------------
22
#include "arch/arm/common/armdefs.h"
26
// end ----------------------------------------------------------------------
27
#include "arm2x86_self.h"
30
get_op_andl_T0_T1 (int *len)
32
unsigned int begin = 0, end = 0;
34
OP_BEGIN ("get_op_andl_T0_T1");
36
OP_END ("get_op_andl_T0_T1");
39
return ((uint8_t *) begin);
43
get_op_eorl_T0_T1 (int *len)
45
unsigned int begin = 0, end = 0;
47
OP_BEGIN ("get_op_eorl_T0_T1");
49
OP_END ("get_op_eorl_T0_T1");
52
return ((uint8_t *) begin);
56
get_op_subl_T0_T1 (int *len)
58
unsigned int begin = 0, end = 0;
60
OP_BEGIN ("get_op_subl_T0_T1");
62
OP_END ("get_op_subl_T0_T1");
65
return ((uint8_t *) begin);
69
get_op_subl_T0_T1_scv (int *len)
71
unsigned int begin = 0, end = 0;
73
OP_BEGIN ("get_op_subl_T0_T1_scv");
75
//CFLAG_reg = (T0<T1)?1:0;
76
CFLAG_reg = (T0 >= T1) ? 1 : 0;
77
//chy 2006-02-12 chage ! to ~
78
//VFLAG_reg = !(T2 ^ T1);
79
VFLAG_reg = ~(T2 ^ T1);
80
VFLAG_reg &= (T0 ^ T1);
83
OP_END ("get_op_subl_T0_T1_scv");
86
return ((uint8_t *) begin);
90
get_op_rsbl_T0_T1 (int *len)
92
unsigned int begin = 0, end = 0;
94
OP_BEGIN ("get_op_rsbl_T0_T1");
96
OP_END ("get_op_rsbl_T0_T1");
99
return ((uint8_t *) begin);
103
get_op_rsbl_T0_T1_scv (int *len)
105
unsigned int begin = 0, end = 0;
107
OP_BEGIN ("get_op_rsbl_T0_T1_scv");
109
//CFLAG_reg = (T1<T0)?1:0;
110
CFLAG_reg = (T1 >= T0) ? 1 : 0;
111
//chy 2006-02-12 chage ! to ~
112
//VFLAG_reg = !(T2 ^ T0);
113
VFLAG_reg = ~(T2 ^ T0);
114
VFLAG_reg &= (T0 ^ T1);
117
OP_END ("get_op_rsbl_T0_T1_scv");
120
return ((uint8_t *) begin);
124
get_op_addl_T0_T1 (int *len)
126
unsigned int begin = 0, end = 0;
128
OP_BEGIN ("get_op_addl_T0_T1");
130
OP_END ("get_op_addl_T0_T1");
133
return ((uint8_t *) begin);
137
get_op_addl_T0_T1_scv (int *len)
139
unsigned int begin = 0, end = 0;
141
OP_BEGIN ("get_op_addl_T0_T1_scv");
143
CFLAG_reg = (T2 < T0);
144
VFLAG_reg = ~(T0 ^ T1);
145
VFLAG_reg &= (T2 ^ T1);
148
OP_END ("get_op_addl_T0_T1_scv");
151
return ((uint8_t *) begin);
155
get_op_adcl_T0_T1 (int *len)
157
unsigned int begin = 0, end = 0;
159
OP_BEGIN ("get_op_adcl_T0_T1");
160
T0 += T1 + CFLAG_reg;
161
OP_END ("get_op_adcl_T0_T1");
164
return ((uint8_t *) begin);
168
get_op_adcl_T0_T1_scv (int *len)
170
unsigned int begin = 0, end = 0;
172
OP_BEGIN ("get_op_adcl_T0_T1_scv");
173
T2 = T0 + T1 + CFLAG_reg;
175
CFLAG_reg = (T2 < T0);
178
CFLAG_reg = (T2 <= T0);
180
VFLAG_reg = ~(T0 ^ T1);
181
VFLAG_reg &= (T2 ^ T1);
184
OP_END ("get_op_adcl_T0_T1_scv");
187
return ((uint8_t *) begin);
191
get_op_sbcl_T0_T1 (int *len)
193
unsigned int begin = 0, end = 0;
195
OP_BEGIN ("get_op_sbcl_T0_T1");
196
//T0 -= (T1 + !CFLAG_reg);
197
T0 = T0 - T1 + CFLAG_reg - 1;
198
OP_END ("get_op_sbcl_T0_T1");
201
return ((uint8_t *) begin);
205
get_op_sbcl_T0_T1_scv (int *len)
207
unsigned int begin = 0, end = 0;
209
OP_BEGIN ("get_op_sbcl_T0_T1_scv");
210
T2 = T0 - T1 + CFLAG_reg - 1;
212
CFLAG_reg = (T0 > T1);
215
CFLAG_reg = (T0 >= T1);
217
//chy 2006-02-12 chage ! to ~
218
//VFLAG_reg = !(T2 ^ T1);
219
VFLAG_reg = ~(T2 ^ T1);
220
VFLAG_reg &= (T0 ^ T1);
223
OP_END ("get_op_sbcl_T0_T1_scv");
226
return ((uint8_t *) begin);
230
get_op_rscl_T0_T1 (int *len)
232
unsigned int begin = 0, end = 0;
234
OP_BEGIN ("get_op_rscl_T0_T1");
235
//T0 = T1 - T0 - !CFLAG_reg;
236
T0 = T1 - T0 + CFLAG_reg - 1;
237
OP_END ("get_op_rscl_T0_T1");
240
return ((uint8_t *) begin);
244
get_op_rscl_T0_T1_scv (int *len)
246
unsigned int begin = 0, end = 0;
248
OP_BEGIN ("get_op_rscl_T0_T1_scv");
251
//CFLAG_reg = (T1<T0)?1:0;
252
//CFLAG_reg = (T1 >= T0)?1:0;
254
CFLAG_reg = (T1 > T0);
257
CFLAG_reg = (T1 >= T0);
259
//chy 2006-02-12 chage ! to ~
260
//VFLAG_reg = !(T2 ^ T0);
261
VFLAG_reg = ~(T2 ^ T0);
262
VFLAG_reg &= (T0 ^ T1);
265
OP_END ("get_op_rscl_T0_T1_scv");
268
return ((uint8_t *) begin);
272
get_op_orrl_T0_T1 (int *len)
274
unsigned int begin = 0, end = 0;
276
OP_BEGIN ("get_op_orrl_T0_T1");
278
OP_END ("get_op_orrl_T0_T1");
281
return ((uint8_t *) begin);
285
get_op_movl_T0_T1 (int *len)
287
unsigned int begin = 0, end = 0;
289
OP_BEGIN ("get_op_movl_T0_T1");
291
OP_END ("get_op_movl_T0_T1");
294
return ((uint8_t *) begin);
298
get_op_bicl_T0_T1 (int *len)
300
unsigned int begin = 0, end = 0;
302
OP_BEGIN ("get_op_bicl_T0_T1");
304
OP_END ("get_op_bicl_T0_T1");
307
return ((uint8_t *) begin);
311
get_op_notl_T0_T1 (int *len)
313
unsigned int begin = 0, end = 0;
315
OP_BEGIN ("get_op_notl_T0_T1");
317
OP_END ("get_op_notl_T0_T1");
320
return ((uint8_t *) begin);
324
get_op_addl_T1_im (int *len)
326
unsigned int begin = 0, end = 0;
328
OP_BEGIN ("get_op_addl_T1_im");
330
OP_END ("get_op_addl_T1_im");
332
if (*len <= sizeof (ULONG_MAX)) {
336
*len -= sizeof (ULONG_MAX);
339
return ((uint8_t *) begin);
343
get_op_subl_T1_T2 (int *len)
345
unsigned int begin = 0, end = 0;
347
OP_BEGIN ("get_op_subl_T1_T2");
349
OP_END ("get_op_subl_T1_T2");
352
return ((uint8_t *) begin);
356
get_op_addl_T1_T2 (int *len)
358
unsigned int begin = 0, end = 0;
360
OP_BEGIN ("get_op_addl_T1_T2");
362
OP_END ("get_op_addl_T1_T2");
365
return ((uint8_t *) begin);
368
//teawater add for xscale(arm v5) 2005.09.01------------------------------------
370
get_op_clzl_T0_T1 (int *len)
372
unsigned int begin = 0, end = 0;
374
OP_BEGIN ("get_op_clzl_T0_T1");
375
//chy 2006-02-12 fix a bug
377
for (T0 = 0; (T1 & 0x80000000) == 0; T1 <<= 1) {
381
OP_END ("get_op_clzl_T0_T1");
384
return ((uint8_t *) begin);
388
get_op_qaddl_T0_T1_sq (int *len)
390
unsigned int begin = 0, end = 0;
392
OP_BEGIN ("get_op_qaddl_T0_T1_sq");
394
QFLAG_reg = ~(T0 ^ T1);
395
QFLAG_reg &= (T2 ^ T1);
399
T0 = (T0 >> 31) ? 0x7fffffff : 0x80000000;
401
OP_END ("get_op_qaddl_T0_T1_sq");
404
return ((uint8_t *) begin);
408
get_op_qsubl_T0_T1_sq (int *len)
410
unsigned int begin = 0, end = 0;
412
OP_BEGIN ("get_op_qsubl_T0_T1_sq");
414
//chy 2006-02-12 chage ! to ~
415
//QFLAG_reg = !(T2 ^ T1);
416
QFLAG_reg = ~(T2 ^ T1);
417
QFLAG_reg &= (T0 ^ T1);
421
T0 = (T0 >> 31) ? 0x7fffffff : 0x80000000;
423
OP_END ("get_op_qsubl_T0_T1_sq");
426
return ((uint8_t *) begin);
430
get_op_addl_T0_T1_sq (int *len)
432
unsigned int begin = 0, end = 0;
434
OP_BEGIN ("get_op_addl_T0_T1_sq");
436
QFLAG_reg = ~(T0 ^ T1);
437
QFLAG_reg &= (T2 ^ T1);
440
OP_END ("get_op_addl_T0_T1_sq");
443
return ((uint8_t *) begin);
446
//AJ2D--------------------------------------------------------------------------
448
op_table_t op_andl_T0_T1;
449
op_table_t op_eorl_T0_T1;
450
op_table_t op_subl_T0_T1;
451
op_table_t op_subl_T0_T1_scv;
452
op_table_t op_rsbl_T0_T1;
453
op_table_t op_rsbl_T0_T1_scv;
454
op_table_t op_addl_T0_T1;
455
op_table_t op_addl_T0_T1_scv;
456
op_table_t op_adcl_T0_T1;
457
op_table_t op_adcl_T0_T1_scv;
458
op_table_t op_sbcl_T0_T1;
459
op_table_t op_sbcl_T0_T1_scv;
460
op_table_t op_rscl_T0_T1;
461
op_table_t op_rscl_T0_T1_scv;
462
op_table_t op_orrl_T0_T1;
463
op_table_t op_movl_T0_T1;
464
op_table_t op_bicl_T0_T1;
465
op_table_t op_notl_T0_T1;
466
op_table_t op_addl_T1_im;
467
op_table_t op_subl_T1_T2;
468
op_table_t op_addl_T1_T2;
469
//teawater add for xscale(arm v5) 2005.09.01------------------------------------
470
op_table_t op_clzl_T0_T1;
471
op_table_t op_qaddl_T0_T1_sq;
472
op_table_t op_qsubl_T0_T1_sq;
473
op_table_t op_addl_T0_T1_sq;
474
//AJ2D--------------------------------------------------------------------------
479
op_andl_T0_T1.op = get_op_andl_T0_T1 (&op_andl_T0_T1.len);
480
if (op_andl_T0_T1.len <= 0)
483
op_eorl_T0_T1.op = get_op_eorl_T0_T1 (&op_eorl_T0_T1.len);
484
if (op_eorl_T0_T1.len <= 0)
487
op_subl_T0_T1.op = get_op_subl_T0_T1 (&op_subl_T0_T1.len);
488
if (op_subl_T0_T1.len <= 0)
491
op_subl_T0_T1_scv.op = get_op_subl_T0_T1_scv (&op_subl_T0_T1_scv.len);
492
if (op_subl_T0_T1_scv.len <= 0)
495
op_rsbl_T0_T1.op = get_op_rsbl_T0_T1 (&op_rsbl_T0_T1.len);
496
if (op_rsbl_T0_T1.len <= 0)
499
op_rsbl_T0_T1_scv.op = get_op_rsbl_T0_T1_scv (&op_rsbl_T0_T1_scv.len);
500
if (op_rsbl_T0_T1_scv.len <= 0)
503
op_addl_T0_T1.op = get_op_addl_T0_T1 (&op_addl_T0_T1.len);
504
if (op_addl_T0_T1.len <= 0)
507
op_addl_T0_T1_scv.op = get_op_addl_T0_T1_scv (&op_addl_T0_T1_scv.len);
508
if (op_addl_T0_T1_scv.len <= 0)
511
op_adcl_T0_T1.op = get_op_adcl_T0_T1 (&op_adcl_T0_T1.len);
512
if (op_adcl_T0_T1.len <= 0)
515
op_adcl_T0_T1_scv.op = get_op_adcl_T0_T1_scv (&op_adcl_T0_T1_scv.len);
516
if (op_adcl_T0_T1_scv.len <= 0)
519
op_sbcl_T0_T1.op = get_op_sbcl_T0_T1 (&op_sbcl_T0_T1.len);
520
if (op_sbcl_T0_T1.len <= 0)
523
op_sbcl_T0_T1_scv.op = get_op_sbcl_T0_T1_scv (&op_sbcl_T0_T1_scv.len);
524
if (op_sbcl_T0_T1_scv.len <= 0)
527
op_rscl_T0_T1.op = get_op_rscl_T0_T1 (&op_rscl_T0_T1.len);
528
if (op_rscl_T0_T1.len <= 0)
531
op_rscl_T0_T1_scv.op = get_op_rscl_T0_T1_scv (&op_rscl_T0_T1_scv.len);
532
if (op_rscl_T0_T1_scv.len <= 0)
535
op_orrl_T0_T1.op = get_op_orrl_T0_T1 (&op_orrl_T0_T1.len);
536
if (op_orrl_T0_T1.len <= 0)
539
op_movl_T0_T1.op = get_op_movl_T0_T1 (&op_movl_T0_T1.len);
540
if (op_movl_T0_T1.len <= 0)
543
op_bicl_T0_T1.op = get_op_bicl_T0_T1 (&op_bicl_T0_T1.len);
544
if (op_bicl_T0_T1.len <= 0)
547
op_notl_T0_T1.op = get_op_notl_T0_T1 (&op_notl_T0_T1.len);
548
if (op_notl_T0_T1.len <= 0)
551
op_addl_T1_im.op = get_op_addl_T1_im (&op_addl_T1_im.len);
552
if (op_addl_T1_im.len <= 0)
555
op_subl_T1_T2.op = get_op_subl_T1_T2 (&op_subl_T1_T2.len);
556
if (op_subl_T1_T2.len <= 0)
559
op_addl_T1_T2.op = get_op_addl_T1_T2 (&op_addl_T1_T2.len);
560
if (op_addl_T1_T2.len <= 0)
563
//teawater add for xscale(arm v5) 2005.09.01------------------------------------
564
op_clzl_T0_T1.op = get_op_clzl_T0_T1 (&op_clzl_T0_T1.len);
565
if (op_clzl_T0_T1.len <= 0)
568
op_qaddl_T0_T1_sq.op = get_op_qaddl_T0_T1_sq (&op_qaddl_T0_T1_sq.len);
569
if (op_qaddl_T0_T1_sq.len <= 0)
572
op_qsubl_T0_T1_sq.op = get_op_qsubl_T0_T1_sq (&op_qsubl_T0_T1_sq.len);
573
if (op_qsubl_T0_T1_sq.len <= 0)
576
op_addl_T0_T1_sq.op = get_op_addl_T0_T1_sq (&op_addl_T0_T1_sq.len);
577
if (op_addl_T0_T1_sq.len <= 0)
579
//AJ2D--------------------------------------------------------------------------
584
//--------------------------------------------------------------------------------------------------
586
arm2x86_get_op_and (ARMul_State * state, uint8_t ** tbpp, int *plen,
587
ARMword set_cc, ARMword rd)
589
GEN_OP (*tbpp, *plen, op_andl_T0_T1);
593
arm2x86_get_op_eor (ARMul_State * state, uint8_t ** tbpp, int *plen,
594
ARMword set_cc, ARMword rd)
596
GEN_OP (*tbpp, *plen, op_eorl_T0_T1);
600
arm2x86_get_op_sub (ARMul_State * state, uint8_t ** tbpp, int *plen,
601
ARMword set_cc, ARMword rd)
603
if (set_cc && rd != 15) {
604
GEN_OP (*tbpp, *plen, op_subl_T0_T1_scv);
607
GEN_OP (*tbpp, *plen, op_subl_T0_T1);
612
arm2x86_get_op_rsb (ARMul_State * state, uint8_t ** tbpp, int *plen,
613
ARMword set_cc, ARMword rd)
615
if (set_cc && rd != 15) {
616
GEN_OP (*tbpp, *plen, op_rsbl_T0_T1_scv);
619
GEN_OP (*tbpp, *plen, op_rsbl_T0_T1);
624
arm2x86_get_op_add (ARMul_State * state, uint8_t ** tbpp, int *plen,
625
ARMword set_cc, ARMword rd)
627
if (set_cc && rd != 15) {
628
GEN_OP (*tbpp, *plen, op_addl_T0_T1_scv);
631
GEN_OP (*tbpp, *plen, op_addl_T0_T1);
636
arm2x86_get_op_adc (ARMul_State * state, uint8_t ** tbpp, int *plen,
637
ARMword set_cc, ARMword rd)
639
if (set_cc && rd != 15) {
640
GEN_OP (*tbpp, *plen, op_adcl_T0_T1_scv);
643
GEN_OP (*tbpp, *plen, op_adcl_T0_T1);
648
arm2x86_get_op_sbc (ARMul_State * state, uint8_t ** tbpp, int *plen,
649
ARMword set_cc, ARMword rd)
651
if (set_cc && rd != 15) {
652
GEN_OP (*tbpp, *plen, op_sbcl_T0_T1_scv);
655
GEN_OP (*tbpp, *plen, op_sbcl_T0_T1);
660
arm2x86_get_op_rsc (ARMul_State * state, uint8_t ** tbpp, int *plen,
661
ARMword set_cc, ARMword rd)
663
if (set_cc && rd != 15) {
664
GEN_OP (*tbpp, *plen, op_rscl_T0_T1_scv);
667
GEN_OP (*tbpp, *plen, op_rscl_T0_T1);
672
arm2x86_get_op_tst (ARMul_State * state, uint8_t ** tbpp, int *plen,
673
ARMword set_cc, ARMword rd)
676
GEN_OP (*tbpp, *plen, op_andl_T0_T1);
681
arm2x86_get_op_teq (ARMul_State * state, uint8_t ** tbpp, int *plen,
682
ARMword set_cc, ARMword rd)
685
GEN_OP (*tbpp, *plen, op_eorl_T0_T1);
690
arm2x86_get_op_cmp (ARMul_State * state, uint8_t ** tbpp, int *plen,
691
ARMword set_cc, ARMword rd)
694
GEN_OP (*tbpp, *plen, op_subl_T0_T1_scv);
699
arm2x86_get_op_cmn (ARMul_State * state, uint8_t ** tbpp, int *plen,
700
ARMword set_cc, ARMword rd)
703
GEN_OP (*tbpp, *plen, op_addl_T0_T1_scv);
708
arm2x86_get_op_orr (ARMul_State * state, uint8_t ** tbpp, int *plen,
709
ARMword set_cc, ARMword rd)
711
GEN_OP (*tbpp, *plen, op_orrl_T0_T1);
715
arm2x86_get_op_mov (ARMul_State * state, uint8_t ** tbpp, int *plen,
716
ARMword set_cc, ARMword rd)
718
GEN_OP (*tbpp, *plen, op_movl_T0_T1);
722
arm2x86_get_op_bic (ARMul_State * state, uint8_t ** tbpp, int *plen,
723
ARMword set_cc, ARMword rd)
725
GEN_OP (*tbpp, *plen, op_bicl_T0_T1);
729
arm2x86_get_op_mvn (ARMul_State * state, uint8_t ** tbpp, int *plen,
730
ARMword set_cc, ARMword rd)
732
GEN_OP (*tbpp, *plen, op_notl_T0_T1);
735
arm2x86_get_dp_op_t *arm2x86_get_dp_op[16] = {
755
arm2x86_get_op_setcpsr_nzc (ARMul_State * state, uint8_t ** tbpp, int *plen,
756
ARMword set_cc, ARMword rd)
760
GEN_OP (*tbpp, *plen, op_logic_T0_sn);
761
//GEN_OP(*tbpp, *plen, op_set_nf);
763
GEN_OP (*tbpp, *plen, op_logic_T0_sz);
764
//GEN_OP(*tbpp, *plen, op_set_zf);
766
//GEN_OP(*tbpp, *plen, op_set_cf);
767
GEN_OP (*tbpp, *plen, op_set_nzcf);
772
arm2x86_get_op_setcpsr_nzc_setreg (ARMul_State * state, uint8_t ** tbpp,
773
int *plen, ARMword set_cc, ARMword rd)
775
if (set_cc && rd != 15) {
777
GEN_OP (*tbpp, *plen, op_logic_T0_sn);
778
//GEN_OP(*tbpp, *plen, op_set_nf);
780
GEN_OP (*tbpp, *plen, op_logic_T0_sz);
781
//GEN_OP(*tbpp, *plen, op_set_zf);
783
//GEN_OP(*tbpp, *plen, op_set_cf);
784
GEN_OP (*tbpp, *plen, op_set_nzcf);
786
gen_op_movl_reg_Tx (state, tbpp, plen, rd, 0);
787
if (rd == 15 && set_cc) {
788
//change pc & set spsr to cpsr
789
gen_op_movl_trap_im_use_T2 (state, tbpp, plen, TRAP_SETS_R15);
794
arm2x86_get_op_setcpsr_nzcv (ARMul_State * state, uint8_t ** tbpp, int *plen,
795
ARMword set_cc, ARMword rd)
799
GEN_OP (*tbpp, *plen, op_logic_T0_sn);
800
//GEN_OP(*tbpp, *plen, op_set_nf);
802
GEN_OP (*tbpp, *plen, op_logic_T0_sz);
803
//GEN_OP(*tbpp, *plen, op_set_zf);
805
//GEN_OP(*tbpp, *plen, op_set_cf);
807
//GEN_OP(*tbpp, *plen, op_set_vf);
808
GEN_OP (*tbpp, *plen, op_set_nzcvf);
813
arm2x86_get_op_setcpsr_nzcv_setreg (ARMul_State * state, uint8_t ** tbpp,
814
int *plen, ARMword set_cc, ARMword rd)
816
if (set_cc && rd != 15) {
818
//GEN_OP(*tbpp, *plen, op_set_cf);
820
//GEN_OP(*tbpp, *plen, op_set_vf);
822
GEN_OP (*tbpp, *plen, op_logic_T0_sn);
823
//GEN_OP(*tbpp, *plen, op_set_nf);
825
GEN_OP (*tbpp, *plen, op_logic_T0_sz);
826
//GEN_OP(*tbpp, *plen, op_set_zf);
827
GEN_OP (*tbpp, *plen, op_set_nzcvf);
829
gen_op_movl_reg_Tx (state, tbpp, plen, rd, 0);
830
if (rd == 15 && set_cc) {
831
//change pc & set spsr to cpsr
832
gen_op_movl_trap_im_use_T2 (state, tbpp, plen, TRAP_SETS_R15);
836
arm2x86_get_dp_op_t *arm2x86_get_dp_op_setcpsr[16] = {
837
arm2x86_get_op_setcpsr_nzc_setreg, //and
838
arm2x86_get_op_setcpsr_nzc_setreg, //eor
839
arm2x86_get_op_setcpsr_nzcv_setreg, //sub
840
arm2x86_get_op_setcpsr_nzcv_setreg, //rsb
841
arm2x86_get_op_setcpsr_nzcv_setreg, //add
842
arm2x86_get_op_setcpsr_nzcv_setreg, //adc
843
arm2x86_get_op_setcpsr_nzcv_setreg, //sbc
844
arm2x86_get_op_setcpsr_nzcv_setreg, //rsc
845
arm2x86_get_op_setcpsr_nzc, //tst
846
arm2x86_get_op_setcpsr_nzc, //teq
847
arm2x86_get_op_setcpsr_nzcv, //cmp
848
arm2x86_get_op_setcpsr_nzcv, //cmn
849
arm2x86_get_op_setcpsr_nzc_setreg, //orr
850
arm2x86_get_op_setcpsr_nzc_setreg, //mov
851
arm2x86_get_op_setcpsr_nzc_setreg, //bic
852
arm2x86_get_op_setcpsr_nzc_setreg, //mvn
855
//--------------------------------------------------------------------------------------------------
859
if (op_dp_T0_T1 ()) {