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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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/* Please note that modifications to all structs defined here are
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* subject to backwards-compatibility constraints.
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/* Each region is a minimum of 16k, and there are at most 255 of them.
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#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
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* of chars for next/prev indices */
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#define I915_LOG_MIN_TEX_REGION_SIZE 14
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typedef struct _drm_i915_init {
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I915_CLEANUP_DMA = 0x02,
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I915_RESUME_DMA = 0x03
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unsigned int mmio_offset;
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int sarea_priv_offset;
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unsigned int ring_start;
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unsigned int ring_end;
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unsigned int ring_size;
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unsigned int front_offset;
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unsigned int back_offset;
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unsigned int depth_offset;
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unsigned int pitch_bits;
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unsigned int back_pitch;
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unsigned int depth_pitch;
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typedef struct _drm_i915_sarea {
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struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
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int last_upload; /* last time texture was uploaded */
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int last_enqueue; /* last time a buffer was enqueued */
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int last_dispatch; /* age of the most recently dispatched buffer */
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int ctxOwner; /* last context to upload state */
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int pf_enabled; /* is pageflipping allowed? */
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int pf_current_page; /* which buffer is being displayed? */
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int perf_boxes; /* performance boxes to be displayed */
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int width, height; /* screen size in pixels */
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drm_handle_t front_handle;
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drm_handle_t back_handle;
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drm_handle_t depth_handle;
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drm_handle_t tex_handle;
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int log_tex_granularity;
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int rotation; /* 0, 90, 180 or 270 */
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int virtualX, virtualY;
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unsigned int front_tiled;
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unsigned int back_tiled;
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unsigned int depth_tiled;
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unsigned int rotated_tiled;
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unsigned int rotated2_tiled;
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/* fill out some space for old userspace triple buffer */
118
drm_handle_t unused_handle;
119
__u32 unused1, unused2, unused3;
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/* buffer object handles for static buffers. May change
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* over the lifetime of the client.
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__u32 front_bo_handle;
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__u32 back_bo_handle;
126
__u32 unused_bo_handle;
127
__u32 depth_bo_handle;
131
/* due to userspace building against these headers we need some compat here */
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#define planeA_x pipeA_x
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#define planeA_y pipeA_y
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#define planeA_w pipeA_w
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#define planeA_h pipeA_h
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#define planeB_x pipeB_x
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#define planeB_y pipeB_y
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#define planeB_w pipeB_w
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#define planeB_h pipeB_h
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/* Flags for perf_boxes
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#define I915_BOX_RING_EMPTY 0x1
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#define I915_BOX_FLIP 0x2
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#define I915_BOX_WAIT 0x4
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#define I915_BOX_TEXTURE_LOAD 0x8
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#define I915_BOX_LOST_CONTEXT 0x10
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/* I915 specific ioctls
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* The device specific ioctl range is 0x40 to 0x79.
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#define DRM_I915_INIT 0x00
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#define DRM_I915_FLUSH 0x01
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#define DRM_I915_FLIP 0x02
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#define DRM_I915_BATCHBUFFER 0x03
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#define DRM_I915_IRQ_EMIT 0x04
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#define DRM_I915_IRQ_WAIT 0x05
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#define DRM_I915_GETPARAM 0x06
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#define DRM_I915_SETPARAM 0x07
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#define DRM_I915_ALLOC 0x08
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#define DRM_I915_FREE 0x09
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#define DRM_I915_INIT_HEAP 0x0a
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#define DRM_I915_CMDBUFFER 0x0b
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#define DRM_I915_DESTROY_HEAP 0x0c
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#define DRM_I915_SET_VBLANK_PIPE 0x0d
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#define DRM_I915_GET_VBLANK_PIPE 0x0e
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#define DRM_I915_VBLANK_SWAP 0x0f
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#define DRM_I915_HWS_ADDR 0x11
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#define DRM_I915_GEM_INIT 0x13
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#define DRM_I915_GEM_EXECBUFFER 0x14
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#define DRM_I915_GEM_PIN 0x15
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#define DRM_I915_GEM_UNPIN 0x16
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#define DRM_I915_GEM_BUSY 0x17
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#define DRM_I915_GEM_THROTTLE 0x18
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#define DRM_I915_GEM_ENTERVT 0x19
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#define DRM_I915_GEM_LEAVEVT 0x1a
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#define DRM_I915_GEM_CREATE 0x1b
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#define DRM_I915_GEM_PREAD 0x1c
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#define DRM_I915_GEM_PWRITE 0x1d
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#define DRM_I915_GEM_MMAP 0x1e
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#define DRM_I915_GEM_SET_DOMAIN 0x1f
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#define DRM_I915_GEM_SW_FINISH 0x20
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#define DRM_I915_GEM_SET_TILING 0x21
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#define DRM_I915_GEM_GET_TILING 0x22
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#define DRM_I915_GEM_GET_APERTURE 0x23
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#define DRM_I915_GEM_MMAP_GTT 0x24
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#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
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#define DRM_I915_GEM_MADVISE 0x26
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#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
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#define DRM_I915_OVERLAY_ATTRS 0x28
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#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
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#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
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#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
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#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
198
#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
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#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
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#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
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#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
202
#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
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#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
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#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
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#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
208
#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
210
#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
211
#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
212
#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
213
#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
214
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
215
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
216
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
217
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
218
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
219
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
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#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
221
#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
222
#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
223
#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
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#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
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#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
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#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
227
#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
228
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image)
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#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
231
/* Allow drivers to submit batchbuffers directly to hardware, relying
232
* on the security mechanisms provided by hardware.
234
typedef struct drm_i915_batchbuffer {
235
int start; /* agp offset */
236
int used; /* nr bytes in use */
237
int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
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int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
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int num_cliprects; /* mulitpass with multiple cliprects? */
240
struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
241
} drm_i915_batchbuffer_t;
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/* As above, but pass a pointer to userspace buffer which can be
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* validated by the kernel prior to sending to hardware.
246
typedef struct _drm_i915_cmdbuffer {
247
char *buf; /* pointer to userspace command buffer */
248
int sz; /* nr bytes in buf */
249
int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
250
int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
251
int num_cliprects; /* mulitpass with multiple cliprects? */
252
struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
253
} drm_i915_cmdbuffer_t;
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/* Userspace can request & wait on irq's:
257
typedef struct drm_i915_irq_emit {
259
} drm_i915_irq_emit_t;
261
typedef struct drm_i915_irq_wait {
263
} drm_i915_irq_wait_t;
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/* Ioctl to query kernel params:
267
#define I915_PARAM_IRQ_ACTIVE 1
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#define I915_PARAM_ALLOW_BATCHBUFFER 2
269
#define I915_PARAM_LAST_DISPATCH 3
270
#define I915_PARAM_CHIPSET_ID 4
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#define I915_PARAM_HAS_GEM 5
272
#define I915_PARAM_NUM_FENCES_AVAIL 6
273
#define I915_PARAM_HAS_OVERLAY 7
274
#define I915_PARAM_HAS_PAGEFLIPPING 8
276
typedef struct drm_i915_getparam {
279
} drm_i915_getparam_t;
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/* Ioctl to set kernel params:
283
#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
284
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
285
#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
286
#define I915_SETPARAM_NUM_USED_FENCES 4
288
typedef struct drm_i915_setparam {
291
} drm_i915_setparam_t;
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/* A memory manager for regions of shared memory:
295
#define I915_MEM_REGION_AGP 1
297
typedef struct drm_i915_mem_alloc {
301
int *region_offset; /* offset from start of fb or agp */
302
} drm_i915_mem_alloc_t;
304
typedef struct drm_i915_mem_free {
307
} drm_i915_mem_free_t;
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typedef struct drm_i915_mem_init_heap {
313
} drm_i915_mem_init_heap_t;
315
/* Allow memory manager to be torn down and re-initialized (eg on
318
typedef struct drm_i915_mem_destroy_heap {
320
} drm_i915_mem_destroy_heap_t;
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/* Allow X server to configure which pipes to monitor for vblank signals
324
#define DRM_I915_VBLANK_PIPE_A 1
325
#define DRM_I915_VBLANK_PIPE_B 2
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typedef struct drm_i915_vblank_pipe {
329
} drm_i915_vblank_pipe_t;
331
/* Schedule buffer swap at given vertical blank:
333
typedef struct drm_i915_vblank_swap {
334
drm_drawable_t drawable;
335
enum drm_vblank_seq_type seqtype;
336
unsigned int sequence;
337
} drm_i915_vblank_swap_t;
339
typedef struct drm_i915_hws_addr {
341
} drm_i915_hws_addr_t;
343
struct drm_i915_gem_init {
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* Beginning offset in the GTT to be managed by the DRM memory
350
* Ending offset in the GTT to be managed by the DRM memory
356
struct drm_i915_gem_create {
358
* Requested size for the object.
360
* The (page-aligned) allocated size for the object will be returned.
364
* Returned handle for the object.
366
* Object handles are nonzero.
372
struct drm_i915_gem_pread {
373
/** Handle for the object being read. */
376
/** Offset into the object to read from */
378
/** Length of data to read */
381
* Pointer to write the data into.
383
* This is a fixed-size type for 32/64 compatibility.
388
struct drm_i915_gem_pwrite {
389
/** Handle for the object being written to. */
392
/** Offset into the object to write to */
394
/** Length of data to write */
397
* Pointer to read the data from.
399
* This is a fixed-size type for 32/64 compatibility.
404
struct drm_i915_gem_mmap {
405
/** Handle for the object being mapped. */
408
/** Offset in the object to map. */
411
* Length of data to map.
413
* The value will be page-aligned.
417
* Returned pointer the data was mapped at.
419
* This is a fixed-size type for 32/64 compatibility.
424
struct drm_i915_gem_mmap_gtt {
425
/** Handle for the object being mapped. */
429
* Fake offset to use for subsequent mmap call
431
* This is a fixed-size type for 32/64 compatibility.
436
struct drm_i915_gem_set_domain {
437
/** Handle for the object */
440
/** New read domains */
443
/** New write domain */
447
struct drm_i915_gem_sw_finish {
448
/** Handle for the object */
452
struct drm_i915_gem_relocation_entry {
454
* Handle of the buffer being pointed to by this relocation entry.
456
* It's appealing to make this be an index into the mm_validate_entry
457
* list to refer to the buffer, but this allows the driver to create
458
* a relocation list for state buffers and not re-write it per
459
* exec using the buffer.
464
* Value to be added to the offset of the target buffer to make up
465
* the relocation entry.
469
/** Offset in the buffer the relocation entry will be written into */
473
* Offset value of the target buffer that the relocation entry was last
476
* If the buffer has the same offset as last time, we can skip syncing
477
* and writing the relocation. This value is written back out by
478
* the execbuffer ioctl when the relocation is written.
480
__u64 presumed_offset;
483
* Target memory domains read by this operation.
488
* Target memory domains written by this operation.
490
* Note that only one domain may be written by the whole
491
* execbuffer operation, so that where there are conflicts,
492
* the application will get -EINVAL back.
498
* Intel memory domains
500
* Most of these just align with the various caches in
501
* the system and are used to flush and invalidate as
502
* objects end up cached in different domains.
505
#define I915_GEM_DOMAIN_CPU 0x00000001
506
/** Render cache, used by 2D and 3D drawing */
507
#define I915_GEM_DOMAIN_RENDER 0x00000002
508
/** Sampler cache, used by texture engine */
509
#define I915_GEM_DOMAIN_SAMPLER 0x00000004
510
/** Command queue, used to load batch buffers */
511
#define I915_GEM_DOMAIN_COMMAND 0x00000008
512
/** Instruction cache, used by shader programs */
513
#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
514
/** Vertex address cache */
515
#define I915_GEM_DOMAIN_VERTEX 0x00000020
516
/** GTT domain - aperture and scanout */
517
#define I915_GEM_DOMAIN_GTT 0x00000040
520
struct drm_i915_gem_exec_object {
522
* User's handle for a buffer to be bound into the GTT for this
527
/** Number of relocations to be performed on this buffer */
528
__u32 relocation_count;
530
* Pointer to array of struct drm_i915_gem_relocation_entry containing
531
* the relocations to be performed in this buffer.
535
/** Required alignment in graphics aperture */
539
* Returned value of the updated offset of the object, for future
540
* presumed_offset writes.
545
struct drm_i915_gem_execbuffer {
547
* List of buffers to be validated with their relocations to be
548
* performend on them.
550
* This is a pointer to an array of struct drm_i915_gem_validate_entry.
552
* These buffers must be listed in an order such that all relocations
553
* a buffer is performing refer to buffers that have already appeared
554
* in the validate list.
559
/** Offset in the batchbuffer to start execution from. */
560
__u32 batch_start_offset;
561
/** Bytes used in batchbuffer from batch_start_offset */
566
/** This is a struct drm_clip_rect *cliprects */
570
struct drm_i915_gem_pin {
571
/** Handle of the buffer to be pinned. */
575
/** alignment required within the aperture */
578
/** Returned GTT offset of the buffer. */
582
struct drm_i915_gem_unpin {
583
/** Handle of the buffer to be unpinned. */
588
struct drm_i915_gem_busy {
589
/** Handle of the buffer to check for busy */
592
/** Return busy status (1 if busy, 0 if idle) */
596
#define I915_TILING_NONE 0
597
#define I915_TILING_X 1
598
#define I915_TILING_Y 2
600
#define I915_BIT_6_SWIZZLE_NONE 0
601
#define I915_BIT_6_SWIZZLE_9 1
602
#define I915_BIT_6_SWIZZLE_9_10 2
603
#define I915_BIT_6_SWIZZLE_9_11 3
604
#define I915_BIT_6_SWIZZLE_9_10_11 4
605
/* Not seen by userland */
606
#define I915_BIT_6_SWIZZLE_UNKNOWN 5
607
/* Seen by userland. */
608
#define I915_BIT_6_SWIZZLE_9_17 6
609
#define I915_BIT_6_SWIZZLE_9_10_17 7
611
struct drm_i915_gem_set_tiling {
612
/** Handle of the buffer to have its tiling state updated */
616
* Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
619
* This value is to be set on request, and will be updated by the
620
* kernel on successful return with the actual chosen tiling layout.
622
* The tiling mode may be demoted to I915_TILING_NONE when the system
623
* has bit 6 swizzling that can't be managed correctly by GEM.
625
* Buffer contents become undefined when changing tiling_mode.
630
* Stride in bytes for the object when in I915_TILING_X or
636
* Returned address bit 6 swizzling required for CPU access through
642
struct drm_i915_gem_get_tiling {
643
/** Handle of the buffer to get tiling state for. */
647
* Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
653
* Returned address bit 6 swizzling required for CPU access through
659
struct drm_i915_gem_get_aperture {
660
/** Total size of the aperture used by i915_gem_execbuffer, in bytes */
664
* Available space in the aperture used by i915_gem_execbuffer, in
667
__u64 aper_available_size;
670
struct drm_i915_get_pipe_from_crtc_id {
671
/** ID of CRTC being requested **/
674
/** pipe of requested CRTC **/
678
#define I915_MADV_WILLNEED 0
679
#define I915_MADV_DONTNEED 1
680
#define __I915_MADV_PURGED 2 /* internal state */
682
struct drm_i915_gem_madvise {
683
/** Handle of the buffer to change the backing store advice */
686
/* Advice: either the buffer will be needed again in the near future,
687
* or wont be and could be discarded under memory pressure.
691
/** Whether the backing store still exists. */
696
#define I915_OVERLAY_TYPE_MASK 0xff
697
#define I915_OVERLAY_YUV_PLANAR 0x01
698
#define I915_OVERLAY_YUV_PACKED 0x02
699
#define I915_OVERLAY_RGB 0x03
701
#define I915_OVERLAY_DEPTH_MASK 0xff00
702
#define I915_OVERLAY_RGB24 0x1000
703
#define I915_OVERLAY_RGB16 0x2000
704
#define I915_OVERLAY_RGB15 0x3000
705
#define I915_OVERLAY_YUV422 0x0100
706
#define I915_OVERLAY_YUV411 0x0200
707
#define I915_OVERLAY_YUV420 0x0300
708
#define I915_OVERLAY_YUV410 0x0400
710
#define I915_OVERLAY_SWAP_MASK 0xff0000
711
#define I915_OVERLAY_NO_SWAP 0x000000
712
#define I915_OVERLAY_UV_SWAP 0x010000
713
#define I915_OVERLAY_Y_SWAP 0x020000
714
#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
716
#define I915_OVERLAY_FLAGS_MASK 0xff000000
717
#define I915_OVERLAY_ENABLE 0x01000000
719
struct drm_intel_overlay_put_image {
720
/* various flags and src format description */
722
/* source picture description */
724
/* stride values and offsets are in bytes, buffer relative */
725
__u16 stride_Y; /* stride for packed formats */
727
__u32 offset_Y; /* offset for packet formats */
733
/* to compensate the scaling factors for partially covered surfaces */
734
__u16 src_scan_width;
735
__u16 src_scan_height;
736
/* output crtc description */
745
#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
746
#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
747
struct drm_intel_overlay_attrs {
761
#endif /* _I915_DRM_H_ */
added
removed
include/drm/i915_drm.h
