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- Committer: Bazaar Package Importer
- Author(s): Timo Aaltonen
- Date: 2010-01-09 00:00:29 UTC
- mfrom: (1.3.3 upstream)
- mto: (2.2.9 experimental)
- mto: This revision was merged to the branch mainline in revision 39.
- Revision ID: james.westby@ubuntu.com-20100109000029-yhmol07llcxuzk0c
Tags: upstream-2.4.17
Import upstream version 2.4.17
- files added:
- .gitignore
- include
- include/drm
- intel
- nouveau
- radeon
- tests/ttmtest
- tests/ttmtest/src
- files removed:
- Makefile.in
- libdrm
- libdrm/intel
- libdrm/nouveau
- libdrm/radeon
- shared-core
- files modified:
- Makefile.am
added
removed
shared-core/radeon_drm.h
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/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
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*
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* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
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* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Kevin E. Martin <martin@valinux.com>
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* Gareth Hughes <gareth@valinux.com>
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* Keith Whitwell <keith@tungstengraphics.com>
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*/
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#ifndef __RADEON_DRM_H__
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#define __RADEON_DRM_H__
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the X server file (radeon_sarea.h)
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*/
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#ifndef __RADEON_SAREA_DEFINES__
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#define __RADEON_SAREA_DEFINES__
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/* Old style state flags, required for sarea interface (1.1 and 1.2
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* clears) and 1.2 drm_vertex2 ioctl.
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*/
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#define RADEON_UPLOAD_CONTEXT 0x00000001
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#define RADEON_UPLOAD_VERTFMT 0x00000002
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#define RADEON_UPLOAD_LINE 0x00000004
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#define RADEON_UPLOAD_BUMPMAP 0x00000008
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#define RADEON_UPLOAD_MASKS 0x00000010
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#define RADEON_UPLOAD_VIEWPORT 0x00000020
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#define RADEON_UPLOAD_SETUP 0x00000040
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#define RADEON_UPLOAD_TCL 0x00000080
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#define RADEON_UPLOAD_MISC 0x00000100
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#define RADEON_UPLOAD_TEX0 0x00000200
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#define RADEON_UPLOAD_TEX1 0x00000400
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#define RADEON_UPLOAD_TEX2 0x00000800
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#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
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#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
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#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
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#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
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#define RADEON_REQUIRE_QUIESCENCE 0x00010000
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#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
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#define RADEON_UPLOAD_ALL 0x003effff
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#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
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/* New style per-packet identifiers for use in cmd_buffer ioctl with
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* the RADEON_EMIT_PACKET command. Comments relate new packets to old
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* state bits and the packet size:
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*/
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#define RADEON_EMIT_PP_MISC 0 /* context/7 */
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#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
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#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
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#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
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#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
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#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
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#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
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#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
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#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
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#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
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#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
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#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
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#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
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#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
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#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
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#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
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#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
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#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
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#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
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#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
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#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
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#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
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#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
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#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
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#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
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#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
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#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
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#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
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#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
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#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
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#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
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#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
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#define R200_EMIT_VAP_CTL 32 /* vap/1 */
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#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
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#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
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#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
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#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
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#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
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#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
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#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
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#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
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#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
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#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
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#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
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#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
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#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
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#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
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#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
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#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
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#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
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#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
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#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
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#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
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#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
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#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
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#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
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#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
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#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
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#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
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#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
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#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
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#define R200_EMIT_PP_CUBIC_FACES_0 61
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#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
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#define R200_EMIT_PP_CUBIC_FACES_1 63
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#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
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#define R200_EMIT_PP_CUBIC_FACES_2 65
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#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
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#define R200_EMIT_PP_CUBIC_FACES_3 67
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#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
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#define R200_EMIT_PP_CUBIC_FACES_4 69
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#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
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#define R200_EMIT_PP_CUBIC_FACES_5 71
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#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
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#define RADEON_EMIT_PP_TEX_SIZE_0 73
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#define RADEON_EMIT_PP_TEX_SIZE_1 74
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#define RADEON_EMIT_PP_TEX_SIZE_2 75
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#define R200_EMIT_RB3D_BLENDCOLOR 76
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#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
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#define RADEON_EMIT_PP_CUBIC_FACES_0 78
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#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
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#define RADEON_EMIT_PP_CUBIC_FACES_1 80
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#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
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#define RADEON_EMIT_PP_CUBIC_FACES_2 82
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#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
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#define R200_EMIT_PP_TRI_PERF_CNTL 84
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#define R200_EMIT_PP_AFS_0 85
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#define R200_EMIT_PP_AFS_1 86
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#define R200_EMIT_ATF_TFACTOR 87
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#define R200_EMIT_PP_TXCTLALL_0 88
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#define R200_EMIT_PP_TXCTLALL_1 89
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#define R200_EMIT_PP_TXCTLALL_2 90
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#define R200_EMIT_PP_TXCTLALL_3 91
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#define R200_EMIT_PP_TXCTLALL_4 92
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#define R200_EMIT_PP_TXCTLALL_5 93
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#define R200_EMIT_VAP_PVS_CNTL 94
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#define RADEON_MAX_STATE_PACKETS 95
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/* Commands understood by cmd_buffer ioctl. More can be added but
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* obviously these can't be removed or changed:
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*/
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#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
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#define RADEON_CMD_SCALARS 2 /* emit scalar data */
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#define RADEON_CMD_VECTORS 3 /* emit vector data */
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#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
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#define RADEON_CMD_PACKET3 5 /* emit hw packet */
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#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
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#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
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#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
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* doesn't make the cpu wait, just
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* the graphics hardware */
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#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
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typedef union {
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int i;
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struct {
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unsigned char cmd_type, pad0, pad1, pad2;
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} header;
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struct {
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unsigned char cmd_type, packet_id, pad0, pad1;
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} packet;
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struct {
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unsigned char cmd_type, offset, stride, count;
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} scalars;
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struct {
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unsigned char cmd_type, offset, stride, count;
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} vectors;
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struct {
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unsigned char cmd_type, addr_lo, addr_hi, count;
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} veclinear;
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struct {
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unsigned char cmd_type, buf_idx, pad0, pad1;
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} dma;
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struct {
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unsigned char cmd_type, flags, pad0, pad1;
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} wait;
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} drm_radeon_cmd_header_t;
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#define RADEON_WAIT_2D 0x1
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#define RADEON_WAIT_3D 0x2
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/* Allowed parameters for R300_CMD_PACKET3
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*/
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#define R300_CMD_PACKET3_CLEAR 0
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#define R300_CMD_PACKET3_RAW 1
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/* Commands understood by cmd_buffer ioctl for R300.
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* The interface has not been stabilized, so some of these may be removed
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* and eventually reordered before stabilization.
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*/
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#define R300_CMD_PACKET0 1
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#define R300_CMD_VPU 2 /* emit vertex program upload */
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#define R300_CMD_PACKET3 3 /* emit a packet3 */
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#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
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#define R300_CMD_CP_DELAY 5
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#define R300_CMD_DMA_DISCARD 6
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#define R300_CMD_WAIT 7
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# define R300_WAIT_2D 0x1
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# define R300_WAIT_3D 0x2
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/* these two defines are DOING IT WRONG - however
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* we have userspace which relies on using these.
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* The wait interface is backwards compat new
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* code should use the NEW_WAIT defines below
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* THESE ARE NOT BIT FIELDS
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*/
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# define R300_WAIT_2D_CLEAN 0x3
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# define R300_WAIT_3D_CLEAN 0x4
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# define R300_NEW_WAIT_2D_3D 0x3
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# define R300_NEW_WAIT_2D_2D_CLEAN 0x4
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# define R300_NEW_WAIT_3D_3D_CLEAN 0x6
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# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
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#define R300_CMD_SCRATCH 8
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#define R300_CMD_R500FP 9
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typedef union {
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unsigned int u;
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struct {
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unsigned char cmd_type, pad0, pad1, pad2;
249
} header;
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struct {
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unsigned char cmd_type, count, reglo, reghi;
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} packet0;
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struct {
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unsigned char cmd_type, count, adrlo, adrhi;
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} vpu;
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struct {
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unsigned char cmd_type, packet, pad0, pad1;
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} packet3;
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struct {
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unsigned char cmd_type, packet;
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unsigned short count; /* amount of packet2 to emit */
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} delay;
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struct {
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unsigned char cmd_type, buf_idx, pad0, pad1;
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} dma;
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struct {
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unsigned char cmd_type, flags, pad0, pad1;
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} wait;
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struct {
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unsigned char cmd_type, reg, n_bufs, flags;
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} scratch;
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struct {
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unsigned char cmd_type, count, adrlo, adrhi_flags;
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} r500fp;
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} drm_r300_cmd_header_t;
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#define RADEON_FRONT 0x1
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#define RADEON_BACK 0x2
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#define RADEON_DEPTH 0x4
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#define RADEON_STENCIL 0x8
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#define RADEON_CLEAR_FASTZ 0x80000000
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#define RADEON_USE_HIERZ 0x40000000
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#define RADEON_USE_COMP_ZBUF 0x20000000
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#define R500FP_CONSTANT_TYPE (1 << 1)
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#define R500FP_CONSTANT_CLAMP (1 << 2)
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/* Primitive types
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*/
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#define RADEON_POINTS 0x1
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#define RADEON_LINES 0x2
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#define RADEON_LINE_STRIP 0x3
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#define RADEON_TRIANGLES 0x4
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#define RADEON_TRIANGLE_FAN 0x5
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#define RADEON_TRIANGLE_STRIP 0x6
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/* Vertex/indirect buffer size
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*/
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#define RADEON_BUFFER_SIZE 65536
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/* Byte offsets for indirect buffer data
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*/
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#define RADEON_INDEX_PRIM_OFFSET 20
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#define RADEON_SCRATCH_REG_OFFSET 32
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#define R600_SCRATCH_REG_OFFSET 256
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#define RADEON_NR_SAREA_CLIPRECTS 12
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/* There are 2 heaps (local/GART). Each region within a heap is a
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* minimum of 64k, and there are at most 64 of them per heap.
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*/
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#define RADEON_LOCAL_TEX_HEAP 0
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#define RADEON_GART_TEX_HEAP 1
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#define RADEON_NR_TEX_HEAPS 2
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#define RADEON_NR_TEX_REGIONS 64
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#define RADEON_LOG_TEX_GRANULARITY 16
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#define RADEON_MAX_TEXTURE_LEVELS 12
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#define RADEON_MAX_TEXTURE_UNITS 3
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#define RADEON_MAX_SURFACES 8
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/* Blits have strict offset rules. All blit offset must be aligned on
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* a 1K-byte boundary.
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*/
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#define RADEON_OFFSET_SHIFT 10
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#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
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#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
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#endif /* __RADEON_SAREA_DEFINES__ */
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typedef struct {
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unsigned int red;
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unsigned int green;
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unsigned int blue;
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unsigned int alpha;
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} radeon_color_regs_t;
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typedef struct {
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/* Context state */
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unsigned int pp_misc; /* 0x1c14 */
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unsigned int pp_fog_color;
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unsigned int re_solid_color;
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unsigned int rb3d_blendcntl;
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unsigned int rb3d_depthoffset;
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unsigned int rb3d_depthpitch;
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unsigned int rb3d_zstencilcntl;
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unsigned int pp_cntl; /* 0x1c38 */
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unsigned int rb3d_cntl;
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unsigned int rb3d_coloroffset;
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unsigned int re_width_height;
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unsigned int rb3d_colorpitch;
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unsigned int se_cntl;
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/* Vertex format state */
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unsigned int se_coord_fmt; /* 0x1c50 */
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/* Line state */
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unsigned int re_line_pattern; /* 0x1cd0 */
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unsigned int re_line_state;
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unsigned int se_line_width; /* 0x1db8 */
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/* Bumpmap state */
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unsigned int pp_lum_matrix; /* 0x1d00 */
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unsigned int pp_rot_matrix_0; /* 0x1d58 */
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unsigned int pp_rot_matrix_1;
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/* Mask state */
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unsigned int rb3d_stencilrefmask; /* 0x1d7c */
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unsigned int rb3d_ropcntl;
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unsigned int rb3d_planemask;
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/* Viewport state */
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unsigned int se_vport_xscale; /* 0x1d98 */
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unsigned int se_vport_xoffset;
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unsigned int se_vport_yscale;
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unsigned int se_vport_yoffset;
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unsigned int se_vport_zscale;
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unsigned int se_vport_zoffset;
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/* Setup state */
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unsigned int se_cntl_status; /* 0x2140 */
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/* Misc state */
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unsigned int re_top_left; /* 0x26c0 */
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unsigned int re_misc;
391
} drm_radeon_context_regs_t;
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393
typedef struct {
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/* Zbias state */
395
unsigned int se_zbias_factor; /* 0x1dac */
396
unsigned int se_zbias_constant;
397
} drm_radeon_context2_regs_t;
398
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/* Setup registers for each texture unit
400
*/
401
typedef struct {
402
unsigned int pp_txfilter;
403
unsigned int pp_txformat;
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unsigned int pp_txoffset;
405
unsigned int pp_txcblend;
406
unsigned int pp_txablend;
407
unsigned int pp_tfactor;
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unsigned int pp_border_color;
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} drm_radeon_texture_regs_t;
410
411
typedef struct {
412
unsigned int start;
413
unsigned int finish;
414
unsigned int prim:8;
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unsigned int stateidx:8;
416
unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
417
unsigned int vc_format; /* vertex format */
418
} drm_radeon_prim_t;
419
420
typedef struct {
421
drm_radeon_context_regs_t context;
422
drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
423
drm_radeon_context2_regs_t context2;
424
unsigned int dirty;
425
} drm_radeon_state_t;
426
427
typedef struct {
428
/* The channel for communication of state information to the
429
* kernel on firing a vertex buffer with either of the
430
* obsoleted vertex/index ioctls.
431
*/
432
drm_radeon_context_regs_t context_state;
433
drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
434
unsigned int dirty;
435
unsigned int vertsize;
436
unsigned int vc_format;
437
438
/* The current cliprects, or a subset thereof.
439
*/
440
struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
441
unsigned int nbox;
442
443
/* Counters for client-side throttling of rendering clients.
444
*/
445
unsigned int last_frame;
446
unsigned int last_dispatch;
447
unsigned int last_clear;
448
449
struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
450
1];
451
unsigned int tex_age[RADEON_NR_TEX_HEAPS];
452
int ctx_owner;
453
int pfState; /* number of 3d windows (0,1,2ormore) */
454
int pfCurrentPage; /* which buffer is being displayed? */
455
int crtc2_base; /* CRTC2 frame offset */
456
int tiling_enabled; /* set by drm, read by 2d + 3d clients */
457
} drm_radeon_sarea_t;
458
459
/* WARNING: If you change any of these defines, make sure to change the
460
* defines in the Xserver file (xf86drmRadeon.h)
461
*
462
* KW: actually it's illegal to change any of this (backwards compatibility).
463
*/
464
465
/* Radeon specific ioctls
466
* The device specific ioctl range is 0x40 to 0x79.
467
*/
468
#define DRM_RADEON_CP_INIT 0x00
469
#define DRM_RADEON_CP_START 0x01
470
#define DRM_RADEON_CP_STOP 0x02
471
#define DRM_RADEON_CP_RESET 0x03
472
#define DRM_RADEON_CP_IDLE 0x04
473
#define DRM_RADEON_RESET 0x05
474
#define DRM_RADEON_FULLSCREEN 0x06
475
#define DRM_RADEON_SWAP 0x07
476
#define DRM_RADEON_CLEAR 0x08
477
#define DRM_RADEON_VERTEX 0x09
478
#define DRM_RADEON_INDICES 0x0A
479
#define DRM_RADEON_NOT_USED
480
#define DRM_RADEON_STIPPLE 0x0C
481
#define DRM_RADEON_INDIRECT 0x0D
482
#define DRM_RADEON_TEXTURE 0x0E
483
#define DRM_RADEON_VERTEX2 0x0F
484
#define DRM_RADEON_CMDBUF 0x10
485
#define DRM_RADEON_GETPARAM 0x11
486
#define DRM_RADEON_FLIP 0x12
487
#define DRM_RADEON_ALLOC 0x13
488
#define DRM_RADEON_FREE 0x14
489
#define DRM_RADEON_INIT_HEAP 0x15
490
#define DRM_RADEON_IRQ_EMIT 0x16
491
#define DRM_RADEON_IRQ_WAIT 0x17
492
#define DRM_RADEON_CP_RESUME 0x18
493
#define DRM_RADEON_SETPARAM 0x19
494
#define DRM_RADEON_SURF_ALLOC 0x1a
495
#define DRM_RADEON_SURF_FREE 0x1b
496
/* KMS ioctl */
497
#define DRM_RADEON_GEM_INFO 0x1c
498
#define DRM_RADEON_GEM_CREATE 0x1d
499
#define DRM_RADEON_GEM_MMAP 0x1e
500
#define DRM_RADEON_GEM_PREAD 0x21
501
#define DRM_RADEON_GEM_PWRITE 0x22
502
#define DRM_RADEON_GEM_SET_DOMAIN 0x23
503
#define DRM_RADEON_GEM_WAIT_IDLE 0x24
504
#define DRM_RADEON_CS 0x26
505
#define DRM_RADEON_INFO 0x27
506
#define DRM_RADEON_GEM_SET_TILING 0x28
507
#define DRM_RADEON_GEM_GET_TILING 0x29
508
#define DRM_RADEON_GEM_BUSY 0x2a
509
510
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
511
#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
512
#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
513
#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
514
#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
515
#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
516
#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
517
#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
518
#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
519
#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
520
#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
521
#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
522
#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
523
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
524
#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
525
#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
526
#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
527
#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
528
#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
529
#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
530
#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
531
#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
532
#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
533
#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
534
#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
535
#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
536
#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
537
/* KMS */
538
#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
539
#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
540
#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
541
#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
542
#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
543
#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
544
#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
545
#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
546
#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
547
#define DRM_IOCTL_RADEON_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
548
#define DRM_IOCTL_RADEON_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
549
#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
550
551
typedef struct drm_radeon_init {
552
enum {
553
RADEON_INIT_CP = 0x01,
554
RADEON_CLEANUP_CP = 0x02,
555
RADEON_INIT_R200_CP = 0x03,
556
RADEON_INIT_R300_CP = 0x04,
557
RADEON_INIT_R600_CP = 0x05
558
} func;
559
unsigned long sarea_priv_offset;
560
int is_pci; /* for overriding only */
561
int cp_mode;
562
int gart_size;
563
int ring_size;
564
int usec_timeout;
565
566
unsigned int fb_bpp;
567
unsigned int front_offset, front_pitch;
568
unsigned int back_offset, back_pitch;
569
unsigned int depth_bpp;
570
unsigned int depth_offset, depth_pitch;
571
572
unsigned long fb_offset DEPRECATED; /* deprecated, driver asks hardware */
573
unsigned long mmio_offset DEPRECATED; /* deprecated, driver asks hardware */
574
unsigned long ring_offset;
575
unsigned long ring_rptr_offset;
576
unsigned long buffers_offset;
577
unsigned long gart_textures_offset;
578
} drm_radeon_init_t;
579
580
typedef struct drm_radeon_cp_stop {
581
int flush;
582
int idle;
583
} drm_radeon_cp_stop_t;
584
585
typedef struct drm_radeon_fullscreen {
586
enum {
587
RADEON_INIT_FULLSCREEN = 0x01,
588
RADEON_CLEANUP_FULLSCREEN = 0x02
589
} func;
590
} drm_radeon_fullscreen_t;
591
592
#define CLEAR_X1 0
593
#define CLEAR_Y1 1
594
#define CLEAR_X2 2
595
#define CLEAR_Y2 3
596
#define CLEAR_DEPTH 4
597
598
typedef union drm_radeon_clear_rect {
599
float f[5];
600
unsigned int ui[5];
601
} drm_radeon_clear_rect_t;
602
603
typedef struct drm_radeon_clear {
604
unsigned int flags;
605
unsigned int clear_color;
606
unsigned int clear_depth;
607
unsigned int color_mask;
608
unsigned int depth_mask; /* misnamed field: should be stencil */
609
drm_radeon_clear_rect_t __user *depth_boxes;
610
} drm_radeon_clear_t;
611
612
typedef struct drm_radeon_vertex {
613
int prim;
614
int idx; /* Index of vertex buffer */
615
int count; /* Number of vertices in buffer */
616
int discard; /* Client finished with buffer? */
617
} drm_radeon_vertex_t;
618
619
typedef struct drm_radeon_indices {
620
int prim;
621
int idx;
622
int start;
623
int end;
624
int discard; /* Client finished with buffer? */
625
} drm_radeon_indices_t;
626
627
/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
628
* - allows multiple primitives and state changes in a single ioctl
629
* - supports driver change to emit native primitives
630
*/
631
typedef struct drm_radeon_vertex2 {
632
int idx; /* Index of vertex buffer */
633
int discard; /* Client finished with buffer? */
634
int nr_states;
635
drm_radeon_state_t __user *state;
636
int nr_prims;
637
drm_radeon_prim_t __user *prim;
638
} drm_radeon_vertex2_t;
639
640
/* v1.3 - obsoletes drm_radeon_vertex2
641
* - allows arbitarily large cliprect list
642
* - allows updating of tcl packet, vector and scalar state
643
* - allows memory-efficient description of state updates
644
* - allows state to be emitted without a primitive
645
* (for clears, ctx switches)
646
* - allows more than one dma buffer to be referenced per ioctl
647
* - supports tcl driver
648
* - may be extended in future versions with new cmd types, packets
649
*/
650
typedef struct drm_radeon_cmd_buffer {
651
int bufsz;
652
char __user *buf;
653
int nbox;
654
struct drm_clip_rect __user *boxes;
655
} drm_radeon_cmd_buffer_t;
656
657
typedef struct drm_radeon_tex_image {
658
unsigned int x, y; /* Blit coordinates */
659
unsigned int width, height;
660
const void __user *data;
661
} drm_radeon_tex_image_t;
662
663
typedef struct drm_radeon_texture {
664
unsigned int offset;
665
int pitch;
666
int format;
667
int width; /* Texture image coordinates */
668
int height;
669
drm_radeon_tex_image_t __user *image;
670
} drm_radeon_texture_t;
671
672
typedef struct drm_radeon_stipple {
673
unsigned int __user *mask;
674
} drm_radeon_stipple_t;
675
676
typedef struct drm_radeon_indirect {
677
int idx;
678
int start;
679
int end;
680
int discard;
681
} drm_radeon_indirect_t;
682
683
/* enum for card type parameters */
684
#define RADEON_CARD_PCI 0
685
#define RADEON_CARD_AGP 1
686
#define RADEON_CARD_PCIE 2
687
688
/* 1.3: An ioctl to get parameters that aren't available to the 3d
689
* client any other way.
690
*/
691
#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
692
#define RADEON_PARAM_LAST_FRAME 2
693
#define RADEON_PARAM_LAST_DISPATCH 3
694
#define RADEON_PARAM_LAST_CLEAR 4
695
/* Added with DRM version 1.6. */
696
#define RADEON_PARAM_IRQ_NR 5
697
#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
698
/* Added with DRM version 1.8. */
699
#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
700
#define RADEON_PARAM_STATUS_HANDLE 8
701
#define RADEON_PARAM_SAREA_HANDLE 9
702
#define RADEON_PARAM_GART_TEX_HANDLE 10
703
#define RADEON_PARAM_SCRATCH_OFFSET 11
704
#define RADEON_PARAM_CARD_TYPE 12
705
#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
706
#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
707
#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
708
#define RADEON_PARAM_DEVICE_ID 16
709
#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */
710
711
typedef struct drm_radeon_getparam {
712
int param;
713
void __user *value;
714
} drm_radeon_getparam_t;
715
716
/* 1.6: Set up a memory manager for regions of shared memory:
717
*/
718
#define RADEON_MEM_REGION_GART 1
719
#define RADEON_MEM_REGION_FB 2
720
721
typedef struct drm_radeon_mem_alloc {
722
int region;
723
int alignment;
724
int size;
725
int __user *region_offset; /* offset from start of fb or GART */
726
} drm_radeon_mem_alloc_t;
727
728
typedef struct drm_radeon_mem_free {
729
int region;
730
int region_offset;
731
} drm_radeon_mem_free_t;
732
733
typedef struct drm_radeon_mem_init_heap {
734
int region;
735
int size;
736
int start;
737
} drm_radeon_mem_init_heap_t;
738
739
/* 1.6: Userspace can request & wait on irq's:
740
*/
741
typedef struct drm_radeon_irq_emit {
742
int __user *irq_seq;
743
} drm_radeon_irq_emit_t;
744
745
typedef struct drm_radeon_irq_wait {
746
int irq_seq;
747
} drm_radeon_irq_wait_t;
748
749
/* 1.10: Clients tell the DRM where they think the framebuffer is located in
750
* the card's address space, via a new generic ioctl to set parameters
751
*/
752
753
typedef struct drm_radeon_setparam {
754
unsigned int param;
755
int64_t value;
756
} drm_radeon_setparam_t;
757
758
#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
759
#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
760
#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
761
#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
762
#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
763
#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
764
/* 1.14: Clients can allocate/free a surface
765
*/
766
typedef struct drm_radeon_surface_alloc {
767
unsigned int address;
768
unsigned int size;
769
unsigned int flags;
770
} drm_radeon_surface_alloc_t;
771
772
typedef struct drm_radeon_surface_free {
773
unsigned int address;
774
} drm_radeon_surface_free_t;
775
776
#define DRM_RADEON_VBLANK_CRTC1 1
777
#define DRM_RADEON_VBLANK_CRTC2 2
778
779
/*
780
* Kernel modesetting world below.
781
*/
782
#define RADEON_GEM_DOMAIN_CPU 0x1
783
#define RADEON_GEM_DOMAIN_GTT 0x2
784
#define RADEON_GEM_DOMAIN_VRAM 0x4
785
786
struct drm_radeon_gem_info {
787
uint64_t gart_size;
788
uint64_t vram_size;
789
uint64_t vram_visible;
790
};
791
792
#define RADEON_GEM_NO_BACKING_STORE 1
793
794
struct drm_radeon_gem_create {
795
uint64_t size;
796
uint64_t alignment;
797
uint32_t handle;
798
uint32_t initial_domain;
799
uint32_t flags;
800
};
801
802
#define RADEON_TILING_MACRO 0x1
803
#define RADEON_TILING_MICRO 0x2
804
#define RADEON_TILING_SWAP 0x4
805
#define RADEON_TILING_SURFACE 0x8 /* this object requires a surface
806
* when mapped - i.e. front buffer */
807
808
struct drm_radeon_gem_set_tiling {
809
uint32_t handle;
810
uint32_t tiling_flags;
811
uint32_t pitch;
812
};
813
814
struct drm_radeon_gem_get_tiling {
815
uint32_t handle;
816
uint32_t tiling_flags;
817
uint32_t pitch;
818
};
819
820
struct drm_radeon_gem_mmap {
821
uint32_t handle;
822
uint32_t pad;
823
uint64_t offset;
824
uint64_t size;
825
uint64_t addr_ptr;
826
};
827
828
struct drm_radeon_gem_set_domain {
829
uint32_t handle;
830
uint32_t read_domains;
831
uint32_t write_domain;
832
};
833
834
struct drm_radeon_gem_wait_idle {
835
uint32_t handle;
836
uint32_t pad;
837
};
838
839
struct drm_radeon_gem_busy {
840
uint32_t handle;
841
uint32_t domain;
842
};
843
844
struct drm_radeon_gem_pread {
845
/** Handle for the object being read. */
846
uint32_t handle;
847
uint32_t pad;
848
/** Offset into the object to read from */
849
uint64_t offset;
850
/** Length of data to read */
851
uint64_t size;
852
/** Pointer to write the data into. */
853
/* void *, but pointers are not 32/64 compatible */
854
uint64_t data_ptr;
855
};
856
857
struct drm_radeon_gem_pwrite {
858
/** Handle for the object being written to. */
859
uint32_t handle;
860
uint32_t pad;
861
/** Offset into the object to write to */
862
uint64_t offset;
863
/** Length of data to write */
864
uint64_t size;
865
/** Pointer to read the data from. */
866
/* void *, but pointers are not 32/64 compatible */
867
uint64_t data_ptr;
868
};
869
870
#define RADEON_CHUNK_ID_RELOCS 0x01
871
#define RADEON_CHUNK_ID_IB 0x02
872
873
struct drm_radeon_cs_chunk {
874
uint32_t chunk_id;
875
uint32_t length_dw;
876
uint64_t chunk_data;
877
};
878
879
struct drm_radeon_cs_reloc {
880
uint32_t handle;
881
uint32_t read_domains;
882
uint32_t write_domain;
883
uint32_t flags;
884
};
885
886
struct drm_radeon_cs {
887
uint32_t num_chunks;
888
uint32_t cs_id;
889
/* this points to uint64_t * which point to cs chunks */
890
uint64_t chunks;
891
/* updates to the limits after this CS ioctl */
892
uint64_t gart_limit;
893
uint64_t vram_limit;
894
};
895
896
#define RADEON_INFO_DEVICE_ID 0x00
897
#define RADEON_INFO_NUM_GB_PIPES 0x01
898
#define RADEON_INFO_NUM_Z_PIPES 0x02
899
900
struct drm_radeon_info {
901
uint32_t request;
902
uint32_t pad;
903
uint64_t value;
904
};
905
906
#endif
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