2
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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/* Please note that modifications to all structs defined here are
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* subject to backwards-compatibility constraints.
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/* Each region is a minimum of 16k, and there are at most 255 of them.
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#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
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* of chars for next/prev indices */
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#define I915_LOG_MIN_TEX_REGION_SIZE 14
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typedef struct _drm_i915_init {
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I915_CLEANUP_DMA = 0x02,
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I915_RESUME_DMA = 0x03,
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/* Since this struct isn't versioned, just used a new
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* 'func' code to indicate the presence of dri2 sarea
53
unsigned int mmio_offset;
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int sarea_priv_offset;
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unsigned int ring_start;
56
unsigned int ring_end;
57
unsigned int ring_size;
58
unsigned int front_offset;
59
unsigned int back_offset;
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unsigned int depth_offset;
64
unsigned int pitch_bits;
65
unsigned int back_pitch;
66
unsigned int depth_pitch;
69
unsigned int sarea_handle;
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typedef struct drm_i915_sarea {
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struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
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int last_upload; /* last time texture was uploaded */
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int last_enqueue; /* last time a buffer was enqueued */
76
int last_dispatch; /* age of the most recently dispatched buffer */
77
int ctxOwner; /* last context to upload state */
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int pf_enabled; /* is pageflipping allowed? */
81
int pf_current_page; /* which buffer is being displayed? */
82
int perf_boxes; /* performance boxes to be displayed */
83
int width, height; /* screen size in pixels */
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drm_handle_t front_handle;
89
drm_handle_t back_handle;
93
drm_handle_t depth_handle;
97
drm_handle_t tex_handle;
100
int log_tex_granularity;
102
int rotation; /* 0, 90, 180 or 270 */
106
int virtualX, virtualY;
108
unsigned int front_tiled;
109
unsigned int back_tiled;
110
unsigned int depth_tiled;
111
unsigned int rotated_tiled;
112
unsigned int rotated2_tiled;
114
/* compat defines for the period of time when pipeA_* got renamed
115
* to planeA_*. They mean pipe, really.
117
#define planeA_x pipeA_x
118
#define planeA_y pipeA_y
119
#define planeA_w pipeA_w
120
#define planeA_h pipeA_h
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#define planeB_x pipeB_x
122
#define planeB_y pipeB_y
123
#define planeB_w pipeB_w
124
#define planeB_h pipeB_h
134
/* Triple buffering */
135
drm_handle_t third_handle;
138
unsigned int third_tiled;
140
/* buffer object handles for the static buffers. May change
141
* over the lifetime of the client, though it doesn't in our current
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unsigned int front_bo_handle;
145
unsigned int back_bo_handle;
146
unsigned int third_bo_handle;
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unsigned int depth_bo_handle;
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/* Driver specific fence types and classes.
153
/* The only fence class we support */
154
#define DRM_I915_FENCE_CLASS_ACCEL 0
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/* Fence type that guarantees read-write flush */
156
#define DRM_I915_FENCE_TYPE_RW 2
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/* MI_FLUSH programmed just before the fence */
158
#define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000
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/* Flags for perf_boxes
162
#define I915_BOX_RING_EMPTY 0x1
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#define I915_BOX_FLIP 0x2
164
#define I915_BOX_WAIT 0x4
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#define I915_BOX_TEXTURE_LOAD 0x8
166
#define I915_BOX_LOST_CONTEXT 0x10
168
/* I915 specific ioctls
169
* The device specific ioctl range is 0x40 to 0x79.
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#define DRM_I915_INIT 0x00
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#define DRM_I915_FLUSH 0x01
173
#define DRM_I915_FLIP 0x02
174
#define DRM_I915_BATCHBUFFER 0x03
175
#define DRM_I915_IRQ_EMIT 0x04
176
#define DRM_I915_IRQ_WAIT 0x05
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#define DRM_I915_GETPARAM 0x06
178
#define DRM_I915_SETPARAM 0x07
179
#define DRM_I915_ALLOC 0x08
180
#define DRM_I915_FREE 0x09
181
#define DRM_I915_INIT_HEAP 0x0a
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#define DRM_I915_CMDBUFFER 0x0b
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#define DRM_I915_DESTROY_HEAP 0x0c
184
#define DRM_I915_SET_VBLANK_PIPE 0x0d
185
#define DRM_I915_GET_VBLANK_PIPE 0x0e
186
#define DRM_I915_VBLANK_SWAP 0x0f
187
#define DRM_I915_MMIO 0x10
188
#define DRM_I915_HWS_ADDR 0x11
189
#define DRM_I915_EXECBUFFER 0x12
190
#define DRM_I915_GEM_INIT 0x13
191
#define DRM_I915_GEM_EXECBUFFER 0x14
192
#define DRM_I915_GEM_PIN 0x15
193
#define DRM_I915_GEM_UNPIN 0x16
194
#define DRM_I915_GEM_BUSY 0x17
195
#define DRM_I915_GEM_THROTTLE 0x18
196
#define DRM_I915_GEM_ENTERVT 0x19
197
#define DRM_I915_GEM_LEAVEVT 0x1a
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#define DRM_I915_GEM_CREATE 0x1b
199
#define DRM_I915_GEM_PREAD 0x1c
200
#define DRM_I915_GEM_PWRITE 0x1d
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#define DRM_I915_GEM_MMAP 0x1e
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#define DRM_I915_GEM_SET_DOMAIN 0x1f
203
#define DRM_I915_GEM_SW_FINISH 0x20
204
#define DRM_I915_GEM_SET_TILING 0x21
205
#define DRM_I915_GEM_GET_TILING 0x22
206
#define DRM_I915_GEM_GET_APERTURE 0x23
207
#define DRM_I915_GEM_MMAP_GTT 0x24
208
#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
210
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
211
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
212
#define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t)
213
#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
214
#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
215
#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
216
#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
217
#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
218
#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
219
#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
220
#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
221
#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
222
#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
223
#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
224
#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
225
#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
226
#define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
227
#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
228
#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
229
#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
230
#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
231
#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
232
#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
233
#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
234
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
235
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
236
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
237
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
238
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
239
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
240
#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
241
#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
242
#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
243
#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
244
#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
245
#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
246
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
248
/* Asynchronous page flipping:
250
typedef struct drm_i915_flip {
252
* This is really talking about planes, and we could rename it
253
* except for the fact that some of the duplicated i915_drm.h files
254
* out there check for HAVE_I915_FLIP and so might pick up this
260
/* Allow drivers to submit batchbuffers directly to hardware, relying
261
* on the security mechanisms provided by hardware.
263
typedef struct drm_i915_batchbuffer {
264
int start; /* agp offset */
265
int used; /* nr bytes in use */
266
int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
267
int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
268
int num_cliprects; /* mulitpass with multiple cliprects? */
269
struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
270
} drm_i915_batchbuffer_t;
272
/* As above, but pass a pointer to userspace buffer which can be
273
* validated by the kernel prior to sending to hardware.
275
typedef struct _drm_i915_cmdbuffer {
276
char __user *buf; /* pointer to userspace command buffer */
277
int sz; /* nr bytes in buf */
278
int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
279
int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
280
int num_cliprects; /* mulitpass with multiple cliprects? */
281
struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
282
} drm_i915_cmdbuffer_t;
284
/* Userspace can request & wait on irq's:
286
typedef struct drm_i915_irq_emit {
288
} drm_i915_irq_emit_t;
290
typedef struct drm_i915_irq_wait {
292
} drm_i915_irq_wait_t;
294
/* Ioctl to query kernel params:
296
#define I915_PARAM_IRQ_ACTIVE 1
297
#define I915_PARAM_ALLOW_BATCHBUFFER 2
298
#define I915_PARAM_LAST_DISPATCH 3
299
#define I915_PARAM_CHIPSET_ID 4
300
#define I915_PARAM_HAS_GEM 5
301
#define I915_PARAM_NUM_FENCES_AVAIL 6
303
typedef struct drm_i915_getparam {
306
} drm_i915_getparam_t;
308
/* Ioctl to set kernel params:
310
#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
311
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
312
#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
313
#define I915_SETPARAM_NUM_USED_FENCES 4
315
typedef struct drm_i915_setparam {
318
} drm_i915_setparam_t;
320
/* A memory manager for regions of shared memory:
322
#define I915_MEM_REGION_AGP 1
324
typedef struct drm_i915_mem_alloc {
328
int __user *region_offset; /* offset from start of fb or agp */
329
} drm_i915_mem_alloc_t;
331
typedef struct drm_i915_mem_free {
334
} drm_i915_mem_free_t;
336
typedef struct drm_i915_mem_init_heap {
340
} drm_i915_mem_init_heap_t;
342
/* Allow memory manager to be torn down and re-initialized (eg on
345
typedef struct drm_i915_mem_destroy_heap {
347
} drm_i915_mem_destroy_heap_t;
349
/* Allow X server to configure which pipes to monitor for vblank signals
351
#define DRM_I915_VBLANK_PIPE_A 1
352
#define DRM_I915_VBLANK_PIPE_B 2
354
typedef struct drm_i915_vblank_pipe {
356
} drm_i915_vblank_pipe_t;
358
/* Schedule buffer swap at given vertical blank:
360
typedef struct drm_i915_vblank_swap {
361
drm_drawable_t drawable;
362
enum drm_vblank_seq_type seqtype;
363
unsigned int sequence;
364
} drm_i915_vblank_swap_t;
366
#define I915_MMIO_READ 0
367
#define I915_MMIO_WRITE 1
369
#define I915_MMIO_MAY_READ 0x1
370
#define I915_MMIO_MAY_WRITE 0x2
372
#define MMIO_REGS_IA_PRIMATIVES_COUNT 0
373
#define MMIO_REGS_IA_VERTICES_COUNT 1
374
#define MMIO_REGS_VS_INVOCATION_COUNT 2
375
#define MMIO_REGS_GS_PRIMITIVES_COUNT 3
376
#define MMIO_REGS_GS_INVOCATION_COUNT 4
377
#define MMIO_REGS_CL_PRIMITIVES_COUNT 5
378
#define MMIO_REGS_CL_INVOCATION_COUNT 6
379
#define MMIO_REGS_PS_INVOCATION_COUNT 7
380
#define MMIO_REGS_PS_DEPTH_COUNT 8
382
typedef struct drm_i915_mmio_entry {
386
} drm_i915_mmio_entry_t;
388
typedef struct drm_i915_mmio {
389
unsigned int read_write:1;
394
typedef struct drm_i915_hws_addr {
396
} drm_i915_hws_addr_t;
398
struct drm_i915_gem_init {
400
* Beginning offset in the GTT to be managed by the DRM memory
405
* Ending offset in the GTT to be managed by the DRM memory
411
struct drm_i915_gem_create {
413
* Requested size for the object.
415
* The (page-aligned) allocated size for the object will be returned.
419
* Returned handle for the object.
421
* Object handles are nonzero.
427
struct drm_i915_gem_pread {
428
/** Handle for the object being read. */
431
/** Offset into the object to read from */
433
/** Length of data to read */
436
* Pointer to write the data into.
438
* This is a fixed-size type for 32/64 compatibility.
443
struct drm_i915_gem_pwrite {
444
/** Handle for the object being written to. */
447
/** Offset into the object to write to */
449
/** Length of data to write */
452
* Pointer to read the data from.
454
* This is a fixed-size type for 32/64 compatibility.
459
struct drm_i915_gem_mmap {
460
/** Handle for the object being mapped. */
463
/** Offset in the object to map. */
466
* Length of data to map.
468
* The value will be page-aligned.
472
* Returned pointer the data was mapped at.
474
* This is a fixed-size type for 32/64 compatibility.
479
struct drm_i915_gem_mmap_gtt {
480
/** Handle for the object being mapped. */
484
* Fake offset to use for subsequent mmap call
486
* This is a fixed-size type for 32/64 compatibility.
491
struct drm_i915_gem_set_domain {
492
/** Handle for the object */
495
/** New read domains */
496
uint32_t read_domains;
498
/** New write domain */
499
uint32_t write_domain;
502
struct drm_i915_gem_sw_finish {
503
/** Handle for the object */
507
struct drm_i915_gem_relocation_entry {
509
* Handle of the buffer being pointed to by this relocation entry.
511
* It's appealing to make this be an index into the mm_validate_entry
512
* list to refer to the buffer, but this allows the driver to create
513
* a relocation list for state buffers and not re-write it per
514
* exec using the buffer.
516
uint32_t target_handle;
519
* Value to be added to the offset of the target buffer to make up
520
* the relocation entry.
524
/** Offset in the buffer the relocation entry will be written into */
528
* Offset value of the target buffer that the relocation entry was last
531
* If the buffer has the same offset as last time, we can skip syncing
532
* and writing the relocation. This value is written back out by
533
* the execbuffer ioctl when the relocation is written.
535
uint64_t presumed_offset;
538
* Target memory domains read by this operation.
540
uint32_t read_domains;
543
* Target memory domains written by this operation.
545
* Note that only one domain may be written by the whole
546
* execbuffer operation, so that where there are conflicts,
547
* the application will get -EINVAL back.
549
uint32_t write_domain;
553
* Intel memory domains
555
* Most of these just align with the various caches in
556
* the system and are used to flush and invalidate as
557
* objects end up cached in different domains.
560
#define I915_GEM_DOMAIN_CPU 0x00000001
561
/** Render cache, used by 2D and 3D drawing */
562
#define I915_GEM_DOMAIN_RENDER 0x00000002
563
/** Sampler cache, used by texture engine */
564
#define I915_GEM_DOMAIN_SAMPLER 0x00000004
565
/** Command queue, used to load batch buffers */
566
#define I915_GEM_DOMAIN_COMMAND 0x00000008
567
/** Instruction cache, used by shader programs */
568
#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
569
/** Vertex address cache */
570
#define I915_GEM_DOMAIN_VERTEX 0x00000020
571
/** GTT domain - aperture and scanout */
572
#define I915_GEM_DOMAIN_GTT 0x00000040
575
struct drm_i915_gem_exec_object {
577
* User's handle for a buffer to be bound into the GTT for this
582
/** Number of relocations to be performed on this buffer */
583
uint32_t relocation_count;
585
* Pointer to array of struct drm_i915_gem_relocation_entry containing
586
* the relocations to be performed in this buffer.
590
/** Required alignment in graphics aperture */
594
* Returned value of the updated offset of the object, for future
595
* presumed_offset writes.
600
struct drm_i915_gem_execbuffer {
602
* List of buffers to be validated with their relocations to be
603
* performend on them.
605
* This is a pointer to an array of struct drm_i915_gem_validate_entry.
607
* These buffers must be listed in an order such that all relocations
608
* a buffer is performing refer to buffers that have already appeared
609
* in the validate list.
611
uint64_t buffers_ptr;
612
uint32_t buffer_count;
614
/** Offset in the batchbuffer to start execution from. */
615
uint32_t batch_start_offset;
616
/** Bytes used in batchbuffer from batch_start_offset */
620
uint32_t num_cliprects;
621
/** This is a struct drm_clip_rect *cliprects */
622
uint64_t cliprects_ptr;
625
struct drm_i915_gem_pin {
626
/** Handle of the buffer to be pinned. */
630
/** alignment required within the aperture */
633
/** Returned GTT offset of the buffer. */
637
struct drm_i915_gem_unpin {
638
/** Handle of the buffer to be unpinned. */
643
struct drm_i915_gem_busy {
644
/** Handle of the buffer to check for busy */
647
/** Return busy status (1 if busy, 0 if idle) */
651
#define I915_TILING_NONE 0
652
#define I915_TILING_X 1
653
#define I915_TILING_Y 2
655
#define I915_BIT_6_SWIZZLE_NONE 0
656
#define I915_BIT_6_SWIZZLE_9 1
657
#define I915_BIT_6_SWIZZLE_9_10 2
658
#define I915_BIT_6_SWIZZLE_9_11 3
659
#define I915_BIT_6_SWIZZLE_9_10_11 4
660
/* Not seen by userland */
661
#define I915_BIT_6_SWIZZLE_UNKNOWN 5
663
struct drm_i915_gem_set_tiling {
664
/** Handle of the buffer to have its tiling state updated */
668
* Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
671
* This value is to be set on request, and will be updated by the
672
* kernel on successful return with the actual chosen tiling layout.
674
* The tiling mode may be demoted to I915_TILING_NONE when the system
675
* has bit 6 swizzling that can't be managed correctly by GEM.
677
* Buffer contents become undefined when changing tiling_mode.
679
uint32_t tiling_mode;
682
* Stride in bytes for the object when in I915_TILING_X or
688
* Returned address bit 6 swizzling required for CPU access through
691
uint32_t swizzle_mode;
694
struct drm_i915_gem_get_tiling {
695
/** Handle of the buffer to get tiling state for. */
699
* Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
702
uint32_t tiling_mode;
705
* Returned address bit 6 swizzling required for CPU access through
708
uint32_t swizzle_mode;
711
struct drm_i915_gem_get_aperture {
712
/** Total size of the aperture used by i915_gem_execbuffer, in bytes */
716
* Available space in the aperture used by i915_gem_execbuffer, in
719
uint64_t aper_available_size;
722
struct drm_i915_get_pipe_from_crtc_id {
723
/** ID of CRTC being requested **/
726
/** pipe of requested CRTC **/
730
#endif /* _I915_DRM_H_ */
added
removed
shared-core/i915_drm.h
