18
18
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21
#include <linux/spinlock.h>
22
22
#include "drivers/kcompat.h"
23
23
#include "drivers/lirc.h"
24
24
#include "drivers/lirc_dev/lirc_dev.h"
26
26
/* hardware address */
27
#define ENE_STATUS 0 /* hardware status - unused */
28
#define ENE_ADDR_HI 1 /* hi byte of register address */
29
#define ENE_ADDR_LO 2 /* low byte of register address */
30
#define ENE_IO 3 /* read/write window */
27
#define ENE_STATUS 0 /* hardware status - unused */
28
#define ENE_ADDR_HI 1 /* hi byte of register address */
29
#define ENE_ADDR_LO 2 /* low byte of register address */
30
#define ENE_IO 3 /* read/write window */
31
31
#define ENE_MAX_IO 4
33
33
/* 8 bytes of samples, divided in 2 halfs*/
34
#define ENE_SAMPLE_BUFFER 0xF8F0 /* regular sample buffer */
35
#define ENE_SAMPLE_SPC_MASK (1 << 7) /* sample is space */
34
#define ENE_SAMPLE_BUFFER 0xF8F0 /* regular sample buffer */
35
#define ENE_SAMPLE_SPC_MASK 0x80 /* sample is space */
36
36
#define ENE_SAMPLE_VALUE_MASK 0x7F
37
37
#define ENE_SAMPLE_OVERFLOW 0x7F
38
38
#define ENE_SAMPLES_SIZE 4
40
40
/* fan input sample buffer */
41
#define ENE_SAMPLE_BUFFER_FAN 0xF8FB /* this buffer holds high byte of */
42
/* each sample of normal buffer */
44
#define ENE_FAN_SMPL_PULS_MSK 0x8000 /* this bit of combined sample */
45
/* if set, says that sample is pulse */
46
#define ENE_FAN_VALUE_MASK 0x0FFF /* mask for valid bits of the value */
41
#define ENE_SAMPLE_BUFFER_FAN 0xF8FB /* this buffer holds high byte of */
42
/* each sample of normal buffer */
43
#define ENE_FAN_SMPL_PULS_MSK 0x8000 /* this bit of combined sample */
44
/* if set, says that sample is pulse */
45
#define ENE_FAN_VALUE_MASK 0x0FFF /* mask for valid bits of the value */
48
47
/* first firmware register */
49
48
#define ENE_FW1 0xF8F8
50
#define ENE_FW1_ENABLE (1 << 0) /* enable fw processing */
51
#define ENE_FW1_TXIRQ (1 << 1) /* TX interrupt pending */
52
#define ENE_FW1_WAKE (1 << 6) /* enable wake from S3 */
53
#define ENE_FW1_IRQ (1 << 7) /* enable interrupt */
49
#define ENE_FW1_ENABLE 0x01 /* enable fw processing */
50
#define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */
51
#define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
52
#define ENE_FW1_IRQ 0x80 /* enable interrupt */
55
54
/* second firmware register */
56
55
#define ENE_FW2 0xF8F9
57
#define ENE_FW2_BUF_HIGH (1 << 0) /* which half of the buffer to read */
58
#define ENE_FW2_IRQ_CLR (1 << 2) /* clear this on IRQ */
59
#define ENE_FW2_GP40_AS_LEARN (1 << 4) /* normal input is used as */
61
#define ENE_FW2_FAN_AS_NRML_IN (1 << 6) /* fan is used as normal input */
62
#define ENE_FW2_LEARNING (1 << 7) /* hardware supports learning and TX */
56
#define ENE_FW2_BUF_HIGH 0x01 /* which half of the buffer to read */
57
#define ENE_FW2_IRQ_CLR 0x04 /* clear this on IRQ */
58
#define ENE_FW2_GP40_AS_LEARN 0x08 /* normal input is used as */
60
#define ENE_FW2_FAN_AS_NRML_IN 0x40 /* fan is used as normal input */
61
#define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */
63
/* transmitter ports */
64
#define ENE_TX_PORT2 0xFC01 /* this enables one or both */
65
#define ENE_TX_PORT2_EN 0x20 /* TX ports */
66
#define ENE_TX_PORT1 0xFC08
67
#define ENE_TX_PORT1_EN 0x02
69
/* IRQ registers block (for revision B) */
70
#define ENEB_IRQ 0xFD09 /* IRQ number */
71
#define ENEB_IRQ_UNK1 0xFD17 /* unknown setting = 1 */
72
#define ENEB_IRQ_STATUS 0xFD80 /* irq status */
73
#define ENEB_IRQ_STATUS_IR 0x20 /* IR irq */
64
75
/* fan as input settings - only if learning capable */
65
#define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */
76
#define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */
66
77
#define ENE_FAN_AS_IN1_EN 0xCD
67
#define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */
78
#define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */
68
79
#define ENE_FAN_AS_IN2_EN 0x03
69
#define ENE_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
71
/* IRQ registers block (for revision B) */
72
#define ENEB_IRQ 0xFD09 /* IRQ number */
73
#define ENEB_IRQ_UNK1 0xFD17 /* unknown setting = 1 */
74
#define ENEB_IRQ_STATUS 0xFD80 /* irq status */
75
#define ENEB_IRQ_STATUS_IR (1 << 5) /* IR irq */
80
#define ENE_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
77
82
/* IRQ registers block (for revision C,D) */
78
#define ENEC_IRQ 0xFE9B /* new irq settings register */
79
#define ENEC_IRQ_MASK 0x0F /* irq number mask */
80
#define ENEC_IRQ_UNK_EN (1 << 4) /* always enabled */
81
#define ENEC_IRQ_STATUS (1 << 5) /* irq status and ACK */
83
#define ENEC_IRQ 0xFE9B /* new irq settings register */
84
#define ENEC_IRQ_MASK 0x0F /* irq number mask */
85
#define ENEC_IRQ_UNK_EN 0x10 /* always enabled */
86
#define ENEC_IRQ_STATUS 0x20 /* irq status and ACK */
83
88
/* CIR block settings */
84
89
#define ENE_CIR_CONF1 0xFEC0
85
#define ENE_CIR_CONF1_ADC_ON 0x7 /* reciever on gpio40 enabled */
86
#define ENE_CIR_CONF1_LEARN1 (1 << 3) /* enabled on learning mode */
87
#define ENE_CIR_CONF1_TX_ON 0x30 /* enabled on transmit */
88
#define ENE_CIR_CONF1_TX_CARR (1 << 7) /* send TX carrier or not */
90
#define ENE_CIR_CONF2 0xFEC1 /* unknown setting = 0 */
91
#define ENE_CIR_CONF2_LEARN2 (1 << 4) /* set on enable learning */
92
#define ENE_CIR_CONF2_GPIO40DIS (1 << 5) /* disable normal input via gpio40 */
94
#define ENE_CIR_SAMPLE_PERIOD 0xFEC8 /* sample period in us */
95
#define ENE_CIR_SAMPLE_OVERFLOW (1 << 7) /* interrupt on overflows if set */
98
/* transmitter - not implemented yet */
99
/* KB3926C and higher */
100
/* transmission is very similiar to recieving, a byte is written to */
101
/* ENE_TX_INPUT, in same manner as it is read from sample buffer */
102
/* sample period is fixed*/
105
/* transmitter ports */
106
#define ENE_TX_PORT1 0xFC01 /* this enables one or both */
107
#define ENE_TX_PORT1_EN (1 << 5) /* TX ports */
108
#define ENE_TX_PORT2 0xFC08
109
#define ENE_TX_PORT2_EN (1 << 1)
111
#define ENE_TX_INPUT 0xFEC9 /* next byte to transmit */
112
#define ENE_TX_SPC_MASK (1 << 7) /* Transmitted sample is space */
113
#define ENE_TX_UNK1 0xFECB /* set to 0x63 */
114
#define ENE_TX_SMPL_PERIOD 50 /* transmit sample period */
117
#define ENE_TX_CARRIER 0xFECE /* TX carrier * 2 (khz) */
118
#define ENE_TX_CARRIER_UNKBIT 0x80 /* This bit set on transmit */
119
#define ENE_TX_CARRIER_LOW 0xFECF /* TX carrier / 2 */
90
#define ENE_CIR_CONF1_TX_CLEAR 0x01 /* clear that on revC */
91
/* while transmitting */
92
#define ENE_CIR_CONF1_RX_ON 0x07 /* normal reciever enabled */
93
#define ENE_CIR_CONF1_LEARN1 0x08 /* enabled on learning mode */
94
#define ENE_CIR_CONF1_TX_ON 0x30 /* enabled on transmit */
95
#define ENE_CIR_CONF1_TX_CARR 0x80 /* send TX carrier or not */
97
#define ENE_CIR_CONF2 0xFEC1 /* unknown setting = 0 */
98
#define ENE_CIR_CONF2_LEARN2 0x10 /* set on enable learning */
99
#define ENE_CIR_CONF2_GPIO40DIS 0x20 /* disable input via gpio40 */
101
#define ENE_CIR_SAMPLE_PERIOD 0xFEC8 /* sample period in us */
102
#define ENE_CIR_SAMPLE_OVERFLOW 0x80 /* interrupt on overflows if set */
105
/* Two byte tx buffer */
106
#define ENE_TX_INPUT1 0xFEC9
107
#define ENE_TX_INPUT2 0xFECA
108
#define ENE_TX_PULSE_MASK 0x80 /* Transmitted sample is pulse */
109
#define ENE_TX_SMLP_MASK 0x7F
110
#define ENE_TX_SMPL_PERIOD 50 /* transmit sample period - fixed */
113
/* Unknown TX setting - TX sample period ??? */
114
#define ENE_TX_UNK1 0xFECB /* set to 0x63 */
116
/* Current recieved carrier period */
117
#define ENE_RX_CARRIER 0xFECC /* RX period (500 ns) */
118
#define ENE_RX_CARRIER_VALID 0x80 /* Register content valid */
121
/* TX period (1/carrier) */
122
#define ENE_TX_PERIOD 0xFECE /* TX period (500 ns) */
123
#define ENE_TX_PERIOD_UNKBIT 0x80 /* This bit set on transmit*/
124
#define ENE_TX_PERIOD_PULSE 0xFECF /* TX pulse period (500 ns)*/
121
126
/* Hardware versions */
122
#define ENE_HW_VERSION 0xFF00 /* hardware revision */
123
#define ENE_HW_UNK 0xFF1D
124
#define ENE_HW_UNK_CLR (1 << 2)
125
#define ENE_HW_VER_MAJOR 0xFF1E /* chip version */
127
#define ENE_HW_VERSION 0xFF00 /* hardware revision */
128
#define ENE_HW_UNK 0xFF1D
129
#define ENE_HW_UNK_CLR 0x04
130
#define ENE_HW_VER_MAJOR 0xFF1E /* chip version */
126
131
#define ENE_HW_VER_MINOR 0xFF1F
127
132
#define ENE_HW_VER_OLD 0xFD00
129
#define same_sign(a, b) ((((a) > 0) && (b) > 0) || ((a) < 0 && (b) < 0))
131
#define ENE_DRIVER_NAME "enecir"
132
#define ENE_MAXGAP 250000 /* this is amount of time we wait
133
before turning the sampler, chosen
136
#define space(len) (-(len)) /* add a space */
138
/* software defines */
134
/* Normal/Learning carrier ranges - only valid if we have learning input*/
136
#define ENE_NORMAL_RX_LOW 34
137
#define ENE_NORMAL_RX_HI 38
139
/* Tx carrier range */
140
/* Hardware might be able to do more, but this range is enough for
142
#define ENE_TX_PERIOD_MAX 32 /* corresponds to 29.4 kHz */
143
#define ENE_TX_PERIOD_MIN 16 /* corrsponds to 62.5 kHz */
147
/* Minimal and maximal gaps */
150
Minimal gap is 0x7F * sample period
151
Maximum gap depends on hardware.
152
For KB3926B, it is unlimited, for newer models its around
153
250000, after which HW stops sending samples, and that is
154
not possible to change */
157
Both minimal and maximal gaps are same, and equal to 0xFFF * 0x61
158
And there is nothing to change this setting
161
#define ENE_MAXGAP 250000
162
#define ENE_MINGAP (127 * sample_period)
164
/******************************************************************************/
166
#define ENE_DRIVER_NAME "enecir"
167
#define ENE_TXBUF_SIZE (500 * sizeof(int)) /* 500 samples (arbitary) */
139
169
#define ENE_IRQ_RX 1
140
170
#define ENE_IRQ_TX 2
146
176
#define ene_printk(level, text, ...) \
147
177
printk(level ENE_DRIVER_NAME ": " text, ## __VA_ARGS__)
179
#define ene_dbg(text, ...) \
182
ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__)
184
#define ene_dbg_verbose(text, ...) \
187
ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__)
149
190
struct ene_device {
150
191
struct pnp_dev *pnp_dev;
151
192
struct lirc_driver *lirc_driver;
154
196
unsigned long hw_io;
157
201
int hw_revision; /* hardware revision */
158
202
int hw_learning_and_tx_capable; /* learning capable */
159
203
int hw_gpio40_learning; /* gpio40 is learning */
160
int hw_fan_as_normal_input; /* fan input is used as regular input */
169
struct timeval gap_start;
204
int hw_fan_as_normal_input; /* fan input is used as */
207
int rx_pointer; /* hw pointer to rx buffer */
208
int rx_fan_input_inuse; /* is fan input in use for rx*/
209
int tx_reg; /* current reg used for TX */
210
u8 saved_conf1; /* saved FEC0 reg */
211
int learning_enabled; /* learning input enabled */
213
/* RX sample handling */
214
int rx_sample; /* current recieved sample */
215
int rx_sample_pulse; /* recieved sample is pulse */
216
int rx_idle; /* idle mode for RX activated */
217
struct timeval rx_gap_start; /* time of start of idle */
218
int rx_timeout; /* time in ms of RX timeout */
219
int rx_send_timeout_packet; /* do we send RX timeout */
220
int rx_timeout_sent; /* we sent the timeout packet */
221
int rx_carrier_sense; /* sense carrier */
223
/* TX sample handling */
224
unsigned int tx_sample; /* current sample for TX */
225
int tx_sample_pulse; /* current sample is pulse */
228
int tx_buffer[ENE_TXBUF_SIZE]; /* input samples buffer*/
229
int tx_pos; /* position in that bufer */
230
int tx_len; /* current len of tx buffer */
231
int tx_underway; /* TX is under way*/
232
int tx_done; /* done transmitting */
233
/* one more sample pending*/
234
struct completion tx_complete; /* TX completion */
235
struct timer_list tx_sim_timer;
240
int transmitter_mask;
added
removed
drivers/lirc_ene0100/lirc_ene0100.h
