1
2011-08-09 Chao-ying Fu <fu@mips.com>
2
Maciej W. Rozycki <macro@codesourcery.com>
4
* mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
6
(print_insn_args, print_insn_micromips): Handle MCU.
7
* micromips-opc.c (MC): New macro.
8
(micromips_opcodes): Add "aclr", "aset" and "iret".
9
* mips-opc.c (MC): New macro.
10
(mips_builtin_opcodes): Add "aclr", "aset" and "iret".
12
2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
14
* micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
15
(MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
16
(MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
17
(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
18
(RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
19
(RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
21
(micromips_opcodes): Update register use flags of: "addiu",
22
"addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
23
"and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
24
"jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
25
"lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
26
"nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
27
"swm" and "xor" instructions.
29
2011-08-05 David S. Miller <davem@davemloft.net>
31
* sparc-dis.c (v9a_ast_reg_names): Add "cps".
33
(print_insn_sparc): Handle '4', '5', and '(' format codes.
34
Accept %asr numbers below 28.
35
* sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
1
38
2011-08-02 Quentin Neill <quentin.neill@amd.com>
3
40
* i386-dis.c (xop_table): Remove spurious bextr insn.
added
removed
opcodes/ChangeLog
