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Viewing changes to drivers/gpu/drm/nouveau/nv50_display.c

  • Committer: Package Import Robot
  • Author(s): Tim Gardner
  • Date: 2013-10-09 13:31:18 UTC
  • Revision ID: package-import@ubuntu.com-20131009133118-l5q5o2hmtz96hefq
Tags: upstream-3.11.0
Import upstream version 3.11.0

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drivers/gpu/drm/nouveau/nv50_display.c
 
1
        /*
 
2
 * Copyright 2011 Red Hat Inc.
 
3
 *
 
4
 * Permission is hereby granted, free of charge, to any person obtaining a
 
5
 * copy of this software and associated documentation files (the "Software"),
 
6
 * to deal in the Software without restriction, including without limitation
 
7
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 
8
 * and/or sell copies of the Software, and to permit persons to whom the
 
9
 * Software is furnished to do so, subject to the following conditions:
 
10
 *
 
11
 * The above copyright notice and this permission notice shall be included in
 
12
 * all copies or substantial portions of the Software.
 
13
 *
 
14
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 
15
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 
16
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 
17
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 
18
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 
19
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 
20
 * OTHER DEALINGS IN THE SOFTWARE.
 
21
 *
 
22
 * Authors: Ben Skeggs
 
23
 */
 
24
 
 
25
#include <linux/dma-mapping.h>
 
26
 
 
27
#include <drm/drmP.h>
 
28
#include <drm/drm_crtc_helper.h>
 
29
 
 
30
#include "nouveau_drm.h"
 
31
#include "nouveau_dma.h"
 
32
#include "nouveau_gem.h"
 
33
#include "nouveau_connector.h"
 
34
#include "nouveau_encoder.h"
 
35
#include "nouveau_crtc.h"
 
36
#include "nouveau_fence.h"
 
37
#include "nv50_display.h"
 
38
 
 
39
#include <core/client.h>
 
40
#include <core/gpuobj.h>
 
41
#include <core/class.h>
 
42
 
 
43
#include <subdev/timer.h>
 
44
#include <subdev/bar.h>
 
45
#include <subdev/fb.h>
 
46
#include <subdev/i2c.h>
 
47
 
 
48
#define EVO_DMA_NR 9
 
49
 
 
50
#define EVO_MASTER  (0x00)
 
51
#define EVO_FLIP(c) (0x01 + (c))
 
52
#define EVO_OVLY(c) (0x05 + (c))
 
53
#define EVO_OIMM(c) (0x09 + (c))
 
54
#define EVO_CURS(c) (0x0d + (c))
 
55
 
 
56
/* offsets in shared sync bo of various structures */
 
57
#define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
 
58
#define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
 
59
#define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
 
60
#define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
 
61
 
 
62
#define EVO_CORE_HANDLE      (0xd1500000)
 
63
#define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
 
64
#define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff))
 
65
#define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) |                               \
 
66
                              (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
 
67
 
 
68
/******************************************************************************
 
69
 * EVO channel
 
70
 *****************************************************************************/
 
71
 
 
72
struct nv50_chan {
 
73
        struct nouveau_object *user;
 
74
        u32 handle;
 
75
};
 
76
 
 
77
static int
 
78
nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head,
 
79
                 void *data, u32 size, struct nv50_chan *chan)
 
80
{
 
81
        struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 
82
        const u32 oclass = EVO_CHAN_OCLASS(bclass, core);
 
83
        const u32 handle = EVO_CHAN_HANDLE(bclass, head);
 
84
        int ret;
 
85
 
 
86
        ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle,
 
87
                                 oclass, data, size, &chan->user);
 
88
        if (ret)
 
89
                return ret;
 
90
 
 
91
        chan->handle = handle;
 
92
        return 0;
 
93
}
 
94
 
 
95
static void
 
96
nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan)
 
97
{
 
98
        struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 
99
        if (chan->handle)
 
100
                nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle);
 
101
}
 
102
 
 
103
/******************************************************************************
 
104
 * PIO EVO channel
 
105
 *****************************************************************************/
 
106
 
 
107
struct nv50_pioc {
 
108
        struct nv50_chan base;
 
109
};
 
110
 
 
111
static void
 
112
nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc)
 
113
{
 
114
        nv50_chan_destroy(core, &pioc->base);
 
115
}
 
116
 
 
117
static int
 
118
nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head,
 
119
                 void *data, u32 size, struct nv50_pioc *pioc)
 
120
{
 
121
        return nv50_chan_create(core, bclass, head, data, size, &pioc->base);
 
122
}
 
123
 
 
124
/******************************************************************************
 
125
 * DMA EVO channel
 
126
 *****************************************************************************/
 
127
 
 
128
struct nv50_dmac {
 
129
        struct nv50_chan base;
 
130
        dma_addr_t handle;
 
131
        u32 *ptr;
 
132
 
 
133
        /* Protects against concurrent pushbuf access to this channel, lock is
 
134
         * grabbed by evo_wait (if the pushbuf reservation is successful) and
 
135
         * dropped again by evo_kick. */
 
136
        struct mutex lock;
 
137
};
 
138
 
 
139
static void
 
140
nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac)
 
141
{
 
142
        if (dmac->ptr) {
 
143
                struct pci_dev *pdev = nv_device(core)->pdev;
 
144
                pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
 
145
        }
 
146
 
 
147
        nv50_chan_destroy(core, &dmac->base);
 
148
}
 
149
 
 
150
static int
 
151
nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
 
152
{
 
153
        struct nouveau_fb *pfb = nouveau_fb(core);
 
154
        struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 
155
        struct nouveau_object *object;
 
156
        int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
 
157
                                     NV_DMA_IN_MEMORY_CLASS,
 
158
                                     &(struct nv_dma_class) {
 
159
                                        .flags = NV_DMA_TARGET_VRAM |
 
160
                                                 NV_DMA_ACCESS_RDWR,
 
161
                                        .start = 0,
 
162
                                        .limit = pfb->ram->size - 1,
 
163
                                        .conf0 = NV50_DMA_CONF0_ENABLE |
 
164
                                                 NV50_DMA_CONF0_PART_256,
 
165
                                     }, sizeof(struct nv_dma_class), &object);
 
166
        if (ret)
 
167
                return ret;
 
168
 
 
169
        ret = nouveau_object_new(client, parent, NvEvoFB16,
 
170
                                 NV_DMA_IN_MEMORY_CLASS,
 
171
                                 &(struct nv_dma_class) {
 
172
                                        .flags = NV_DMA_TARGET_VRAM |
 
173
                                                 NV_DMA_ACCESS_RDWR,
 
174
                                        .start = 0,
 
175
                                        .limit = pfb->ram->size - 1,
 
176
                                        .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 |
 
177
                                                 NV50_DMA_CONF0_PART_256,
 
178
                                 }, sizeof(struct nv_dma_class), &object);
 
179
        if (ret)
 
180
                return ret;
 
181
 
 
182
        ret = nouveau_object_new(client, parent, NvEvoFB32,
 
183
                                 NV_DMA_IN_MEMORY_CLASS,
 
184
                                 &(struct nv_dma_class) {
 
185
                                        .flags = NV_DMA_TARGET_VRAM |
 
186
                                                 NV_DMA_ACCESS_RDWR,
 
187
                                        .start = 0,
 
188
                                        .limit = pfb->ram->size - 1,
 
189
                                        .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a |
 
190
                                                 NV50_DMA_CONF0_PART_256,
 
191
                                 }, sizeof(struct nv_dma_class), &object);
 
192
        return ret;
 
193
}
 
194
 
 
195
static int
 
196
nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
 
197
{
 
198
        struct nouveau_fb *pfb = nouveau_fb(core);
 
199
        struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 
200
        struct nouveau_object *object;
 
201
        int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
 
202
                                     NV_DMA_IN_MEMORY_CLASS,
 
203
                                     &(struct nv_dma_class) {
 
204
                                        .flags = NV_DMA_TARGET_VRAM |
 
205
                                                 NV_DMA_ACCESS_RDWR,
 
206
                                        .start = 0,
 
207
                                        .limit = pfb->ram->size - 1,
 
208
                                        .conf0 = NVC0_DMA_CONF0_ENABLE,
 
209
                                     }, sizeof(struct nv_dma_class), &object);
 
210
        if (ret)
 
211
                return ret;
 
212
 
 
213
        ret = nouveau_object_new(client, parent, NvEvoFB16,
 
214
                                 NV_DMA_IN_MEMORY_CLASS,
 
215
                                 &(struct nv_dma_class) {
 
216
                                        .flags = NV_DMA_TARGET_VRAM |
 
217
                                                 NV_DMA_ACCESS_RDWR,
 
218
                                        .start = 0,
 
219
                                        .limit = pfb->ram->size - 1,
 
220
                                        .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
 
221
                                 }, sizeof(struct nv_dma_class), &object);
 
222
        if (ret)
 
223
                return ret;
 
224
 
 
225
        ret = nouveau_object_new(client, parent, NvEvoFB32,
 
226
                                 NV_DMA_IN_MEMORY_CLASS,
 
227
                                 &(struct nv_dma_class) {
 
228
                                        .flags = NV_DMA_TARGET_VRAM |
 
229
                                                 NV_DMA_ACCESS_RDWR,
 
230
                                        .start = 0,
 
231
                                        .limit = pfb->ram->size - 1,
 
232
                                        .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
 
233
                                 }, sizeof(struct nv_dma_class), &object);
 
234
        return ret;
 
235
}
 
236
 
 
237
static int
 
238
nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
 
239
{
 
240
        struct nouveau_fb *pfb = nouveau_fb(core);
 
241
        struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 
242
        struct nouveau_object *object;
 
243
        int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
 
244
                                     NV_DMA_IN_MEMORY_CLASS,
 
245
                                     &(struct nv_dma_class) {
 
246
                                        .flags = NV_DMA_TARGET_VRAM |
 
247
                                                 NV_DMA_ACCESS_RDWR,
 
248
                                        .start = 0,
 
249
                                        .limit = pfb->ram->size - 1,
 
250
                                        .conf0 = NVD0_DMA_CONF0_ENABLE |
 
251
                                                 NVD0_DMA_CONF0_PAGE_LP,
 
252
                                     }, sizeof(struct nv_dma_class), &object);
 
253
        if (ret)
 
254
                return ret;
 
255
 
 
256
        ret = nouveau_object_new(client, parent, NvEvoFB32,
 
257
                                 NV_DMA_IN_MEMORY_CLASS,
 
258
                                 &(struct nv_dma_class) {
 
259
                                        .flags = NV_DMA_TARGET_VRAM |
 
260
                                                 NV_DMA_ACCESS_RDWR,
 
261
                                        .start = 0,
 
262
                                        .limit = pfb->ram->size - 1,
 
263
                                        .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe |
 
264
                                                 NVD0_DMA_CONF0_PAGE_LP,
 
265
                                 }, sizeof(struct nv_dma_class), &object);
 
266
        return ret;
 
267
}
 
268
 
 
269
static int
 
270
nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head,
 
271
                 void *data, u32 size, u64 syncbuf,
 
272
                 struct nv50_dmac *dmac)
 
273
{
 
274
        struct nouveau_fb *pfb = nouveau_fb(core);
 
275
        struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 
276
        struct nouveau_object *object;
 
277
        u32 pushbuf = *(u32 *)data;
 
278
        int ret;
 
279
 
 
280
        mutex_init(&dmac->lock);
 
281
 
 
282
        dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE,
 
283
                                        &dmac->handle);
 
284
        if (!dmac->ptr)
 
285
                return -ENOMEM;
 
286
 
 
287
        ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf,
 
288
                                 NV_DMA_FROM_MEMORY_CLASS,
 
289
                                 &(struct nv_dma_class) {
 
290
                                        .flags = NV_DMA_TARGET_PCI_US |
 
291
                                                 NV_DMA_ACCESS_RD,
 
292
                                        .start = dmac->handle + 0x0000,
 
293
                                        .limit = dmac->handle + 0x0fff,
 
294
                                 }, sizeof(struct nv_dma_class), &object);
 
295
        if (ret)
 
296
                return ret;
 
297
 
 
298
        ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base);
 
299
        if (ret)
 
300
                return ret;
 
301
 
 
302
        ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync,
 
303
                                 NV_DMA_IN_MEMORY_CLASS,
 
304
                                 &(struct nv_dma_class) {
 
305
                                        .flags = NV_DMA_TARGET_VRAM |
 
306
                                                 NV_DMA_ACCESS_RDWR,
 
307
                                        .start = syncbuf + 0x0000,
 
308
                                        .limit = syncbuf + 0x0fff,
 
309
                                 }, sizeof(struct nv_dma_class), &object);
 
310
        if (ret)
 
311
                return ret;
 
312
 
 
313
        ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM,
 
314
                                 NV_DMA_IN_MEMORY_CLASS,
 
315
                                 &(struct nv_dma_class) {
 
316
                                        .flags = NV_DMA_TARGET_VRAM |
 
317
                                                 NV_DMA_ACCESS_RDWR,
 
318
                                        .start = 0,
 
319
                                        .limit = pfb->ram->size - 1,
 
320
                                 }, sizeof(struct nv_dma_class), &object);
 
321
        if (ret)
 
322
                return ret;
 
323
 
 
324
        if (nv_device(core)->card_type < NV_C0)
 
325
                ret = nv50_dmac_create_fbdma(core, dmac->base.handle);
 
326
        else
 
327
        if (nv_device(core)->card_type < NV_D0)
 
328
                ret = nvc0_dmac_create_fbdma(core, dmac->base.handle);
 
329
        else
 
330
                ret = nvd0_dmac_create_fbdma(core, dmac->base.handle);
 
331
        return ret;
 
332
}
 
333
 
 
334
struct nv50_mast {
 
335
        struct nv50_dmac base;
 
336
};
 
337
 
 
338
struct nv50_curs {
 
339
        struct nv50_pioc base;
 
340
};
 
341
 
 
342
struct nv50_sync {
 
343
        struct nv50_dmac base;
 
344
        u32 addr;
 
345
        u32 data;
 
346
};
 
347
 
 
348
struct nv50_ovly {
 
349
        struct nv50_dmac base;
 
350
};
 
351
 
 
352
struct nv50_oimm {
 
353
        struct nv50_pioc base;
 
354
};
 
355
 
 
356
struct nv50_head {
 
357
        struct nouveau_crtc base;
 
358
        struct nouveau_bo *image;
 
359
        struct nv50_curs curs;
 
360
        struct nv50_sync sync;
 
361
        struct nv50_ovly ovly;
 
362
        struct nv50_oimm oimm;
 
363
};
 
364
 
 
365
#define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 
366
#define nv50_curs(c) (&nv50_head(c)->curs)
 
367
#define nv50_sync(c) (&nv50_head(c)->sync)
 
368
#define nv50_ovly(c) (&nv50_head(c)->ovly)
 
369
#define nv50_oimm(c) (&nv50_head(c)->oimm)
 
370
#define nv50_chan(c) (&(c)->base.base)
 
371
#define nv50_vers(c) nv_mclass(nv50_chan(c)->user)
 
372
 
 
373
struct nv50_disp {
 
374
        struct nouveau_object *core;
 
375
        struct nv50_mast mast;
 
376
 
 
377
        u32 modeset;
 
378
 
 
379
        struct nouveau_bo *sync;
 
380
};
 
381
 
 
382
static struct nv50_disp *
 
383
nv50_disp(struct drm_device *dev)
 
384
{
 
385
        return nouveau_display(dev)->priv;
 
386
}
 
387
 
 
388
#define nv50_mast(d) (&nv50_disp(d)->mast)
 
389
 
 
390
static struct drm_crtc *
 
391
nv50_display_crtc_get(struct drm_encoder *encoder)
 
392
{
 
393
        return nouveau_encoder(encoder)->crtc;
 
394
}
 
395
 
 
396
/******************************************************************************
 
397
 * EVO channel helpers
 
398
 *****************************************************************************/
 
399
static u32 *
 
400
evo_wait(void *evoc, int nr)
 
401
{
 
402
        struct nv50_dmac *dmac = evoc;
 
403
        u32 put = nv_ro32(dmac->base.user, 0x0000) / 4;
 
404
 
 
405
        mutex_lock(&dmac->lock);
 
406
        if (put + nr >= (PAGE_SIZE / 4) - 8) {
 
407
                dmac->ptr[put] = 0x20000000;
 
408
 
 
409
                nv_wo32(dmac->base.user, 0x0000, 0x00000000);
 
410
                if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) {
 
411
                        mutex_unlock(&dmac->lock);
 
412
                        NV_ERROR(dmac->base.user, "channel stalled\n");
 
413
                        return NULL;
 
414
                }
 
415
 
 
416
                put = 0;
 
417
        }
 
418
 
 
419
        return dmac->ptr + put;
 
420
}
 
421
 
 
422
static void
 
423
evo_kick(u32 *push, void *evoc)
 
424
{
 
425
        struct nv50_dmac *dmac = evoc;
 
426
        nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 
427
        mutex_unlock(&dmac->lock);
 
428
}
 
429
 
 
430
#define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 
431
#define evo_data(p,d)   *((p)++) = (d)
 
432
 
 
433
static bool
 
434
evo_sync_wait(void *data)
 
435
{
 
436
        if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
 
437
                return true;
 
438
        usleep_range(1, 2);
 
439
        return false;
 
440
}
 
441
 
 
442
static int
 
443
evo_sync(struct drm_device *dev)
 
444
{
 
445
        struct nouveau_device *device = nouveau_dev(dev);
 
446
        struct nv50_disp *disp = nv50_disp(dev);
 
447
        struct nv50_mast *mast = nv50_mast(dev);
 
448
        u32 *push = evo_wait(mast, 8);
 
449
        if (push) {
 
450
                nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
 
451
                evo_mthd(push, 0x0084, 1);
 
452
                evo_data(push, 0x80000000 | EVO_MAST_NTFY);
 
453
                evo_mthd(push, 0x0080, 2);
 
454
                evo_data(push, 0x00000000);
 
455
                evo_data(push, 0x00000000);
 
456
                evo_kick(push, mast);
 
457
                if (nv_wait_cb(device, evo_sync_wait, disp->sync))
 
458
                        return 0;
 
459
        }
 
460
 
 
461
        return -EBUSY;
 
462
}
 
463
 
 
464
/******************************************************************************
 
465
 * Page flipping channel
 
466
 *****************************************************************************/
 
467
struct nouveau_bo *
 
468
nv50_display_crtc_sema(struct drm_device *dev, int crtc)
 
469
{
 
470
        return nv50_disp(dev)->sync;
 
471
}
 
472
 
 
473
struct nv50_display_flip {
 
474
        struct nv50_disp *disp;
 
475
        struct nv50_sync *chan;
 
476
};
 
477
 
 
478
static bool
 
479
nv50_display_flip_wait(void *data)
 
480
{
 
481
        struct nv50_display_flip *flip = data;
 
482
        if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
 
483
                                              flip->chan->data)
 
484
                return true;
 
485
        usleep_range(1, 2);
 
486
        return false;
 
487
}
 
488
 
 
489
void
 
490
nv50_display_flip_stop(struct drm_crtc *crtc)
 
491
{
 
492
        struct nouveau_device *device = nouveau_dev(crtc->dev);
 
493
        struct nv50_display_flip flip = {
 
494
                .disp = nv50_disp(crtc->dev),
 
495
                .chan = nv50_sync(crtc),
 
496
        };
 
497
        u32 *push;
 
498
 
 
499
        push = evo_wait(flip.chan, 8);
 
500
        if (push) {
 
501
                evo_mthd(push, 0x0084, 1);
 
502
                evo_data(push, 0x00000000);
 
503
                evo_mthd(push, 0x0094, 1);
 
504
                evo_data(push, 0x00000000);
 
505
                evo_mthd(push, 0x00c0, 1);
 
506
                evo_data(push, 0x00000000);
 
507
                evo_mthd(push, 0x0080, 1);
 
508
                evo_data(push, 0x00000000);
 
509
                evo_kick(push, flip.chan);
 
510
        }
 
511
 
 
512
        nv_wait_cb(device, nv50_display_flip_wait, &flip);
 
513
}
 
514
 
 
515
int
 
516
nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 
517
                       struct nouveau_channel *chan, u32 swap_interval)
 
518
{
 
519
        struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 
520
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 
521
        struct nv50_head *head = nv50_head(crtc);
 
522
        struct nv50_sync *sync = nv50_sync(crtc);
 
523
        u32 *push;
 
524
        int ret;
 
525
 
 
526
        swap_interval <<= 4;
 
527
        if (swap_interval == 0)
 
528
                swap_interval |= 0x100;
 
529
        if (chan == NULL)
 
530
                evo_sync(crtc->dev);
 
531
 
 
532
        push = evo_wait(sync, 128);
 
533
        if (unlikely(push == NULL))
 
534
                return -EBUSY;
 
535
 
 
536
        if (chan && nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
 
537
                ret = RING_SPACE(chan, 8);
 
538
                if (ret)
 
539
                        return ret;
 
540
 
 
541
                BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
 
542
                OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 
543
                OUT_RING  (chan, sync->addr ^ 0x10);
 
544
                BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
 
545
                OUT_RING  (chan, sync->data + 1);
 
546
                BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
 
547
                OUT_RING  (chan, sync->addr);
 
548
                OUT_RING  (chan, sync->data);
 
549
        } else
 
550
        if (chan && nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
 
551
                u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 
552
                ret = RING_SPACE(chan, 12);
 
553
                if (ret)
 
554
                        return ret;
 
555
 
 
556
                BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
 
557
                OUT_RING  (chan, chan->vram);
 
558
                BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 
559
                OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 
560
                OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 
561
                OUT_RING  (chan, sync->data + 1);
 
562
                OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
 
563
                BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 
564
                OUT_RING  (chan, upper_32_bits(addr));
 
565
                OUT_RING  (chan, lower_32_bits(addr));
 
566
                OUT_RING  (chan, sync->data);
 
567
                OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
 
568
        } else
 
569
        if (chan) {
 
570
                u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 
571
                ret = RING_SPACE(chan, 10);
 
572
                if (ret)
 
573
                        return ret;
 
574
 
 
575
                BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 
576
                OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 
577
                OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 
578
                OUT_RING  (chan, sync->data + 1);
 
579
                OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
 
580
                                 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 
581
                BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 
582
                OUT_RING  (chan, upper_32_bits(addr));
 
583
                OUT_RING  (chan, lower_32_bits(addr));
 
584
                OUT_RING  (chan, sync->data);
 
585
                OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
 
586
                                 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 
587
        }
 
588
 
 
589
        if (chan) {
 
590
                sync->addr ^= 0x10;
 
591
                sync->data++;
 
592
                FIRE_RING (chan);
 
593
        }
 
594
 
 
595
        /* queue the flip */
 
596
        evo_mthd(push, 0x0100, 1);
 
597
        evo_data(push, 0xfffe0000);
 
598
        evo_mthd(push, 0x0084, 1);
 
599
        evo_data(push, swap_interval);
 
600
        if (!(swap_interval & 0x00000100)) {
 
601
                evo_mthd(push, 0x00e0, 1);
 
602
                evo_data(push, 0x40000000);
 
603
        }
 
604
        evo_mthd(push, 0x0088, 4);
 
605
        evo_data(push, sync->addr);
 
606
        evo_data(push, sync->data++);
 
607
        evo_data(push, sync->data);
 
608
        evo_data(push, NvEvoSync);
 
609
        evo_mthd(push, 0x00a0, 2);
 
610
        evo_data(push, 0x00000000);
 
611
        evo_data(push, 0x00000000);
 
612
        evo_mthd(push, 0x00c0, 1);
 
613
        evo_data(push, nv_fb->r_dma);
 
614
        evo_mthd(push, 0x0110, 2);
 
615
        evo_data(push, 0x00000000);
 
616
        evo_data(push, 0x00000000);
 
617
        if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) {
 
618
                evo_mthd(push, 0x0800, 5);
 
619
                evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 
620
                evo_data(push, 0);
 
621
                evo_data(push, (fb->height << 16) | fb->width);
 
622
                evo_data(push, nv_fb->r_pitch);
 
623
                evo_data(push, nv_fb->r_format);
 
624
        } else {
 
625
                evo_mthd(push, 0x0400, 5);
 
626
                evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 
627
                evo_data(push, 0);
 
628
                evo_data(push, (fb->height << 16) | fb->width);
 
629
                evo_data(push, nv_fb->r_pitch);
 
630
                evo_data(push, nv_fb->r_format);
 
631
        }
 
632
        evo_mthd(push, 0x0080, 1);
 
633
        evo_data(push, 0x00000000);
 
634
        evo_kick(push, sync);
 
635
 
 
636
        nouveau_bo_ref(nv_fb->nvbo, &head->image);
 
637
        return 0;
 
638
}
 
639
 
 
640
/******************************************************************************
 
641
 * CRTC
 
642
 *****************************************************************************/
 
643
static int
 
644
nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 
645
{
 
646
        struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 
647
        struct nouveau_connector *nv_connector;
 
648
        struct drm_connector *connector;
 
649
        u32 *push, mode = 0x00;
 
650
 
 
651
        nv_connector = nouveau_crtc_connector_get(nv_crtc);
 
652
        connector = &nv_connector->base;
 
653
        if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
 
654
                if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3)
 
655
                        mode = DITHERING_MODE_DYNAMIC2X2;
 
656
        } else {
 
657
                mode = nv_connector->dithering_mode;
 
658
        }
 
659
 
 
660
        if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
 
661
                if (connector->display_info.bpc >= 8)
 
662
                        mode |= DITHERING_DEPTH_8BPC;
 
663
        } else {
 
664
                mode |= nv_connector->dithering_depth;
 
665
        }
 
666
 
 
667
        push = evo_wait(mast, 4);
 
668
        if (push) {
 
669
                if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 
670
                        evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
 
671
                        evo_data(push, mode);
 
672
                } else
 
673
                if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) {
 
674
                        evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
 
675
                        evo_data(push, mode);
 
676
                } else {
 
677
                        evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
 
678
                        evo_data(push, mode);
 
679
                }
 
680
 
 
681
                if (update) {
 
682
                        evo_mthd(push, 0x0080, 1);
 
683
                        evo_data(push, 0x00000000);
 
684
                }
 
685
                evo_kick(push, mast);
 
686
        }
 
687
 
 
688
        return 0;
 
689
}
 
690
 
 
691
static int
 
692
nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 
693
{
 
694
        struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 
695
        struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
 
696
        struct drm_crtc *crtc = &nv_crtc->base;
 
697
        struct nouveau_connector *nv_connector;
 
698
        int mode = DRM_MODE_SCALE_NONE;
 
699
        u32 oX, oY, *push;
 
700
 
 
701
        /* start off at the resolution we programmed the crtc for, this
 
702
         * effectively handles NONE/FULL scaling
 
703
         */
 
704
        nv_connector = nouveau_crtc_connector_get(nv_crtc);
 
705
        if (nv_connector && nv_connector->native_mode)
 
706
                mode = nv_connector->scaling_mode;
 
707
 
 
708
        if (mode != DRM_MODE_SCALE_NONE)
 
709
                omode = nv_connector->native_mode;
 
710
        else
 
711
                omode = umode;
 
712
 
 
713
        oX = omode->hdisplay;
 
714
        oY = omode->vdisplay;
 
715
        if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
 
716
                oY *= 2;
 
717
 
 
718
        /* add overscan compensation if necessary, will keep the aspect
 
719
         * ratio the same as the backend mode unless overridden by the
 
720
         * user setting both hborder and vborder properties.
 
721
         */
 
722
        if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
 
723
                             (nv_connector->underscan == UNDERSCAN_AUTO &&
 
724
                              nv_connector->edid &&
 
725
                              drm_detect_hdmi_monitor(nv_connector->edid)))) {
 
726
                u32 bX = nv_connector->underscan_hborder;
 
727
                u32 bY = nv_connector->underscan_vborder;
 
728
                u32 aspect = (oY << 19) / oX;
 
729
 
 
730
                if (bX) {
 
731
                        oX -= (bX * 2);
 
732
                        if (bY) oY -= (bY * 2);
 
733
                        else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 
734
                } else {
 
735
                        oX -= (oX >> 4) + 32;
 
736
                        if (bY) oY -= (bY * 2);
 
737
                        else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 
738
                }
 
739
        }
 
740
 
 
741
        /* handle CENTER/ASPECT scaling, taking into account the areas
 
742
         * removed already for overscan compensation
 
743
         */
 
744
        switch (mode) {
 
745
        case DRM_MODE_SCALE_CENTER:
 
746
                oX = min((u32)umode->hdisplay, oX);
 
747
                oY = min((u32)umode->vdisplay, oY);
 
748
                /* fall-through */
 
749
        case DRM_MODE_SCALE_ASPECT:
 
750
                if (oY < oX) {
 
751
                        u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
 
752
                        oX = ((oY * aspect) + (aspect / 2)) >> 19;
 
753
                } else {
 
754
                        u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
 
755
                        oY = ((oX * aspect) + (aspect / 2)) >> 19;
 
756
                }
 
757
                break;
 
758
        default:
 
759
                break;
 
760
        }
 
761
 
 
762
        push = evo_wait(mast, 8);
 
763
        if (push) {
 
764
                if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 
765
                        /*XXX: SCALE_CTRL_ACTIVE??? */
 
766
                        evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
 
767
                        evo_data(push, (oY << 16) | oX);
 
768
                        evo_data(push, (oY << 16) | oX);
 
769
                        evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
 
770
                        evo_data(push, 0x00000000);
 
771
                        evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
 
772
                        evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 
773
                } else {
 
774
                        evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 
775
                        evo_data(push, (oY << 16) | oX);
 
776
                        evo_data(push, (oY << 16) | oX);
 
777
                        evo_data(push, (oY << 16) | oX);
 
778
                        evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 
779
                        evo_data(push, 0x00000000);
 
780
                        evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 
781
                        evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 
782
                }
 
783
 
 
784
                evo_kick(push, mast);
 
785
 
 
786
                if (update) {
 
787
                        nv50_display_flip_stop(crtc);
 
788
                        nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
 
789
                }
 
790
        }
 
791
 
 
792
        return 0;
 
793
}
 
794
 
 
795
static int
 
796
nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
 
797
{
 
798
        struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 
799
        u32 *push, hue, vib;
 
800
        int adj;
 
801
 
 
802
        adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
 
803
        vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
 
804
        hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
 
805
 
 
806
        push = evo_wait(mast, 16);
 
807
        if (push) {
 
808
                if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 
809
                        evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
 
810
                        evo_data(push, (hue << 20) | (vib << 8));
 
811
                } else {
 
812
                        evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
 
813
                        evo_data(push, (hue << 20) | (vib << 8));
 
814
                }
 
815
 
 
816
                if (update) {
 
817
                        evo_mthd(push, 0x0080, 1);
 
818
                        evo_data(push, 0x00000000);
 
819
                }
 
820
                evo_kick(push, mast);
 
821
        }
 
822
 
 
823
        return 0;
 
824
}
 
825
 
 
826
static int
 
827
nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 
828
                    int x, int y, bool update)
 
829
{
 
830
        struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 
831
        struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 
832
        u32 *push;
 
833
 
 
834
        push = evo_wait(mast, 16);
 
835
        if (push) {
 
836
                if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 
837
                        evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
 
838
                        evo_data(push, nvfb->nvbo->bo.offset >> 8);
 
839
                        evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
 
840
                        evo_data(push, (fb->height << 16) | fb->width);
 
841
                        evo_data(push, nvfb->r_pitch);
 
842
                        evo_data(push, nvfb->r_format);
 
843
                        evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
 
844
                        evo_data(push, (y << 16) | x);
 
845
                        if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) {
 
846
                                evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 
847
                                evo_data(push, nvfb->r_dma);
 
848
                        }
 
849
                } else {
 
850
                        evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 
851
                        evo_data(push, nvfb->nvbo->bo.offset >> 8);
 
852
                        evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 
853
                        evo_data(push, (fb->height << 16) | fb->width);
 
854
                        evo_data(push, nvfb->r_pitch);
 
855
                        evo_data(push, nvfb->r_format);
 
856
                        evo_data(push, nvfb->r_dma);
 
857
                        evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 
858
                        evo_data(push, (y << 16) | x);
 
859
                }
 
860
 
 
861
                if (update) {
 
862
                        evo_mthd(push, 0x0080, 1);
 
863
                        evo_data(push, 0x00000000);
 
864
                }
 
865
                evo_kick(push, mast);
 
866
        }
 
867
 
 
868
        nv_crtc->fb.tile_flags = nvfb->r_dma;
 
869
        return 0;
 
870
}
 
871
 
 
872
static void
 
873
nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
 
874
{
 
875
        struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 
876
        u32 *push = evo_wait(mast, 16);
 
877
        if (push) {
 
878
                if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 
879
                        evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 
880
                        evo_data(push, 0x85000000);
 
881
                        evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 
882
                } else
 
883
                if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 
884
                        evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 
885
                        evo_data(push, 0x85000000);
 
886
                        evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 
887
                        evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 
888
                        evo_data(push, NvEvoVRAM);
 
889
                } else {
 
890
                        evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 
891
                        evo_data(push, 0x85000000);
 
892
                        evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 
893
                        evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 
894
                        evo_data(push, NvEvoVRAM);
 
895
                }
 
896
                evo_kick(push, mast);
 
897
        }
 
898
}
 
899
 
 
900
static void
 
901
nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
 
902
{
 
903
        struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 
904
        u32 *push = evo_wait(mast, 16);
 
905
        if (push) {
 
906
                if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 
907
                        evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 
908
                        evo_data(push, 0x05000000);
 
909
                } else
 
910
                if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 
911
                        evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 
912
                        evo_data(push, 0x05000000);
 
913
                        evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 
914
                        evo_data(push, 0x00000000);
 
915
                } else {
 
916
                        evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 
917
                        evo_data(push, 0x05000000);
 
918
                        evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 
919
                        evo_data(push, 0x00000000);
 
920
                }
 
921
                evo_kick(push, mast);
 
922
        }
 
923
}
 
924
 
 
925
static void
 
926
nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
 
927
{
 
928
        struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 
929
 
 
930
        if (show)
 
931
                nv50_crtc_cursor_show(nv_crtc);
 
932
        else
 
933
                nv50_crtc_cursor_hide(nv_crtc);
 
934
 
 
935
        if (update) {
 
936
                u32 *push = evo_wait(mast, 2);
 
937
                if (push) {
 
938
                        evo_mthd(push, 0x0080, 1);
 
939
                        evo_data(push, 0x00000000);
 
940
                        evo_kick(push, mast);
 
941
                }
 
942
        }
 
943
}
 
944
 
 
945
static void
 
946
nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
 
947
{
 
948
}
 
949
 
 
950
static void
 
951
nv50_crtc_prepare(struct drm_crtc *crtc)
 
952
{
 
953
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 
954
        struct nv50_mast *mast = nv50_mast(crtc->dev);
 
955
        u32 *push;
 
956
 
 
957
        nv50_display_flip_stop(crtc);
 
958
 
 
959
        push = evo_wait(mast, 2);
 
960
        if (push) {
 
961
                if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 
962
                        evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 
963
                        evo_data(push, 0x00000000);
 
964
                        evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
 
965
                        evo_data(push, 0x40000000);
 
966
                } else
 
967
                if (nv50_vers(mast) <  NVD0_DISP_MAST_CLASS) {
 
968
                        evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 
969
                        evo_data(push, 0x00000000);
 
970
                        evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
 
971
                        evo_data(push, 0x40000000);
 
972
                        evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
 
973
                        evo_data(push, 0x00000000);
 
974
                } else {
 
975
                        evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 
976
                        evo_data(push, 0x00000000);
 
977
                        evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
 
978
                        evo_data(push, 0x03000000);
 
979
                        evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 
980
                        evo_data(push, 0x00000000);
 
981
                }
 
982
 
 
983
                evo_kick(push, mast);
 
984
        }
 
985
 
 
986
        nv50_crtc_cursor_show_hide(nv_crtc, false, false);
 
987
}
 
988
 
 
989
static void
 
990
nv50_crtc_commit(struct drm_crtc *crtc)
 
991
{
 
992
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 
993
        struct nv50_mast *mast = nv50_mast(crtc->dev);
 
994
        u32 *push;
 
995
 
 
996
        push = evo_wait(mast, 32);
 
997
        if (push) {
 
998
                if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 
999
                        evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 
1000
                        evo_data(push, NvEvoVRAM_LP);
 
1001
                        evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
 
1002
                        evo_data(push, 0xc0000000);
 
1003
                        evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 
1004
                } else
 
1005
                if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 
1006
                        evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 
1007
                        evo_data(push, nv_crtc->fb.tile_flags);
 
1008
                        evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
 
1009
                        evo_data(push, 0xc0000000);
 
1010
                        evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 
1011
                        evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
 
1012
                        evo_data(push, NvEvoVRAM);
 
1013
                } else {
 
1014
                        evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 
1015
                        evo_data(push, nv_crtc->fb.tile_flags);
 
1016
                        evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
 
1017
                        evo_data(push, 0x83000000);
 
1018
                        evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 
1019
                        evo_data(push, 0x00000000);
 
1020
                        evo_data(push, 0x00000000);
 
1021
                        evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 
1022
                        evo_data(push, NvEvoVRAM);
 
1023
                        evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
 
1024
                        evo_data(push, 0xffffff00);
 
1025
                }
 
1026
 
 
1027
                evo_kick(push, mast);
 
1028
        }
 
1029
 
 
1030
        nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
 
1031
        nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
 
1032
}
 
1033
 
 
1034
static bool
 
1035
nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
 
1036
                     struct drm_display_mode *adjusted_mode)
 
1037
{
 
1038
        return true;
 
1039
}
 
1040
 
 
1041
static int
 
1042
nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
 
1043
{
 
1044
        struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
 
1045
        struct nv50_head *head = nv50_head(crtc);
 
1046
        int ret;
 
1047
 
 
1048
        ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
 
1049
        if (ret == 0) {
 
1050
                if (head->image)
 
1051
                        nouveau_bo_unpin(head->image);
 
1052
                nouveau_bo_ref(nvfb->nvbo, &head->image);
 
1053
        }
 
1054
 
 
1055
        return ret;
 
1056
}
 
1057
 
 
1058
static int
 
1059
nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
 
1060
                   struct drm_display_mode *mode, int x, int y,
 
1061
                   struct drm_framebuffer *old_fb)
 
1062
{
 
1063
        struct nv50_mast *mast = nv50_mast(crtc->dev);
 
1064
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 
1065
        struct nouveau_connector *nv_connector;
 
1066
        u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
 
1067
        u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
 
1068
        u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
 
1069
        u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
 
1070
        u32 vblan2e = 0, vblan2s = 1;
 
1071
        u32 *push;
 
1072
        int ret;
 
1073
 
 
1074
        hactive = mode->htotal;
 
1075
        hsynce  = mode->hsync_end - mode->hsync_start - 1;
 
1076
        hbackp  = mode->htotal - mode->hsync_end;
 
1077
        hblanke = hsynce + hbackp;
 
1078
        hfrontp = mode->hsync_start - mode->hdisplay;
 
1079
        hblanks = mode->htotal - hfrontp - 1;
 
1080
 
 
1081
        vactive = mode->vtotal * vscan / ilace;
 
1082
        vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
 
1083
        vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
 
1084
        vblanke = vsynce + vbackp;
 
1085
        vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
 
1086
        vblanks = vactive - vfrontp - 1;
 
1087
        if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 
1088
                vblan2e = vactive + vsynce + vbackp;
 
1089
                vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
 
1090
                vactive = (vactive * 2) + 1;
 
1091
        }
 
1092
 
 
1093
        ret = nv50_crtc_swap_fbs(crtc, old_fb);
 
1094
        if (ret)
 
1095
                return ret;
 
1096
 
 
1097
        push = evo_wait(mast, 64);
 
1098
        if (push) {
 
1099
                if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 
1100
                        evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
 
1101
                        evo_data(push, 0x00800000 | mode->clock);
 
1102
                        evo_data(push, (ilace == 2) ? 2 : 0);
 
1103
                        evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
 
1104
                        evo_data(push, 0x00000000);
 
1105
                        evo_data(push, (vactive << 16) | hactive);
 
1106
                        evo_data(push, ( vsynce << 16) | hsynce);
 
1107
                        evo_data(push, (vblanke << 16) | hblanke);
 
1108
                        evo_data(push, (vblanks << 16) | hblanks);
 
1109
                        evo_data(push, (vblan2e << 16) | vblan2s);
 
1110
                        evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
 
1111
                        evo_data(push, 0x00000000);
 
1112
                        evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
 
1113
                        evo_data(push, 0x00000311);
 
1114
                        evo_data(push, 0x00000100);
 
1115
                } else {
 
1116
                        evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
 
1117
                        evo_data(push, 0x00000000);
 
1118
                        evo_data(push, (vactive << 16) | hactive);
 
1119
                        evo_data(push, ( vsynce << 16) | hsynce);
 
1120
                        evo_data(push, (vblanke << 16) | hblanke);
 
1121
                        evo_data(push, (vblanks << 16) | hblanks);
 
1122
                        evo_data(push, (vblan2e << 16) | vblan2s);
 
1123
                        evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
 
1124
                        evo_data(push, 0x00000000); /* ??? */
 
1125
                        evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
 
1126
                        evo_data(push, mode->clock * 1000);
 
1127
                        evo_data(push, 0x00200000); /* ??? */
 
1128
                        evo_data(push, mode->clock * 1000);
 
1129
                        evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
 
1130
                        evo_data(push, 0x00000311);
 
1131
                        evo_data(push, 0x00000100);
 
1132
                }
 
1133
 
 
1134
                evo_kick(push, mast);
 
1135
        }
 
1136
 
 
1137
        nv_connector = nouveau_crtc_connector_get(nv_crtc);
 
1138
        nv50_crtc_set_dither(nv_crtc, false);
 
1139
        nv50_crtc_set_scale(nv_crtc, false);
 
1140
        nv50_crtc_set_color_vibrance(nv_crtc, false);
 
1141
        nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
 
1142
        return 0;
 
1143
}
 
1144
 
 
1145
static int
 
1146
nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 
1147
                        struct drm_framebuffer *old_fb)
 
1148
{
 
1149
        struct nouveau_drm *drm = nouveau_drm(crtc->dev);
 
1150
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 
1151
        int ret;
 
1152
 
 
1153
        if (!crtc->fb) {
 
1154
                NV_DEBUG(drm, "No FB bound\n");
 
1155
                return 0;
 
1156
        }
 
1157
 
 
1158
        ret = nv50_crtc_swap_fbs(crtc, old_fb);
 
1159
        if (ret)
 
1160
                return ret;
 
1161
 
 
1162
        nv50_display_flip_stop(crtc);
 
1163
        nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
 
1164
        nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
 
1165
        return 0;
 
1166
}
 
1167
 
 
1168
static int
 
1169
nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
 
1170
                               struct drm_framebuffer *fb, int x, int y,
 
1171
                               enum mode_set_atomic state)
 
1172
{
 
1173
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 
1174
        nv50_display_flip_stop(crtc);
 
1175
        nv50_crtc_set_image(nv_crtc, fb, x, y, true);
 
1176
        return 0;
 
1177
}
 
1178
 
 
1179
static void
 
1180
nv50_crtc_lut_load(struct drm_crtc *crtc)
 
1181
{
 
1182
        struct nv50_disp *disp = nv50_disp(crtc->dev);
 
1183
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 
1184
        void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
 
1185
        int i;
 
1186
 
 
1187
        for (i = 0; i < 256; i++) {
 
1188
                u16 r = nv_crtc->lut.r[i] >> 2;
 
1189
                u16 g = nv_crtc->lut.g[i] >> 2;
 
1190
                u16 b = nv_crtc->lut.b[i] >> 2;
 
1191
 
 
1192
                if (nv_mclass(disp->core) < NVD0_DISP_CLASS) {
 
1193
                        writew(r + 0x0000, lut + (i * 0x08) + 0);
 
1194
                        writew(g + 0x0000, lut + (i * 0x08) + 2);
 
1195
                        writew(b + 0x0000, lut + (i * 0x08) + 4);
 
1196
                } else {
 
1197
                        writew(r + 0x6000, lut + (i * 0x20) + 0);
 
1198
                        writew(g + 0x6000, lut + (i * 0x20) + 2);
 
1199
                        writew(b + 0x6000, lut + (i * 0x20) + 4);
 
1200
                }
 
1201
        }
 
1202
}
 
1203
 
 
1204
static void
 
1205
nv50_crtc_disable(struct drm_crtc *crtc)
 
1206
{
 
1207
        struct nv50_head *head = nv50_head(crtc);
 
1208
        if (head->image)
 
1209
                nouveau_bo_unpin(head->image);
 
1210
        nouveau_bo_ref(NULL, &head->image);
 
1211
}
 
1212
 
 
1213
static int
 
1214
nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
 
1215
                     uint32_t handle, uint32_t width, uint32_t height)
 
1216
{
 
1217
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 
1218
        struct drm_device *dev = crtc->dev;
 
1219
        struct drm_gem_object *gem;
 
1220
        struct nouveau_bo *nvbo;
 
1221
        bool visible = (handle != 0);
 
1222
        int i, ret = 0;
 
1223
 
 
1224
        if (visible) {
 
1225
                if (width != 64 || height != 64)
 
1226
                        return -EINVAL;
 
1227
 
 
1228
                gem = drm_gem_object_lookup(dev, file_priv, handle);
 
1229
                if (unlikely(!gem))
 
1230
                        return -ENOENT;
 
1231
                nvbo = nouveau_gem_object(gem);
 
1232
 
 
1233
                ret = nouveau_bo_map(nvbo);
 
1234
                if (ret == 0) {
 
1235
                        for (i = 0; i < 64 * 64; i++) {
 
1236
                                u32 v = nouveau_bo_rd32(nvbo, i);
 
1237
                                nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
 
1238
                        }
 
1239
                        nouveau_bo_unmap(nvbo);
 
1240
                }
 
1241
 
 
1242
                drm_gem_object_unreference_unlocked(gem);
 
1243
        }
 
1244
 
 
1245
        if (visible != nv_crtc->cursor.visible) {
 
1246
                nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
 
1247
                nv_crtc->cursor.visible = visible;
 
1248
        }
 
1249
 
 
1250
        return ret;
 
1251
}
 
1252
 
 
1253
static int
 
1254
nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 
1255
{
 
1256
        struct nv50_curs *curs = nv50_curs(crtc);
 
1257
        struct nv50_chan *chan = nv50_chan(curs);
 
1258
        nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff));
 
1259
        nv_wo32(chan->user, 0x0080, 0x00000000);
 
1260
        return 0;
 
1261
}
 
1262
 
 
1263
static void
 
1264
nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 
1265
                    uint32_t start, uint32_t size)
 
1266
{
 
1267
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 
1268
        u32 end = max(start + size, (u32)256);
 
1269
        u32 i;
 
1270
 
 
1271
        for (i = start; i < end; i++) {
 
1272
                nv_crtc->lut.r[i] = r[i];
 
1273
                nv_crtc->lut.g[i] = g[i];
 
1274
                nv_crtc->lut.b[i] = b[i];
 
1275
        }
 
1276
 
 
1277
        nv50_crtc_lut_load(crtc);
 
1278
}
 
1279
 
 
1280
static void
 
1281
nv50_crtc_destroy(struct drm_crtc *crtc)
 
1282
{
 
1283
        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 
1284
        struct nv50_disp *disp = nv50_disp(crtc->dev);
 
1285
        struct nv50_head *head = nv50_head(crtc);
 
1286
 
 
1287
        nv50_dmac_destroy(disp->core, &head->ovly.base);
 
1288
        nv50_pioc_destroy(disp->core, &head->oimm.base);
 
1289
        nv50_dmac_destroy(disp->core, &head->sync.base);
 
1290
        nv50_pioc_destroy(disp->core, &head->curs.base);
 
1291
 
 
1292
        /*XXX: this shouldn't be necessary, but the core doesn't call
 
1293
         *     disconnect() during the cleanup paths
 
1294
         */
 
1295
        if (head->image)
 
1296
                nouveau_bo_unpin(head->image);
 
1297
        nouveau_bo_ref(NULL, &head->image);
 
1298
 
 
1299
        nouveau_bo_unmap(nv_crtc->cursor.nvbo);
 
1300
        if (nv_crtc->cursor.nvbo)
 
1301
                nouveau_bo_unpin(nv_crtc->cursor.nvbo);
 
1302
        nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 
1303
 
 
1304
        nouveau_bo_unmap(nv_crtc->lut.nvbo);
 
1305
        if (nv_crtc->lut.nvbo)
 
1306
                nouveau_bo_unpin(nv_crtc->lut.nvbo);
 
1307
        nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 
1308
 
 
1309
        drm_crtc_cleanup(crtc);
 
1310
        kfree(crtc);
 
1311
}
 
1312
 
 
1313
static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
 
1314
        .dpms = nv50_crtc_dpms,
 
1315
        .prepare = nv50_crtc_prepare,
 
1316
        .commit = nv50_crtc_commit,
 
1317
        .mode_fixup = nv50_crtc_mode_fixup,
 
1318
        .mode_set = nv50_crtc_mode_set,
 
1319
        .mode_set_base = nv50_crtc_mode_set_base,
 
1320
        .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
 
1321
        .load_lut = nv50_crtc_lut_load,
 
1322
        .disable = nv50_crtc_disable,
 
1323
};
 
1324
 
 
1325
static const struct drm_crtc_funcs nv50_crtc_func = {
 
1326
        .cursor_set = nv50_crtc_cursor_set,
 
1327
        .cursor_move = nv50_crtc_cursor_move,
 
1328
        .gamma_set = nv50_crtc_gamma_set,
 
1329
        .set_config = drm_crtc_helper_set_config,
 
1330
        .destroy = nv50_crtc_destroy,
 
1331
        .page_flip = nouveau_crtc_page_flip,
 
1332
};
 
1333
 
 
1334
static void
 
1335
nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
 
1336
{
 
1337
}
 
1338
 
 
1339
static void
 
1340
nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
 
1341
{
 
1342
}
 
1343
 
 
1344
static int
 
1345
nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index)
 
1346
{
 
1347
        struct nv50_disp *disp = nv50_disp(dev);
 
1348
        struct nv50_head *head;
 
1349
        struct drm_crtc *crtc;
 
1350
        int ret, i;
 
1351
 
 
1352
        head = kzalloc(sizeof(*head), GFP_KERNEL);
 
1353
        if (!head)
 
1354
                return -ENOMEM;
 
1355
 
 
1356
        head->base.index = index;
 
1357
        head->base.set_dither = nv50_crtc_set_dither;
 
1358
        head->base.set_scale = nv50_crtc_set_scale;
 
1359
        head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
 
1360
        head->base.color_vibrance = 50;
 
1361
        head->base.vibrant_hue = 0;
 
1362
        head->base.cursor.set_offset = nv50_cursor_set_offset;
 
1363
        head->base.cursor.set_pos = nv50_cursor_set_pos;
 
1364
        for (i = 0; i < 256; i++) {
 
1365
                head->base.lut.r[i] = i << 8;
 
1366
                head->base.lut.g[i] = i << 8;
 
1367
                head->base.lut.b[i] = i << 8;
 
1368
        }
 
1369
 
 
1370
        crtc = &head->base.base;
 
1371
        drm_crtc_init(dev, crtc, &nv50_crtc_func);
 
1372
        drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
 
1373
        drm_mode_crtc_set_gamma_size(crtc, 256);
 
1374
 
 
1375
        ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
 
1376
                             0, 0x0000, NULL, &head->base.lut.nvbo);
 
1377
        if (!ret) {
 
1378
                ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
 
1379
                if (!ret) {
 
1380
                        ret = nouveau_bo_map(head->base.lut.nvbo);
 
1381
                        if (ret)
 
1382
                                nouveau_bo_unpin(head->base.lut.nvbo);
 
1383
                }
 
1384
                if (ret)
 
1385
                        nouveau_bo_ref(NULL, &head->base.lut.nvbo);
 
1386
        }
 
1387
 
 
1388
        if (ret)
 
1389
                goto out;
 
1390
 
 
1391
        nv50_crtc_lut_load(crtc);
 
1392
 
 
1393
        /* allocate cursor resources */
 
1394
        ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index,
 
1395
                              &(struct nv50_display_curs_class) {
 
1396
                                        .head = index,
 
1397
                              }, sizeof(struct nv50_display_curs_class),
 
1398
                              &head->curs.base);
 
1399
        if (ret)
 
1400
                goto out;
 
1401
 
 
1402
        ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
 
1403
                             0, 0x0000, NULL, &head->base.cursor.nvbo);
 
1404
        if (!ret) {
 
1405
                ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
 
1406
                if (!ret) {
 
1407
                        ret = nouveau_bo_map(head->base.cursor.nvbo);
 
1408
                        if (ret)
 
1409
                                nouveau_bo_unpin(head->base.lut.nvbo);
 
1410
                }
 
1411
                if (ret)
 
1412
                        nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
 
1413
        }
 
1414
 
 
1415
        if (ret)
 
1416
                goto out;
 
1417
 
 
1418
        /* allocate page flip / sync resources */
 
1419
        ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index,
 
1420
                              &(struct nv50_display_sync_class) {
 
1421
                                        .pushbuf = EVO_PUSH_HANDLE(SYNC, index),
 
1422
                                        .head = index,
 
1423
                              }, sizeof(struct nv50_display_sync_class),
 
1424
                              disp->sync->bo.offset, &head->sync.base);
 
1425
        if (ret)
 
1426
                goto out;
 
1427
 
 
1428
        head->sync.addr = EVO_FLIP_SEM0(index);
 
1429
        head->sync.data = 0x00000000;
 
1430
 
 
1431
        /* allocate overlay resources */
 
1432
        ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index,
 
1433
                              &(struct nv50_display_oimm_class) {
 
1434
                                        .head = index,
 
1435
                              }, sizeof(struct nv50_display_oimm_class),
 
1436
                              &head->oimm.base);
 
1437
        if (ret)
 
1438
                goto out;
 
1439
 
 
1440
        ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index,
 
1441
                              &(struct nv50_display_ovly_class) {
 
1442
                                        .pushbuf = EVO_PUSH_HANDLE(OVLY, index),
 
1443
                                        .head = index,
 
1444
                              }, sizeof(struct nv50_display_ovly_class),
 
1445
                              disp->sync->bo.offset, &head->ovly.base);
 
1446
        if (ret)
 
1447
                goto out;
 
1448
 
 
1449
out:
 
1450
        if (ret)
 
1451
                nv50_crtc_destroy(crtc);
 
1452
        return ret;
 
1453
}
 
1454
 
 
1455
/******************************************************************************
 
1456
 * DAC
 
1457
 *****************************************************************************/
 
1458
static void
 
1459
nv50_dac_dpms(struct drm_encoder *encoder, int mode)
 
1460
{
 
1461
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1462
        struct nv50_disp *disp = nv50_disp(encoder->dev);
 
1463
        int or = nv_encoder->or;
 
1464
        u32 dpms_ctrl;
 
1465
 
 
1466
        dpms_ctrl = 0x00000000;
 
1467
        if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
 
1468
                dpms_ctrl |= 0x00000001;
 
1469
        if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
 
1470
                dpms_ctrl |= 0x00000004;
 
1471
 
 
1472
        nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl);
 
1473
}
 
1474
 
 
1475
static bool
 
1476
nv50_dac_mode_fixup(struct drm_encoder *encoder,
 
1477
                    const struct drm_display_mode *mode,
 
1478
                    struct drm_display_mode *adjusted_mode)
 
1479
{
 
1480
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1481
        struct nouveau_connector *nv_connector;
 
1482
 
 
1483
        nv_connector = nouveau_encoder_connector_get(nv_encoder);
 
1484
        if (nv_connector && nv_connector->native_mode) {
 
1485
                if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 
1486
                        int id = adjusted_mode->base.id;
 
1487
                        *adjusted_mode = *nv_connector->native_mode;
 
1488
                        adjusted_mode->base.id = id;
 
1489
                }
 
1490
        }
 
1491
 
 
1492
        return true;
 
1493
}
 
1494
 
 
1495
static void
 
1496
nv50_dac_commit(struct drm_encoder *encoder)
 
1497
{
 
1498
}
 
1499
 
 
1500
static void
 
1501
nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 
1502
                  struct drm_display_mode *adjusted_mode)
 
1503
{
 
1504
        struct nv50_mast *mast = nv50_mast(encoder->dev);
 
1505
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1506
        struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 
1507
        u32 *push;
 
1508
 
 
1509
        nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 
1510
 
 
1511
        push = evo_wait(mast, 8);
 
1512
        if (push) {
 
1513
                if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 
1514
                        u32 syncs = 0x00000000;
 
1515
 
 
1516
                        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 
1517
                                syncs |= 0x00000001;
 
1518
                        if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 
1519
                                syncs |= 0x00000002;
 
1520
 
 
1521
                        evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
 
1522
                        evo_data(push, 1 << nv_crtc->index);
 
1523
                        evo_data(push, syncs);
 
1524
                } else {
 
1525
                        u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
 
1526
                        u32 syncs = 0x00000001;
 
1527
 
 
1528
                        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 
1529
                                syncs |= 0x00000008;
 
1530
                        if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 
1531
                                syncs |= 0x00000010;
 
1532
 
 
1533
                        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 
1534
                                magic |= 0x00000001;
 
1535
 
 
1536
                        evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
 
1537
                        evo_data(push, syncs);
 
1538
                        evo_data(push, magic);
 
1539
                        evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
 
1540
                        evo_data(push, 1 << nv_crtc->index);
 
1541
                }
 
1542
 
 
1543
                evo_kick(push, mast);
 
1544
        }
 
1545
 
 
1546
        nv_encoder->crtc = encoder->crtc;
 
1547
}
 
1548
 
 
1549
static void
 
1550
nv50_dac_disconnect(struct drm_encoder *encoder)
 
1551
{
 
1552
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1553
        struct nv50_mast *mast = nv50_mast(encoder->dev);
 
1554
        const int or = nv_encoder->or;
 
1555
        u32 *push;
 
1556
 
 
1557
        if (nv_encoder->crtc) {
 
1558
                nv50_crtc_prepare(nv_encoder->crtc);
 
1559
 
 
1560
                push = evo_wait(mast, 4);
 
1561
                if (push) {
 
1562
                        if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 
1563
                                evo_mthd(push, 0x0400 + (or * 0x080), 1);
 
1564
                                evo_data(push, 0x00000000);
 
1565
                        } else {
 
1566
                                evo_mthd(push, 0x0180 + (or * 0x020), 1);
 
1567
                                evo_data(push, 0x00000000);
 
1568
                        }
 
1569
                        evo_kick(push, mast);
 
1570
                }
 
1571
        }
 
1572
 
 
1573
        nv_encoder->crtc = NULL;
 
1574
}
 
1575
 
 
1576
static enum drm_connector_status
 
1577
nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 
1578
{
 
1579
        struct nv50_disp *disp = nv50_disp(encoder->dev);
 
1580
        int ret, or = nouveau_encoder(encoder)->or;
 
1581
        u32 load = nouveau_drm(encoder->dev)->vbios.dactestval;
 
1582
        if (load == 0)
 
1583
                load = 340;
 
1584
 
 
1585
        ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
 
1586
        if (ret || load != 7)
 
1587
                return connector_status_disconnected;
 
1588
 
 
1589
        return connector_status_connected;
 
1590
}
 
1591
 
 
1592
static void
 
1593
nv50_dac_destroy(struct drm_encoder *encoder)
 
1594
{
 
1595
        drm_encoder_cleanup(encoder);
 
1596
        kfree(encoder);
 
1597
}
 
1598
 
 
1599
static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
 
1600
        .dpms = nv50_dac_dpms,
 
1601
        .mode_fixup = nv50_dac_mode_fixup,
 
1602
        .prepare = nv50_dac_disconnect,
 
1603
        .commit = nv50_dac_commit,
 
1604
        .mode_set = nv50_dac_mode_set,
 
1605
        .disable = nv50_dac_disconnect,
 
1606
        .get_crtc = nv50_display_crtc_get,
 
1607
        .detect = nv50_dac_detect
 
1608
};
 
1609
 
 
1610
static const struct drm_encoder_funcs nv50_dac_func = {
 
1611
        .destroy = nv50_dac_destroy,
 
1612
};
 
1613
 
 
1614
static int
 
1615
nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 
1616
{
 
1617
        struct nouveau_drm *drm = nouveau_drm(connector->dev);
 
1618
        struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
 
1619
        struct nouveau_encoder *nv_encoder;
 
1620
        struct drm_encoder *encoder;
 
1621
        int type = DRM_MODE_ENCODER_DAC;
 
1622
 
 
1623
        nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 
1624
        if (!nv_encoder)
 
1625
                return -ENOMEM;
 
1626
        nv_encoder->dcb = dcbe;
 
1627
        nv_encoder->or = ffs(dcbe->or) - 1;
 
1628
        nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
 
1629
 
 
1630
        encoder = to_drm_encoder(nv_encoder);
 
1631
        encoder->possible_crtcs = dcbe->heads;
 
1632
        encoder->possible_clones = 0;
 
1633
        drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
 
1634
        drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
 
1635
 
 
1636
        drm_mode_connector_attach_encoder(connector, encoder);
 
1637
        return 0;
 
1638
}
 
1639
 
 
1640
/******************************************************************************
 
1641
 * Audio
 
1642
 *****************************************************************************/
 
1643
static void
 
1644
nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
 
1645
{
 
1646
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1647
        struct nouveau_connector *nv_connector;
 
1648
        struct nv50_disp *disp = nv50_disp(encoder->dev);
 
1649
 
 
1650
        nv_connector = nouveau_encoder_connector_get(nv_encoder);
 
1651
        if (!drm_detect_monitor_audio(nv_connector->edid))
 
1652
                return;
 
1653
 
 
1654
        drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
 
1655
 
 
1656
        nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or,
 
1657
                            nv_connector->base.eld,
 
1658
                            nv_connector->base.eld[2] * 4);
 
1659
}
 
1660
 
 
1661
static void
 
1662
nv50_audio_disconnect(struct drm_encoder *encoder)
 
1663
{
 
1664
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1665
        struct nv50_disp *disp = nv50_disp(encoder->dev);
 
1666
 
 
1667
        nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0);
 
1668
}
 
1669
 
 
1670
/******************************************************************************
 
1671
 * HDMI
 
1672
 *****************************************************************************/
 
1673
static void
 
1674
nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
 
1675
{
 
1676
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1677
        struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 
1678
        struct nouveau_connector *nv_connector;
 
1679
        struct nv50_disp *disp = nv50_disp(encoder->dev);
 
1680
        const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
 
1681
        u32 rekey = 56; /* binary driver, and tegra constant */
 
1682
        u32 max_ac_packet;
 
1683
 
 
1684
        nv_connector = nouveau_encoder_connector_get(nv_encoder);
 
1685
        if (!drm_detect_hdmi_monitor(nv_connector->edid))
 
1686
                return;
 
1687
 
 
1688
        max_ac_packet  = mode->htotal - mode->hdisplay;
 
1689
        max_ac_packet -= rekey;
 
1690
        max_ac_packet -= 18; /* constant from tegra */
 
1691
        max_ac_packet /= 32;
 
1692
 
 
1693
        nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff,
 
1694
                            NV84_DISP_SOR_HDMI_PWR_STATE_ON |
 
1695
                            (max_ac_packet << 16) | rekey);
 
1696
 
 
1697
        nv50_audio_mode_set(encoder, mode);
 
1698
}
 
1699
 
 
1700
static void
 
1701
nv50_hdmi_disconnect(struct drm_encoder *encoder)
 
1702
{
 
1703
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1704
        struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
 
1705
        struct nv50_disp *disp = nv50_disp(encoder->dev);
 
1706
        const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
 
1707
 
 
1708
        nv50_audio_disconnect(encoder);
 
1709
 
 
1710
        nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000);
 
1711
}
 
1712
 
 
1713
/******************************************************************************
 
1714
 * SOR
 
1715
 *****************************************************************************/
 
1716
static void
 
1717
nv50_sor_dpms(struct drm_encoder *encoder, int mode)
 
1718
{
 
1719
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1720
        struct drm_device *dev = encoder->dev;
 
1721
        struct nv50_disp *disp = nv50_disp(dev);
 
1722
        struct drm_encoder *partner;
 
1723
        int or = nv_encoder->or;
 
1724
 
 
1725
        nv_encoder->last_dpms = mode;
 
1726
 
 
1727
        list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
 
1728
                struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
 
1729
 
 
1730
                if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
 
1731
                        continue;
 
1732
 
 
1733
                if (nv_partner != nv_encoder &&
 
1734
                    nv_partner->dcb->or == nv_encoder->dcb->or) {
 
1735
                        if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
 
1736
                                return;
 
1737
                        break;
 
1738
                }
 
1739
        }
 
1740
 
 
1741
        nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON));
 
1742
}
 
1743
 
 
1744
static bool
 
1745
nv50_sor_mode_fixup(struct drm_encoder *encoder,
 
1746
                    const struct drm_display_mode *mode,
 
1747
                    struct drm_display_mode *adjusted_mode)
 
1748
{
 
1749
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1750
        struct nouveau_connector *nv_connector;
 
1751
 
 
1752
        nv_connector = nouveau_encoder_connector_get(nv_encoder);
 
1753
        if (nv_connector && nv_connector->native_mode) {
 
1754
                if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 
1755
                        int id = adjusted_mode->base.id;
 
1756
                        *adjusted_mode = *nv_connector->native_mode;
 
1757
                        adjusted_mode->base.id = id;
 
1758
                }
 
1759
        }
 
1760
 
 
1761
        return true;
 
1762
}
 
1763
 
 
1764
static void
 
1765
nv50_sor_disconnect(struct drm_encoder *encoder)
 
1766
{
 
1767
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1768
        struct nv50_mast *mast = nv50_mast(encoder->dev);
 
1769
        const int or = nv_encoder->or;
 
1770
        u32 *push;
 
1771
 
 
1772
        if (nv_encoder->crtc) {
 
1773
                nv50_crtc_prepare(nv_encoder->crtc);
 
1774
 
 
1775
                push = evo_wait(mast, 4);
 
1776
                if (push) {
 
1777
                        if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 
1778
                                evo_mthd(push, 0x0600 + (or * 0x40), 1);
 
1779
                                evo_data(push, 0x00000000);
 
1780
                        } else {
 
1781
                                evo_mthd(push, 0x0200 + (or * 0x20), 1);
 
1782
                                evo_data(push, 0x00000000);
 
1783
                        }
 
1784
                        evo_kick(push, mast);
 
1785
                }
 
1786
 
 
1787
                nv50_hdmi_disconnect(encoder);
 
1788
        }
 
1789
 
 
1790
        nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
 
1791
        nv_encoder->crtc = NULL;
 
1792
}
 
1793
 
 
1794
static void
 
1795
nv50_sor_commit(struct drm_encoder *encoder)
 
1796
{
 
1797
}
 
1798
 
 
1799
static void
 
1800
nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
 
1801
                  struct drm_display_mode *mode)
 
1802
{
 
1803
        struct nv50_disp *disp = nv50_disp(encoder->dev);
 
1804
        struct nv50_mast *mast = nv50_mast(encoder->dev);
 
1805
        struct drm_device *dev = encoder->dev;
 
1806
        struct nouveau_drm *drm = nouveau_drm(dev);
 
1807
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1808
        struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 
1809
        struct nouveau_connector *nv_connector;
 
1810
        struct nvbios *bios = &drm->vbios;
 
1811
        u32 *push, lvds = 0;
 
1812
        u8 owner = 1 << nv_crtc->index;
 
1813
        u8 proto = 0xf;
 
1814
        u8 depth = 0x0;
 
1815
 
 
1816
        nv_connector = nouveau_encoder_connector_get(nv_encoder);
 
1817
        switch (nv_encoder->dcb->type) {
 
1818
        case DCB_OUTPUT_TMDS:
 
1819
                if (nv_encoder->dcb->sorconf.link & 1) {
 
1820
                        if (mode->clock < 165000)
 
1821
                                proto = 0x1;
 
1822
                        else
 
1823
                                proto = 0x5;
 
1824
                } else {
 
1825
                        proto = 0x2;
 
1826
                }
 
1827
 
 
1828
                nv50_hdmi_mode_set(encoder, mode);
 
1829
                break;
 
1830
        case DCB_OUTPUT_LVDS:
 
1831
                proto = 0x0;
 
1832
 
 
1833
                if (bios->fp_no_ddc) {
 
1834
                        if (bios->fp.dual_link)
 
1835
                                lvds |= 0x0100;
 
1836
                        if (bios->fp.if_is_24bit)
 
1837
                                lvds |= 0x0200;
 
1838
                } else {
 
1839
                        if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
 
1840
                                if (((u8 *)nv_connector->edid)[121] == 2)
 
1841
                                        lvds |= 0x0100;
 
1842
                        } else
 
1843
                        if (mode->clock >= bios->fp.duallink_transition_clk) {
 
1844
                                lvds |= 0x0100;
 
1845
                        }
 
1846
 
 
1847
                        if (lvds & 0x0100) {
 
1848
                                if (bios->fp.strapless_is_24bit & 2)
 
1849
                                        lvds |= 0x0200;
 
1850
                        } else {
 
1851
                                if (bios->fp.strapless_is_24bit & 1)
 
1852
                                        lvds |= 0x0200;
 
1853
                        }
 
1854
 
 
1855
                        if (nv_connector->base.display_info.bpc == 8)
 
1856
                                lvds |= 0x0200;
 
1857
                }
 
1858
 
 
1859
                nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds);
 
1860
                break;
 
1861
        case DCB_OUTPUT_DP:
 
1862
                if (nv_connector->base.display_info.bpc == 6) {
 
1863
                        nv_encoder->dp.datarate = mode->clock * 18 / 8;
 
1864
                        depth = 0x2;
 
1865
                } else
 
1866
                if (nv_connector->base.display_info.bpc == 8) {
 
1867
                        nv_encoder->dp.datarate = mode->clock * 24 / 8;
 
1868
                        depth = 0x5;
 
1869
                } else {
 
1870
                        nv_encoder->dp.datarate = mode->clock * 30 / 8;
 
1871
                        depth = 0x6;
 
1872
                }
 
1873
 
 
1874
                if (nv_encoder->dcb->sorconf.link & 1)
 
1875
                        proto = 0x8;
 
1876
                else
 
1877
                        proto = 0x9;
 
1878
                break;
 
1879
        default:
 
1880
                BUG_ON(1);
 
1881
                break;
 
1882
        }
 
1883
 
 
1884
        nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
 
1885
 
 
1886
        push = evo_wait(nv50_mast(dev), 8);
 
1887
        if (push) {
 
1888
                if (nv50_vers(mast) < NVD0_DISP_CLASS) {
 
1889
                        u32 ctrl = (depth << 16) | (proto << 8) | owner;
 
1890
                        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 
1891
                                ctrl |= 0x00001000;
 
1892
                        if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 
1893
                                ctrl |= 0x00002000;
 
1894
                        evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1);
 
1895
                        evo_data(push, ctrl);
 
1896
                } else {
 
1897
                        u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
 
1898
                        u32 syncs = 0x00000001;
 
1899
 
 
1900
                        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 
1901
                                syncs |= 0x00000008;
 
1902
                        if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 
1903
                                syncs |= 0x00000010;
 
1904
 
 
1905
                        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 
1906
                                magic |= 0x00000001;
 
1907
 
 
1908
                        evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
 
1909
                        evo_data(push, syncs | (depth << 6));
 
1910
                        evo_data(push, magic);
 
1911
                        evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1);
 
1912
                        evo_data(push, owner | (proto << 8));
 
1913
                }
 
1914
 
 
1915
                evo_kick(push, mast);
 
1916
        }
 
1917
 
 
1918
        nv_encoder->crtc = encoder->crtc;
 
1919
}
 
1920
 
 
1921
static void
 
1922
nv50_sor_destroy(struct drm_encoder *encoder)
 
1923
{
 
1924
        drm_encoder_cleanup(encoder);
 
1925
        kfree(encoder);
 
1926
}
 
1927
 
 
1928
static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
 
1929
        .dpms = nv50_sor_dpms,
 
1930
        .mode_fixup = nv50_sor_mode_fixup,
 
1931
        .prepare = nv50_sor_disconnect,
 
1932
        .commit = nv50_sor_commit,
 
1933
        .mode_set = nv50_sor_mode_set,
 
1934
        .disable = nv50_sor_disconnect,
 
1935
        .get_crtc = nv50_display_crtc_get,
 
1936
};
 
1937
 
 
1938
static const struct drm_encoder_funcs nv50_sor_func = {
 
1939
        .destroy = nv50_sor_destroy,
 
1940
};
 
1941
 
 
1942
static int
 
1943
nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
 
1944
{
 
1945
        struct nouveau_drm *drm = nouveau_drm(connector->dev);
 
1946
        struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
 
1947
        struct nouveau_encoder *nv_encoder;
 
1948
        struct drm_encoder *encoder;
 
1949
        int type;
 
1950
 
 
1951
        switch (dcbe->type) {
 
1952
        case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
 
1953
        case DCB_OUTPUT_TMDS:
 
1954
        case DCB_OUTPUT_DP:
 
1955
        default:
 
1956
                type = DRM_MODE_ENCODER_TMDS;
 
1957
                break;
 
1958
        }
 
1959
 
 
1960
        nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 
1961
        if (!nv_encoder)
 
1962
                return -ENOMEM;
 
1963
        nv_encoder->dcb = dcbe;
 
1964
        nv_encoder->or = ffs(dcbe->or) - 1;
 
1965
        nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
 
1966
        nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
 
1967
 
 
1968
        encoder = to_drm_encoder(nv_encoder);
 
1969
        encoder->possible_crtcs = dcbe->heads;
 
1970
        encoder->possible_clones = 0;
 
1971
        drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
 
1972
        drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
 
1973
 
 
1974
        drm_mode_connector_attach_encoder(connector, encoder);
 
1975
        return 0;
 
1976
}
 
1977
 
 
1978
/******************************************************************************
 
1979
 * PIOR
 
1980
 *****************************************************************************/
 
1981
 
 
1982
static void
 
1983
nv50_pior_dpms(struct drm_encoder *encoder, int mode)
 
1984
{
 
1985
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1986
        struct nv50_disp *disp = nv50_disp(encoder->dev);
 
1987
        u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or;
 
1988
        u32 ctrl = (mode == DRM_MODE_DPMS_ON);
 
1989
        nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl);
 
1990
}
 
1991
 
 
1992
static bool
 
1993
nv50_pior_mode_fixup(struct drm_encoder *encoder,
 
1994
                     const struct drm_display_mode *mode,
 
1995
                     struct drm_display_mode *adjusted_mode)
 
1996
{
 
1997
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
1998
        struct nouveau_connector *nv_connector;
 
1999
 
 
2000
        nv_connector = nouveau_encoder_connector_get(nv_encoder);
 
2001
        if (nv_connector && nv_connector->native_mode) {
 
2002
                if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 
2003
                        int id = adjusted_mode->base.id;
 
2004
                        *adjusted_mode = *nv_connector->native_mode;
 
2005
                        adjusted_mode->base.id = id;
 
2006
                }
 
2007
        }
 
2008
 
 
2009
        adjusted_mode->clock *= 2;
 
2010
        return true;
 
2011
}
 
2012
 
 
2013
static void
 
2014
nv50_pior_commit(struct drm_encoder *encoder)
 
2015
{
 
2016
}
 
2017
 
 
2018
static void
 
2019
nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 
2020
                   struct drm_display_mode *adjusted_mode)
 
2021
{
 
2022
        struct nv50_mast *mast = nv50_mast(encoder->dev);
 
2023
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
2024
        struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 
2025
        struct nouveau_connector *nv_connector;
 
2026
        u8 owner = 1 << nv_crtc->index;
 
2027
        u8 proto, depth;
 
2028
        u32 *push;
 
2029
 
 
2030
        nv_connector = nouveau_encoder_connector_get(nv_encoder);
 
2031
        switch (nv_connector->base.display_info.bpc) {
 
2032
        case 10: depth = 0x6; break;
 
2033
        case  8: depth = 0x5; break;
 
2034
        case  6: depth = 0x2; break;
 
2035
        default: depth = 0x0; break;
 
2036
        }
 
2037
 
 
2038
        switch (nv_encoder->dcb->type) {
 
2039
        case DCB_OUTPUT_TMDS:
 
2040
        case DCB_OUTPUT_DP:
 
2041
                proto = 0x0;
 
2042
                break;
 
2043
        default:
 
2044
                BUG_ON(1);
 
2045
                break;
 
2046
        }
 
2047
 
 
2048
        nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
 
2049
 
 
2050
        push = evo_wait(mast, 8);
 
2051
        if (push) {
 
2052
                if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 
2053
                        u32 ctrl = (depth << 16) | (proto << 8) | owner;
 
2054
                        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 
2055
                                ctrl |= 0x00001000;
 
2056
                        if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 
2057
                                ctrl |= 0x00002000;
 
2058
                        evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
 
2059
                        evo_data(push, ctrl);
 
2060
                }
 
2061
 
 
2062
                evo_kick(push, mast);
 
2063
        }
 
2064
 
 
2065
        nv_encoder->crtc = encoder->crtc;
 
2066
}
 
2067
 
 
2068
static void
 
2069
nv50_pior_disconnect(struct drm_encoder *encoder)
 
2070
{
 
2071
        struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 
2072
        struct nv50_mast *mast = nv50_mast(encoder->dev);
 
2073
        const int or = nv_encoder->or;
 
2074
        u32 *push;
 
2075
 
 
2076
        if (nv_encoder->crtc) {
 
2077
                nv50_crtc_prepare(nv_encoder->crtc);
 
2078
 
 
2079
                push = evo_wait(mast, 4);
 
2080
                if (push) {
 
2081
                        if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 
2082
                                evo_mthd(push, 0x0700 + (or * 0x040), 1);
 
2083
                                evo_data(push, 0x00000000);
 
2084
                        }
 
2085
                        evo_kick(push, mast);
 
2086
                }
 
2087
        }
 
2088
 
 
2089
        nv_encoder->crtc = NULL;
 
2090
}
 
2091
 
 
2092
static void
 
2093
nv50_pior_destroy(struct drm_encoder *encoder)
 
2094
{
 
2095
        drm_encoder_cleanup(encoder);
 
2096
        kfree(encoder);
 
2097
}
 
2098
 
 
2099
static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
 
2100
        .dpms = nv50_pior_dpms,
 
2101
        .mode_fixup = nv50_pior_mode_fixup,
 
2102
        .prepare = nv50_pior_disconnect,
 
2103
        .commit = nv50_pior_commit,
 
2104
        .mode_set = nv50_pior_mode_set,
 
2105
        .disable = nv50_pior_disconnect,
 
2106
        .get_crtc = nv50_display_crtc_get,
 
2107
};
 
2108
 
 
2109
static const struct drm_encoder_funcs nv50_pior_func = {
 
2110
        .destroy = nv50_pior_destroy,
 
2111
};
 
2112
 
 
2113
static int
 
2114
nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
 
2115
{
 
2116
        struct nouveau_drm *drm = nouveau_drm(connector->dev);
 
2117
        struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
 
2118
        struct nouveau_i2c_port *ddc = NULL;
 
2119
        struct nouveau_encoder *nv_encoder;
 
2120
        struct drm_encoder *encoder;
 
2121
        int type;
 
2122
 
 
2123
        switch (dcbe->type) {
 
2124
        case DCB_OUTPUT_TMDS:
 
2125
                ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
 
2126
                type = DRM_MODE_ENCODER_TMDS;
 
2127
                break;
 
2128
        case DCB_OUTPUT_DP:
 
2129
                ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
 
2130
                type = DRM_MODE_ENCODER_TMDS;
 
2131
                break;
 
2132
        default:
 
2133
                return -ENODEV;
 
2134
        }
 
2135
 
 
2136
        nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 
2137
        if (!nv_encoder)
 
2138
                return -ENOMEM;
 
2139
        nv_encoder->dcb = dcbe;
 
2140
        nv_encoder->or = ffs(dcbe->or) - 1;
 
2141
        nv_encoder->i2c = ddc;
 
2142
 
 
2143
        encoder = to_drm_encoder(nv_encoder);
 
2144
        encoder->possible_crtcs = dcbe->heads;
 
2145
        encoder->possible_clones = 0;
 
2146
        drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
 
2147
        drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
 
2148
 
 
2149
        drm_mode_connector_attach_encoder(connector, encoder);
 
2150
        return 0;
 
2151
}
 
2152
 
 
2153
/******************************************************************************
 
2154
 * Init
 
2155
 *****************************************************************************/
 
2156
void
 
2157
nv50_display_fini(struct drm_device *dev)
 
2158
{
 
2159
}
 
2160
 
 
2161
int
 
2162
nv50_display_init(struct drm_device *dev)
 
2163
{
 
2164
        struct nv50_disp *disp = nv50_disp(dev);
 
2165
        struct drm_crtc *crtc;
 
2166
        u32 *push;
 
2167
 
 
2168
        push = evo_wait(nv50_mast(dev), 32);
 
2169
        if (!push)
 
2170
                return -EBUSY;
 
2171
 
 
2172
        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 
2173
                struct nv50_sync *sync = nv50_sync(crtc);
 
2174
                nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
 
2175
        }
 
2176
 
 
2177
        evo_mthd(push, 0x0088, 1);
 
2178
        evo_data(push, NvEvoSync);
 
2179
        evo_kick(push, nv50_mast(dev));
 
2180
        return 0;
 
2181
}
 
2182
 
 
2183
void
 
2184
nv50_display_destroy(struct drm_device *dev)
 
2185
{
 
2186
        struct nv50_disp *disp = nv50_disp(dev);
 
2187
 
 
2188
        nv50_dmac_destroy(disp->core, &disp->mast.base);
 
2189
 
 
2190
        nouveau_bo_unmap(disp->sync);
 
2191
        if (disp->sync)
 
2192
                nouveau_bo_unpin(disp->sync);
 
2193
        nouveau_bo_ref(NULL, &disp->sync);
 
2194
 
 
2195
        nouveau_display(dev)->priv = NULL;
 
2196
        kfree(disp);
 
2197
}
 
2198
 
 
2199
int
 
2200
nv50_display_create(struct drm_device *dev)
 
2201
{
 
2202
        static const u16 oclass[] = {
 
2203
                NVF0_DISP_CLASS,
 
2204
                NVE0_DISP_CLASS,
 
2205
                NVD0_DISP_CLASS,
 
2206
                NVA3_DISP_CLASS,
 
2207
                NV94_DISP_CLASS,
 
2208
                NVA0_DISP_CLASS,
 
2209
                NV84_DISP_CLASS,
 
2210
                NV50_DISP_CLASS,
 
2211
        };
 
2212
        struct nouveau_device *device = nouveau_dev(dev);
 
2213
        struct nouveau_drm *drm = nouveau_drm(dev);
 
2214
        struct dcb_table *dcb = &drm->vbios.dcb;
 
2215
        struct drm_connector *connector, *tmp;
 
2216
        struct nv50_disp *disp;
 
2217
        struct dcb_output *dcbe;
 
2218
        int crtcs, ret, i;
 
2219
 
 
2220
        disp = kzalloc(sizeof(*disp), GFP_KERNEL);
 
2221
        if (!disp)
 
2222
                return -ENOMEM;
 
2223
 
 
2224
        nouveau_display(dev)->priv = disp;
 
2225
        nouveau_display(dev)->dtor = nv50_display_destroy;
 
2226
        nouveau_display(dev)->init = nv50_display_init;
 
2227
        nouveau_display(dev)->fini = nv50_display_fini;
 
2228
 
 
2229
        /* small shared memory area we use for notifiers and semaphores */
 
2230
        ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
 
2231
                             0, 0x0000, NULL, &disp->sync);
 
2232
        if (!ret) {
 
2233
                ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
 
2234
                if (!ret) {
 
2235
                        ret = nouveau_bo_map(disp->sync);
 
2236
                        if (ret)
 
2237
                                nouveau_bo_unpin(disp->sync);
 
2238
                }
 
2239
                if (ret)
 
2240
                        nouveau_bo_ref(NULL, &disp->sync);
 
2241
        }
 
2242
 
 
2243
        if (ret)
 
2244
                goto out;
 
2245
 
 
2246
        /* attempt to allocate a supported evo display class */
 
2247
        ret = -ENODEV;
 
2248
        for (i = 0; ret && i < ARRAY_SIZE(oclass); i++) {
 
2249
                ret = nouveau_object_new(nv_object(drm), NVDRM_DEVICE,
 
2250
                                         0xd1500000, oclass[i], NULL, 0,
 
2251
                                         &disp->core);
 
2252
        }
 
2253
 
 
2254
        if (ret)
 
2255
                goto out;
 
2256
 
 
2257
        /* allocate master evo channel */
 
2258
        ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0,
 
2259
                              &(struct nv50_display_mast_class) {
 
2260
                                        .pushbuf = EVO_PUSH_HANDLE(MAST, 0),
 
2261
                              }, sizeof(struct nv50_display_mast_class),
 
2262
                              disp->sync->bo.offset, &disp->mast.base);
 
2263
        if (ret)
 
2264
                goto out;
 
2265
 
 
2266
        /* create crtc objects to represent the hw heads */
 
2267
        if (nv_mclass(disp->core) >= NVD0_DISP_CLASS)
 
2268
                crtcs = nv_rd32(device, 0x022448);
 
2269
        else
 
2270
                crtcs = 2;
 
2271
 
 
2272
        for (i = 0; i < crtcs; i++) {
 
2273
                ret = nv50_crtc_create(dev, disp->core, i);
 
2274
                if (ret)
 
2275
                        goto out;
 
2276
        }
 
2277
 
 
2278
        /* create encoder/connector objects based on VBIOS DCB table */
 
2279
        for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
 
2280
                connector = nouveau_connector_create(dev, dcbe->connector);
 
2281
                if (IS_ERR(connector))
 
2282
                        continue;
 
2283
 
 
2284
                if (dcbe->location == DCB_LOC_ON_CHIP) {
 
2285
                        switch (dcbe->type) {
 
2286
                        case DCB_OUTPUT_TMDS:
 
2287
                        case DCB_OUTPUT_LVDS:
 
2288
                        case DCB_OUTPUT_DP:
 
2289
                                ret = nv50_sor_create(connector, dcbe);
 
2290
                                break;
 
2291
                        case DCB_OUTPUT_ANALOG:
 
2292
                                ret = nv50_dac_create(connector, dcbe);
 
2293
                                break;
 
2294
                        default:
 
2295
                                ret = -ENODEV;
 
2296
                                break;
 
2297
                        }
 
2298
                } else {
 
2299
                        ret = nv50_pior_create(connector, dcbe);
 
2300
                }
 
2301
 
 
2302
                if (ret) {
 
2303
                        NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
 
2304
                                     dcbe->location, dcbe->type,
 
2305
                                     ffs(dcbe->or) - 1, ret);
 
2306
                        ret = 0;
 
2307
                }
 
2308
        }
 
2309
 
 
2310
        /* cull any connectors we created that don't have an encoder */
 
2311
        list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
 
2312
                if (connector->encoder_ids[0])
 
2313
                        continue;
 
2314
 
 
2315
                NV_WARN(drm, "%s has no encoders, removing\n",
 
2316
                        drm_get_connector_name(connector));
 
2317
                connector->funcs->destroy(connector);
 
2318
        }
 
2319
 
 
2320
out:
 
2321
        if (ret)
 
2322
                nv50_display_destroy(dev);
 
2323
        return ret;
 
2324
}