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OPENSSL_ia32cap - finding the IA-32 processor capabilities
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unsigned long *OPENSSL_ia32cap_loc(void);
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#define OPENSSL_ia32cap (*(OPENSSL_ia32cap_loc()))
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Value returned by OPENSSL_ia32cap_loc() is address of a variable
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containing IA-32 processor capabilities bit vector as it appears in EDX
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register after executing CPUID instruction with EAX=1 input value (see
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Intel Application Note #241618). Naturally it's meaningful on IA-32[E]
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platforms only. The variable is normally set up automatically upon
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toolkit initialization, but can be manipulated afterwards to modify
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crypto library behaviour. For the moment of this writing six bits are
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1. bit #28 denoting Hyperthreading, which is used to distiguish
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cores with shared cache;
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2. bit #26 denoting SSE2 support;
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3. bit #25 denoting SSE support;
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4. bit #23 denoting MMX support;
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5. bit #20, reserved by Intel, is used to choose between RC4 code
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6. bit #4 denoting presence of Time-Stamp Counter.
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For example, clearing bit #26 at run-time disables high-performance
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SSE2 code present in the crypto library. You might have to do this if
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target OpenSSL application is executed on SSE2 capable CPU, but under
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control of OS which does not support SSE2 extentions. Even though you
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can manipulate the value programmatically, you most likely will find it
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more appropriate to set up an environment variable with the same name
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prior starting target application, e.g. on Intel P4 processor 'env
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OPENSSL_ia32cap=0x12900010 apps/openssl', to achieve same effect
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without modifying the application source code. Alternatively you can
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reconfigure the toolkit with no-sse2 option and recompile.